MICROCHIP 93AA86A, 93AA86B, 93AA86C, 93LC86A, 93LC86B Technical data

...

93AA86A/B/C, 93LC86A/B/C,

93C86A/B/C

16K Microwire Compatible Serial EEPROM

Device Selection Table

Part Number VCC Range ORG Pin PE Pin Word Size Temp Ranges Packages

93AA86A 1.8-5.5 No No 8-bit I OT 93AA86B 1.8-5-5 No No 16-bit I OT 93LC86A 2.5-5.5 No No 8-bit I, E OT 93LC86B 2.5-5.5 No No 16-bit I, E OT 93C86A 4.5-5.5 No No 8-bit I, E OT 93C86B 4.5-5.5 No No 16-bit I, E OT 93AA86C 1.8-5.5 Yes Yes 8 or 16-bit I P, SN, ST, MS, MC 93LC86C 2.5-5.5 Yes Yes 8 or 16-bit I, E P, SN, ST, MS, MC 93C86C 4.5-5.5 Yes Yes 8 or 16-bit I, E P, SN, ST, MS, MC

Features:

• Low-power CMOS technology

• ORG pin to select word size for ‘86C’ version

• 2048 x 8-bit organization ‘A’ devices (no ORG)

• 1024 x 16-bit organization ‘B’ devices (no ORG)

• Program Enable pin to write-protect the entire array (‘86C’ version only)

• Self-timed erase/write cycles (including auto-erase)

• Automatic ERAL before WRAL

• Power-on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device St atus signal (Ready/Busy

)

• Sequential read function

• 1,000,000 E/W cycles

• Data retention > 200 years

• Temperature ranges supported:

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

Pin Function Table

Name Function

CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output

SS Ground

V PE Program Enable ORG Memory Configuration

CC Power Supply

Description:

The Microchip Technology Inc. 93XX86A/B/C devices are 16K bit low-voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93XX86C are dependent upon external logic levels driving the ORG pin to set word size. In the SOT-23 package, the 93XX86A devices provide dedicated 8-bit memory organization, while the 93XX86B devices provide dedicated 16-bit memory organization. A Program Enable ( PE) pin allows th e user to write-protect the entire memory array. Advanced CMOS technology makes these devices ideal for low-po wer, nonvolatile memo ry ap plicat ions. The entire 93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging incl uding 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish is available.

Package Types (not to scale)

PDIP/SOIC

CLK

2 3

TSSOP/MSOP

CLK

(P, SN)

(ST, MS )

1 2 3 4

8 7

ORG V

ORG

CLK

SOT-23

(OT)

1 2 3

DFN

(MC)

1 2

CLK

VCC

ORG

6 5

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rat ing on ly and funct ional operati on of th e dev ice at those or any oth er con dit ions abov e thos e indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All parameters apply over the speci fied ranges unless otherwise noted.

Param.

No.

D1 V

D2 VIL1

D3 VOL1

D4 V

Symbol Parameter Min Typ Max Units Conditions

IH1 IH2

High-level input voltag e 2.0

Low-level input voltage -0.3

IL2

Low-level output voltag e —

OL2

High-level output volt ag e 2.4

OH1 OH2

D5 ILI Input leakage current — — ±1 μAVIN = VSS or VCC D6 ILO Output leakage current — — ±1 μAVOUT = VSS or VCC D7 CIN,

OUT

D8 I

CC write Write current —

Pin capacitance (all inputs/ outputs)

D9 ICC read Read current —

D10 ICCS Standby current —

D11 VPOR VCC voltage detect

Note 1: This parameter is periodically sampled and not 100% tested.

2: ORG and PE pin not available on ‘A’ or ‘B’ versions. 3: Ready/Busy status must be cleared from DO, see Section 3.4 “Data Out (DO)”.

Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V Automotive (E): T

0.7 VCC

-0.3

—

VCC - 0.2——

A = -40°C to +125°C, VCC = +2.5V to 5.5V

——VCC +1

CC +1

— —

0.8

0.2 VCC

0.4

0.2 —

—

VVV

CC ≥ 2.7V CC < 2.7V

VVVCC ≥ 2.7V

CC < 2.7V

VVI

OL = 2.1 mA, VCC = 4.5V OL = 100 μA, VCC = 2.5V

VVI

OH = -400 μA, VCC = 4.5V OH = -100 μA, VCC = 2.5V

——7pFVIN/VOUT = 0V (Note 1)

A = 25°C, FCLK = 1 MHz

—

— —

—

500

— —

100

— —

—

500

—

1 5

mAμAFCLK = 3 MHz, VCC = 5.5V

CLK = 2 MHz, VCC = 2.5V

FCLK = 3 MHz, VCC = 5.5V

μA

CLK = 2 MHz, VCC = 3.0V

μA

CLK = 2 MHz, VCC = 2.5V

μAμAI – Temp

E – Temp CLK = CS = 0V ORG = DI PE = VSS or VCC

(Note 2) (Note 3) (Note 1)

— —

1.5

3.8

— —

93AA86A/B/C, 93LC86A/B/C

93C86A/B/C

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

TABLE 1-2: AC CHARACTERISTICS

All parameters apply over the specified ranges unless otherwise noted.

Param.

No.

A1 F

Symbol Parameter Min Max Units Conditions

CLK Clock frequency — 3

A2 TCKH Clock high time 200

A3 TCKL Clock low time 100

A4 TCSS Chip Select setup time 50

Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V Automotive (E): T

250 450

200 450

100 250

A = -40°C to +125°C, VCC = +2.5V to 5.5V

MHz

4.5V ≤ VCC < 5.5V 2 1

—ns

MHz

2.5V ≤ V

1.8V ≤ V

MHz

4.5V ≤ VCC < 5.5V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC < 5.5V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC < 5.5V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

A5 TCSH Ch ip Sele ct hol d time 0 — ns 1 .8V ≤ VCC < 5.5V A6 TCSL Chip Select low time 250 — ns 1 .8V ≤ VCC < 5.5V A7 T

DIS Data input setup time 50

—ns 100 250

A8 T

DIH Data input hold time 50

—ns 100 250

A9 T

PD Data output delay time — 100

250 400

A10 T

CZ Data output disable time — 100

200

A11 TSV Status valid time — 200

300 500

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

ns ns

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

ns nsns4.5V ≤ VCC < 5.5V, (Note 1)

1.8V ≤ V

4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ V

1.8V ≤ V

CC < 5.5V CC < 4.5V CC < 2.5V

CC < 5.5V, CL = 100 pF CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF

CC < 4.5V, (Note 1)

CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF

A12 TWC Program cycle time — 5 ms Erase/Write mo de (AA and LC

versions)

A13 T

WC — 2 ms Erase/Write mode

(93C versions)

A14 T

EC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V

A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This application is not tested but ensured by characterization. For endurance estimates in a specific

application, ple ase consul t the Tot al Endura nce™ Model which may be obt ained from Microchi p’s w eb site at www.microchip.com.

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

FIGURE 1-1 : SYNCHRONOUS DA TA TIMING

VIL

VIH

CLK

VIL

TDIS

VIH

VIL

VOH

(Read)

(Program)

Note: TSV is relative to CS.

VOL VOH

VOL

CSS

TCKH

TDIH

TPD

TCKL

TPD

Status Valid

TCSH

TCZ

TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX86B OR 93XX86C WITH ORG = 1)

Instruction SB Opcode Address Data In Data Out

READ 1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15-D0 29 EWEN 1 00 11XXXXXXXX — HighZ 13 ERASE 1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY ERAL 1 00 10XXXXXXXX — (RDY/BSY WRITE 1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY WRAL 1 00 01XXXXXXXX D15-D0 (RDY/BSY EWDS 1 00 00XXXXXXXX — High-Z 13

Req. CLK

Cycles

)13 )13 )29 )29

TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX86A OR 93XX86C WITH ORG = 0)

Instruction SB Opcode Address Data In Data Out

READ 1 10 A10A9A8A7A6A5A4A3A2A1A0 — D7-D0 22 EWEN 1 00 1 1X X XX XXXXX —High-Z 14 ERASE 1 11 A10A9A8A7A6A5A4A3A2A1A0 — (RDY/BSY ERAL 1 00 1 0X X XX XXXXX — (RDY/BSY WRITE 1 01 A10A9A8A7A6A5A4A3A2A1A0 D7-D0 (RDY/BSY WRAL 1 00 0 1X X XX XXXXX D7-D0 (RDY/BSY EWDS 1 00 0 0X X XX XXXXX —High-Z 14

Req. CLK

Cycles

)14 )14 )22 )22

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

2.0 FUNCTIONAL DESCRIPTION

When the ORG pin (93XX86C) is connected to VCC, the (x16) organization is selected. When it is co nnected to ground, the (x8) organization is selected. Instructions, addresses and write dat a are cl oc ke d into the DI pin on the rising edge of the clock (CLK). Th e DO pin is normally he ld in a High-Z stat e except when read ing data from the device, or when checking the Ready/

status during a programming operation. The

Busy Ready/Busy Write operation by polli ng the DO pi n; DO low indicate s that programming is still in progress, while DO high indicates the device is ready. DO will enter the High-Z state on the falling edge of CS.

2.1 Start Condition

The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.

Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL or WRAL). As soon as CS is high, the device is no longer in Standby mode.

An instruction following a Start condition will only be executed if the requi red opcode, address and data bits for any particular instruction are clocked in.

Note: When preparing to transm it an instruction,

status can be verified during an Erase/

either the CLK or DI signal levels must be at a logic low as CS is toggled active high.

2.2 Data In/Data Out (DI/DO)

It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out i s undefined a nd will d epend upon the relativ e impedances of Data Out and the signal source driving A0. The hi gher the current s ourcing capabilit y of the driver, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO.

2.3 Data Protection

All modes of operation ar e inhibited when VCC is below a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices or 3.8V for ‘93C’ devices.

The EWEN and EWDS commands give additional protection against accidentally programming during normal operation.

Note: For added protection, an EWDS

command should be performed after every write operation and an external 10 kΩ pull-down protection res istor sho uld be added to the CS pin.

After power-up the device is automatically in the EWD S mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed.

Note: T o preven t accident al writes to the array in

the 93XX86C devices, set the PE pin to a logic low.

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

Block Diagram

CC VSS

Memory

Array

Data Register

Mode

ORG*

CS PE*

CLK

*ORG and PE inputs are not available on A/B devices.

Decode

Logic

Clock

Address Decoder

Address

Counter

Output

Buffer

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

2.4 Erase

The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. The rising edge of CLK before the last address bit initiates the write cycle.

FIGURE 2-1 : ERASE TIMI NG

CLK

111A

High-Z

AN-1 AN-2

The DO pin indicates the Ready/Busy device if CS is brought high after a minimum of 250 ns low (TCSL). D O at logical ‘ 0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been erased and the device is ready for another instruction.

Note: After the Erase cycle is complete, issuing

a St art bit and then taki ng CS lo w will c lear the Ready/Busy s tatus from DO .

CSL

Check Status

•••

SV TCZ

Busy Ready

status of the

High-Z

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

2.5 Erase All (ERAL)

The Erase Al l (ERAL) instruction will erase the entire memory array to the logical ‘1’ state. The ERAL cycle is identical to the erase cycle, except for the different opcode. The ERAL cycle is completely self-timed. The rising edge of CLK before the last data bit initiates the write cycle. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle.

FIGURE 2-2 : ERAL TIMI N G

CLK

High-Z

100 10x

The DO pin indicates the Ready/Busy device, if CS is brough t high a fter a minimum of 250 n s low (TCSL).

Note: After the ERAL command is complete,

issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO.

VCC must be ≥ 4.5V for proper operation of ERAL.

CSL

Check Status

•••

SV TCZ

Busy Ready

status of the

High-Z

93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C

2.6 Erase/Write Disable and Enable (EWDS/EWEN)

The 93XX86A/B/C powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/W rite Enable (EWEN) instruc tion.

FIGURE 2-3: EWDS TIMING

CLK

FIGURE 2-4: EWEN TIMING

000x

Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device.

To protect against accidental data disturbance, the EWDS instruction c an be used to di sable all Erase/W ri te functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.

CSL

•••

TCSL

CLK

00 1 1x

2.7 Read

The READ instruction outputs the serial data of the addressed memory lo cation on the DO pin. A dummy zero bit precedes the 8-bit (If O RG pin is low or A-V e rsion devices) or 16-bit (If ORG pin is high or B-version devices) output string.

FIGURE 2-5 : READ TIMIN G

CLK

110

•••

The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (T

PD).

Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output se qu en ti ally.

High-Z

0 Dx

•••

D0 Dx

•••

Dx D0

•••

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