MICROCHIP 93AA76A, 93AA76B, 93AA76C, 93LC76A, 93LC76B Technical data
...
2004 Microchip Technology Inc. DS21796D-page 1
93AA76A/B/C, 93LC76A/B/C,
93C76A/B/C
Device Selection Table
Features
• Low-power CMOS technology
• ORG pin to select word size for ‘76C’ version
• 1024 x 8-bit organization ‘A’ devices (no ORG)
• 512 x 16-bit organization ‘B’ devices (no ORG)
• Program Enable pin to write-protect the entire
array (except on SOT-23 packages)
• Self-timed ERASE/WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device St a tus signal (READ Y/BUSY
)
• Sequential READ function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Temperature ranges supported:
Pin Function Table
Description
The Microchip Technology Inc. 93X X7 6A/ B/C d evices
are 8K bit, low-voltage, serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93XX76C are dependent upon external logic
levels driving the ORG pin to set word size. For
dedicated 8-bit communication, the 93XX76A devices
are available, while the 93XX76B devices provide
dedicated 16-bit communication, available on SOT-23
devices only. A Program Enable (PE) pin allows the
user to write-protect the entire memory array.
Advanced CMOS technology makes these devices
ideal for low-power, nonvolatile memory application s.
The 93XX Series is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead MSOP, 6-lead SOT-23,
and 8-lead TSSOP. Pb-free (Pure Mat te Sn) finish is
also available.
Package Types (not to scale)
Part Number VCC Range ORG Pin PE Pin Word Size Temp Ranges Packages
93AA76A 1.8-5.5 No No 8-bit I OT
93AA76B 1.8- 5-5 No No 16-bit I OT
93LC76A 2.5-5.5 No No 8-bit I, E OT
93LC76B 2.5-5.5 No No 16-bit I, E OT
93C76A 4.5-5.5 No No 8-bit I, E OT
93C76B 4.5-5.5 No No 16-bit I, E OT
93AA76C 1.8-5.5 Yes Yes 8 or 16-bit I P, SN, ST, MS
93LC76C 2.5-5.5 Yes Yes 8 or 16-bit I, E P, SN, ST, MS
93C76C 4.5-5.5 Yes Yes 8 or 16-bit I, E P, SN, ST, MS
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
V
SS Ground
PE Program Enable
ORG Memory Configuration
V
CC Power Supply
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PE
ORG
V
SS
PDIP/SO IC
(P, SN)
TSSOP/MSOP
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PE
ORG
V
SS
(ST, MS
)
SOT-23
DO
V
SS
DI
1
2
3
6
5
4
V
CC
CS
CLK
(OT)
8K Microwire Compatible Serial EEPROM
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796D-page 2 2004 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rat ing on ly and funct ional operati on of th e dev ice at those or any oth er con dit ions abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
All parameters apply over the speci fied
ranges unless otherwise noted.
VCC = 1.8V to 5.5V
Industrial (I): T
A = -40°C to +85°C
Automotive (E): T
A = -40°C to +125°C
Param.
No.
Symbol Parameter Min Typ Max Units Conditions
D1 V
IH1
V
IH2
High-level input volt ag e 2.0
0.7 VCC
——VCC +1
V
CC +1
VVV
CC ≥ 2.7V
V
CC < 2.7V
D2 V
IL1
V
IL2
Low-level input voltage -0.3
-0.3
—
—
0.8
0.2 VCC
VVVCC ≥ 2.7V
V
CC < 2.7V
D3 VOL1
V
OL2
Low-level output voltag e —
—
—
—
0.4
0.2
VVI
OL = 2.1 mA, VCC = 4.5V
I
OL = 100 µA, VCC = 2.5V
D4 VOH1
V
OH2
High-level output volt ag e 2.4
VCC - 0.2——
—
—
VVI
OH = -400 µA, VCC = 4.5V
I
OH = -100 µA, VCC = 2.5V
D5 I
LI Input leakage current — — ±1 µAVIN = VSS to VCC
D6 ILO Output leakage current — — ±1 µAVOUT = VSS to VCC
D7 CIN,
C
OUT
Pin capacitance (all inputs/
outputs)
——7pFVIN/VOUT = 0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
D8 ICC write Write current —
—
—
500
3
—
mAµAFCLK = 3 MHz, VCC = 5.5V
F
CLK = 2 MHz, VCC = 2.5V
D9 I
CC read Read current —
—
—
—
—
100
1
500
—
mA
µA
µA
F
CLK = 3 MHz, VCC = 5.5V
F
CLK = 2 MHz, VCC = 3.0V
F
CLK = 2 MHz, VCC = 2.5V
D10 I
CCS Standby current —
—
—
—
1
5
µAµAI – Temp
E – Temp
CLK = Cs = 0V
ORG = DI = V
SS or VCC
(Note 2) (Note 3)
D11 VPOR VCC voltage detect
93AA76A/B/C, 93LC76A/B/C
93C76A/B/C
—
—
1.5V
3.8V
—
—
VV(Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: READY/BUSY status must be cleared from DO, see Section 3.4 “Data Out (DO)”.
2004 Microchip Technology Inc. DS21796D-page 3
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
TABLE 1-2: AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
V
CC = 1.8V to 5.5V
Industrial (I): T
A = -40°C to +85°C
Automotive (E): T
A = -40°C to +125°C
Param.
No.
Symbol Parameter Min Max Units Conditions
A1 FCLK Clock frequency — 3
2
1
MHz
MHz
MHz
4.5V ≤ VCC < 5.5V
2.5V ≤ V
CC < 4.5V
1.8V ≤ V
CC < 2.5V
A2 TCKH Clock high time 200
250
450
—ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ V
CC < 4.5V
1.8V ≤ V
CC < 2.5V
A3 TCKL Clock low time 100
200
450
—ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ V
CC < 4.5V
1.8V ≤ V
CC < 2.5V
A4 TCSS Chip Select setup time 50
100
250
—ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ V
CC < 4.5V
1.8V ≤ V
CC < 2.5V
A5 TCSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V
A6 T
CSL Chip Select low time 250 — ns 1.8V ≤ VCC < 5.5V
A7 TDIS Data input setup time 50
100
250
—ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ V
CC < 4.5V
1.8V ≤ V
CC < 2.5V
A8 TDIH Data input hold time 50
100
250
—ns
ns
ns
4.5V ≤ VCC < 5.5V
2.5V ≤ V
CC < 4.5V
1.8V ≤ V
CC < 2.5V
A9 TPD Data output delay time — 1 00
250
400
ns
ns
ns
4.5V ≤ VCC < 5.5V, CL = 100 pF
2.5V ≤ V
CC < 4.5V, CL = 100 pF
1.8V ≤ V
CC < 2.5V, CL = 100 pF
A10 TCZ Data output disable time — 100
200
nsns4.5V ≤ VCC < 5.5V, (Note 1)
1.8V ≤ V
CC < 4.5V, (Note 1)
A11 T
SV Status valid time — 200
300
500
ns
ns
ns
4.5V ≤ V
CC < 5.5V, CL = 100 pF
2.5V ≤ V
CC < 4.5V, CL = 100 pF
1.8V ≤ V
CC < 2.5V, CL = 100 pF
A12 T
WC Program cycle time — 5 ms Erase/Write mode (AA and LC
versions)
A13 T
WC — 2 ms Erase/Wr ite mode
(93C versions)
A14 T
EC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V
A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V
A16 — Endurance 1M — cycles 25°C, V
CC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from
www.microchip.com.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796D-page 4 2004 Microchip Technology Inc.
FIGURE 1-1 : SYNCHRONOUS DA TA TIMING
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX76B OR 93XX76C WITH ORG = 1)
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX76A OR 93XX76C WITH ORG = 0)
Instruction SB Opcode Address Data In Data Out
Req. CLK
Cycles
READ 1 10 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 – D0 29
EWEN 1 00 11XXXXXXXX — HIGH-Z 13
ERASE 1 11 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)13
ERAL 1 00 10XXXXXXXX — (RDY/BSY
)13
WRITE 1 01 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY
)29
WRAL 1 00 01XXXXXXXXD15 – D0(RDY/BSY
)29
EWDS 1 00 00XXXXXXXX — HIGH-Z 13
Instruction SB Opcode Address Data In Data Out
Req. CLK
Cycles
READ 1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 – D0 22
EWEN 1 00 11XXXXXXXXX — HIGH-Z 14
ERASE 1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
)14
ERAL 1 00 10XXXXXXXXX — (RDY/BSY
)14
WRITE 1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY
)22
WRAL 1 00 01XX XXXXXXXD7 – D0(RDY/BSY
)22
EWDS 1 00 00XXXXXXXXX — HIGH-Z 14
CS
V
IH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK
DI
DO
(READ)
DO
(PROGRAM)
T
CSS
TDIS
TCKH
TCKL
TDIH
TPD
TCSH
TPD
TCZ
STATUS VALID
TSV
TCZ
Note: TSV is relative to CS.
2004 Microchip Technology Inc. DS21796D-page 5
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG* pin is connected to VCC, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write d ata a re clocke d into the D I pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
BUSY
status during a programming operation. The
READY/BUSY
status can be verified during an Erase/
Write operation by polli ng the DO pi n; DO low indicate s
that programming is still in progress, while DO high
indicates the de vi ce is rea dy. DO will ente r th e HI GH -Z
state on the falling edge of CS.
2.1 Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a Start condition will only be
executed if the requi red opcode, address and data bits
for any particular instruction are clocked in.
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic highlevel. Under such a condition the voltage level seen at
Data Out i s undefined a nd will d epend upon the relativ e
impedances of Data Out and the signal source driving
A0. The hi gher the current s ourcing capabilit y of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
2.3 Data Protection
All modes of operation ar e inhibited when VCC is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note: For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
Memory
Array
Data Register
Mode
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
DI
ORG*
CS
CLK
V
CC VSS
*ORG and PE inputs are not available on
PE*
A/B devices.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796D-page 6 2004 Microchip Technology Inc.
2.4 ERASE
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low (T CSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY
status from
DO.
FIGURE 2-1 : ERASE TI MI NG
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
1
1A
N
AN-1 AN-2
•••
A0
T
SV TCZ
BUSY READY
HIGH-Z
T
WC
HIGH-Z
2004 Microchip Technology Inc. DS21796D-page 7
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.5 ERASE ALL (ERAL)
The Erase Al l (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
The DO pin indicates the READY/BUSY
status of the
device, if CS is brough t high a fter a minimum of 250 n s
low (TCSL).
Note: Issuing a Start bit and then taking CS low
will clear the READY/BUSY
status from
DO.
V
CC must be ≥ 4.5V for proper operation of ERAL.
FIGURE 2-2 : ERAL TIMING
CS
CLK
DI
DO
T
CSL
CHECK STATUS
10010X
•••
X
T
SV TCZ
BUSY READY
HIGH-Z
T
EC
HIGH-Z
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
DS21796D-page 8 2004 Microchip Technology Inc.
2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)
The 93XX76A/B/C powers up in the ERASE/WRITE
Disable (EWDS) state. All programming modes must be
preceded by an ERASE/WRITE En able (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is
executed or V
CC is removed from the device.
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all ERASE/
WRITE functions and should follow all programming
operations. Execution of a READ instruction is
independent of both the EWEN and EWDS instructions.
FIGURE 2-3: EWDS TIMING
FIGURE 2-4: EWEN TIMING
2.7 READ
The READ instruction outputs the serial data of the
addressed memory lo cation on the DO pin. A dummy
zero bit precedes the 8-bit (If O RG pin is low or A-V e rsion
devices) or 16-bit (If ORG pin is high or B-version
devices) output st rin g. The ou tput dat a bi t s will toggle on
the rising edge of the CLK and are stable after the specified time dela y (T
PD). Sequentia l read is po ssibl e when
CS is held high. The memory data will automatically cycle
to the next re gi ster and output seque nt ia ll y.
FIGURE 2-5 : READ TIMI N G
CS
CLK
DI
10
000X
•••
X
T
CSL
1X
CS
CLK
DI
00 1 1X
TCSL
•••
CS
CLK
DI
DO
110
An
•••
A0
HIGH-Z
0Dx
•••
D0 Dx
•••
D0
•••
Dx D0
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