MICROCHIP 93AA76, 93AA86 Technical data

Not recommended for new designs – Please use 93AA76C or 93AA86C.

93AA76/86

8K/16K 1.8V Microwire Serial EEPROM

Features:

• Single supply operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current typical

-5 µA standby current (typical) at 3.0V

• ORG pin selectable memory configuration:

- 1024 x 8 or 512 x 16-bit organization (93AA76)

- 2048 x 8 or 1024 x 16-bit organization (93AA86)

• Self-timed erase and write cycles

• Automatic ERAL before WRAL

• Power on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device status signal during erase/write cycles

• Sequential read function

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• 8-pin PDIP/SOIC package

• Temperature ranges available:

- Commercial (C): 0°C to +70°C

Description:

Package Types

PDIP Package

CLK

SOIC Package

CLK

Block Diagram

CC VSS

93AA76/86

1 2

3 4

1 2

3 4

ORG

93AA76/86

VCC

ORG

The Microchip Technology Inc. 93AA76/86 are 8K and 16K low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 or x16 bits depending on the ORG pin setup. Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. These devices also have a Progr am Enable (PE) pin to allow t he user to write-protect the entire contents of the memory array. The 93AA76/86 is ava ilable in st andard 8-pi n PDIP and 8-pin surface mount SOIC packages.

PE CS

CLK

Memory

Array

Data

Mode

Decode

Logic

Clock

Generator

Address

Decoder

Address Counter

Output

Buffer

 2004 Microchip Technology Inc. DS21130E-page 1

93AA76/86

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

Soldering temperature of leads (10 seconds).......................................................................................................+300°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stres s ratin g only and func tional operati on of the devic e at thes e or any other co nditio ns abov e thos e indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.

(†)

SS ........................................................................................................-0.6V to Vcc + 1.0V

1.1 AC Test Conditions

AC Waveform:

VLO = 2.0V VHI = Vcc - 0.2V (Note 1)

HI = 4.0V for (Note 2)

Timing Measurement Reference Level:

Input 0.5 V Output 0.5 VCC

Note 1: For VCC < 4.0V

2: For V

CC > 4.0V

DS21130E-page 2  2004 Microchip Technology Inc.

93AA76/86

TABLE 1-1: DC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:

DC CHARACTERISTICS

Parameter Symbol Min. Max. Units Conditions

High-level input voltage V

Low-level input voltage V

Low-level output voltage VOL1 —0.4VIOL = 2.1 mA; VCC = 4.5V

High-level output voltage VOH1 2.4 — V IOH = -400 µA; VCC = 4.5V

Input leakage current I Output leakage current ILO -10 10 µAVOUT = 0.1V to VCC Pin capacitance

(all inputs/outpu t s) Operating current ICC write — 3 mA VCC = 5.5V

Standby current ICCS —10030µAµACLK = CS = 0V; VCC = 5.5V

Note 1: This parameter is periodically sampled and not 100% tested.

VCC = +1.8V to +6.0V Commercial (C): T

IH1 2.0 VCC + 1 V VCC ≥ 2.7V

A = 0°C to +70°C

VIH2 0.7 VCC VCC + 1 V VCC < 2.7V

IL1 -0.3 0.8 V VCC ≥ 2.7V

VIL2 -0.3 0.2 VCC VVCC < 2.7V

OL2 —0.2VIOL =100 µA; VCC = VCC Min.

VOH2 VCC-0.2 — V IOH = -100 µA; VCC = VCC Min.

LI -10 10 µAVIN = 0.1V to VCC

CINT —7pF (Note 1)

A = +25°C, FCLK = 1 MHz

ICC read — 1

500

mAµAFCLK = 3 MHz; VCC = 5.5V

CLK = 1 MHz; VCC = 3.0V

CLK = CS = 0V; V DI = PE = V

CC = 3.0V

ORG = VSS or VCC

 2004 Microchip Technology Inc. DS21130E-page 3

93AA76/86

TABLE 1-2: AC CHARACTERISTICS

Applicable over recommended operating ranges shown below unless otherwise noted:

AC CHARACTERISTICS

Parameter Symbol Min. Max. Units Conditions

VCC = +1.8V to +6.0V Commercial (C): T

A = 0°C to +70°C

Clock frequency F

Clock high time TCKH 200

Clock low time T

Chip select set up time T

CLK —3

2 1

—ns 300 500

CKL 100

—ns 200 500

CSS 50

—ns 100 250

MHz MHz

Mhz

ns ns

4.5V ≤ VCC ≤ 6.0 V

2.5V ≤ V

1.8V ≤ V

CC ≤ 4.5V

CC < 2.5V

4.5V ≥ VCC ≤ 6.0V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

CC ≤ 6.0V CC < 4.5V

CC < 2.5V

4.5V ≤ VCC ≤ 6.0V, Relative to CLK

2.5V ≤ V

1.8V ≤ V

CC < 4.5V, Relative to CLK CC < 2.5V, Relative to CLK

Chip select hol d time TCSH 0 — ns 1.8V ≤ VCC ≤ 6.0V Chip select low ti me T Data input setup time T

Data input hold time T

Data output delay time TPD —100

CSL 250 — ns 1.8V ≤ VCC ≤ 6.0V, Relative to CLK

DIS 50

100 250

DIH 50

100 250

—ns

ns ns

—ns

ns ns

ns 250 500

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC ≤ 6.0V, Relative to CLK

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC ≤ 6.0V, CL = 100 pF

2.5V ≤ V

1.8V ≤ V

≤ 6.0V, Relative to CLK

CC <4.5V, Relative to CLK CC < 2.5V, Relative to CLK

CC < 4.5V, Relative to CLK CC < 2.5V, Relative to CLK

CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF

Data output disable time T

CZ —100

500

Status valid time Tsv — 200

300 500

Program cycle time T

WC — 5 ms Erase/Write mode

EC —15msERAL mode

4.5V ≤ VCC ≤ 5.5V (Note 1)

1.8V ≤ V

4.5V ≥ V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V (Note 1) CC ≤ 6.0V, CL = 100 pF

CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF

TWL — 30 ms WRAL mode

Endurance — 1M — cycles 25°C, V

CC = 5.0V, Block mode (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by char acterization. For endurance estimates in a specific

application, please con sult the Total Endurance

™

Model which can be obta ined from Microc hip’s we b site

at: www.microchip.com

DS21130E-page 4  2004 Microchip Technology Inc.

93AA76/86

TABLE 1-3: INSTRUCTION SET FOR 93AA76: ORG = 1 (X16 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 29 EWEN 1 00 1 1 X X X X X X X X — High-Z 13 ERASE 1 11 X A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13 ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13 WRITE 1 01 X A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29 WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29 EWDS 1 00 0 0 X X X X X X X X — High-Z 13

TABLE 1-4: INSTRUCTION SET FOR 93AA76: ORG = 0 (X8 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out

READ 1 10 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22 EWEN 1 00 1 1 X X X X X X X X — High-Z 14 ERASE 1 11 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14 ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 14 WRITE 1 01 X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22 WRAL 1 00 0 1 X X X X X X X X D7 - D0 (RDY/BSY) 22 EWDS 1 00 0 0 X X X X X X X X — High-Z 14

Req. CLK

Cycles

TABLE 1-5: INSTRUCTION SET FOR 93AA86: ORG = 1 (X16 ORGANIZATION)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

READ 1 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D15 - D0 29 EWEN 1 00 1 1 X X X X X X X X — High-Z 13 ERASE 1 11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 13 ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 13 WRITE 1 01 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 29 WRAL 1 00 0 1 X X X X X X X X D15 - D0 (RDY/BSY) 29 EWDS 1 00 0 0 X X X X X X X X — High-Z 13

TABLE 1-6: INSTRUCTION SET FOR 93AA86: ORG = 0 (X8 ORGANIZATION)

Instruction SB Opco de Address Data In Data Out Req. CLK Cycles

READ 1 10 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 22 EWEN 1 00 1 1 X X X X X X X X — High-Z 14 ERASE 1 11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY) 14 ERAL 1 00 1 0 X X X X X X X X — (RDY/BSY) 14 WRITE 1 01 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 22 WRAL 1 00 0 1 X X X X X X X X D7 - D0 (RDY/BSY) 22 EWDS 1 00 0 0 X X X X X X X X — High-Z 14

 2004 Microchip Technology Inc. DS21130E-page 5

93AA76/86

2.0 PRINCIPLES OF OPERATION

When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a high-Z state except when reading data from the device, or when checking the Ready/Busy a programming operation. The Ready/Busy be verified during an erase/write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the high-impedance state on the falling edge of the CS.

2.1 Start Condition

The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.

Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL and WRAL). As soon as CS is high, th e de vic e is no long er in the Standby mode.

An instruction following a Start condition will only be executed if the required amount of opcode, address and data bits for any particular instruction are clocked in.

After exec utio n of a n ins truct io n (i. e., clock in or out of the last required address or data bit) CLK and DI become “don't care” bits until a new Start condition is detected.

status during

status can

2.3 Erase/Write Enable and Disable (EWEN, EWDS)

The 93AA76/86 powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed

CC is removed from the device. To protect against

or V accidental data disturb, the EWDS instruction can be used to disable all erase/write functions and should follow all programming operati ons. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.

2.4 Data Protection

During power-up, all programming modes of operation are inhibited until V

1.4V. During power-down, the source data protection

circuitry acts to inhibit all programming modes w hen

CC has fallen below 1.4V.

V The EWEN and EWDS commands give additional

protection against accidentally programming during normal operation.

After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.

CC has reache d a leve l greate r than

2.2 DI/DO

It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefine d and will depend upon the rela tive impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin.

DS21130E-page 6  2004 Microchip Technology Inc.

93AA76/86

3.0 DEVICE OPERATION

3.1 READ

The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16-bit (x16 organization) or 8-bit (x8 organization) ou tput s tring. T he output dat a bit s wil l toggle on the rising edge of the CLK and are stable after the specified time delay (T possible when CS is held high and clock transitions continue. The memory address pointer will automatically increment and output data sequentially.

3.2 ERASE

The ERASE instruction forces all data bits of the specified address to the logical “1” state. The self-timed programming cycle is initiated on the rising edge of CLK as the last address bit (A0) is clocked in. At this point, the CLK, CS and DI inputs beco me “don’t cares”.

The DO pin indicates the Ready/Busy device if the CS is hig h. Th e R ead y/B usy displayed on the DO pin until the next Start bit is received as long as CS is hig h. Bringing t he CS low w ill place the device in Standby mode and cause the DO pin to enter the high-impedan ce state . DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction.

The erase cycle takes 3 ms per word (typical).

3.3 WRITE

The WRITE instruction is followed by 16 bits (or by 8 bits) of data to be written into the specified address. The self-timed programming cycle is initiated on the rising edge of CLK as the last data bit (D0) is clocked in. At this point, the CLK, CS and DI inputs become “don’t cares”.

The DO pin indicates the Ready/Busy device if the CS is hig h. Th e R ead y/B usy displayed on the DO pin until the next Start bit is received as long as CS is hig h. Bringing t he CS low w ill place the device in Standby mode and cause the DO pin to enter the high-impedan ce state . DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written and the device is ready for another instruction.

The write cycle takes 3 ms per word (typical).

PD). Sequential read is

status of the

status will be

status of the

status will be

3.4 Erase All (ERAL)

The ERAL instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the erase cycle except for the different opcode. The ERAL cycle is completely self-timed and commences on the rising edge of the l ast addre ss bit (A0). Note that the Least Signific ant 8 or 9 address bits ar e “don’t care” bits, depending on selection of x16 or x8 mode. Clocking of the CLK pin is not necessary after the device has entered the self clocking mode. The ERAL instruction is ensured at Vcc = +4.5V to +6.0V.

The DO pin indicates the Ready/Busy device if the CS is hig h. Th e Read y/Busy displayed on the DO pin until the next Start bit is received as long as C S is hig h. Bringing t he CS low wil l place the device in Standby mode and cause the DO pin to enter the high-impedanc e state . DO at logical “ 0” indicates that programming is still in progress. DO at logical “1” indicates that the entire device has been erased and is ready for another instruction.

The ERAL cycle takes 15 ms maximum (8 ms typical).

status of the

status will be

3.5 Write All (WRAL)

The WRAL instruction will write the entire me mory array with the data specified in the command. The WRAL cycle is completely self-timed and commences on the rising edge of the last address bit (A0). Note that the Least Significant 8 or 9 address bits are “don’t cares”, depending on selecti on of x1 6 or x8 m ode . Clock in g of the CLK pin is not necessary after the device has entered the self clocking mode. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The WRAL instruction is ensured at Vcc = +4.5V to +6.0V.

The DO pin indicates the Ready/Busy device if the CS is hig h. Th e Read y/Busy displayed on the DO pin until the next Start bit is received as long as C S is hig h. Bringing t he CS low wil l place the device in Standby mode and cause the DO pin to enter the high-impedanc e state . DO at logical “ 0” indicates that programming is still in progress. DO at logical “1” indicates that the entire device has been written and is ready for another instruction.

The WRAL cycle takes 30 ms maximum (16 ms typical).

status of the

status will be

 2004 Microchip Technology Inc. DS21130E-page 7

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