93AA56A/B/C, 93LC56A/B/C,
93C56A/B/C
2K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number VCC Range ORG Pin Word Size Temp Ranges Packages
93AA56A 1.8-5.5 No 8-bit I P, SN, ST , MS, OT
93AA56B 1.8-5-5 No 16-bit I P, SN, ST , MS, OT
93LC56A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT
93LC56B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT
93C56A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT
93C56B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT
93AA56C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST , MS
93LC56C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST , MS
93C56C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS
Features
• Low-power CMOS technology
• ORG pin to select word size for ‘56C version
• 256 x 8-bit organization ‘A’ ver. devices (no ORG)
• 128 x 16-bit organization ‘B’ ver. devices (no
ORG)
• Self-timed ERASE/WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device St a tus signal (READ Y/BUSY)
• Sequential READ function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Temperature ranges supported:
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Pin Function Table
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No internal conn ec tio n
ORG Memory Configuration
V
CC Power Supply
Description
The Microchip Technology Inc. 93XX56A/B/C devices
are 2K bit low voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA56C, 93LC56C or 93C56C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA56A, 93LC56A or 93C56A devices are available,
while the 93AA56B, 93LC56B and 93C56B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, and 8-lead
TSSOP. Pb-free (Pure Matte Sn) finish is also
available.
Package Types (not to scale)
ROTATED SOIC
(ex: 93LC56BX)
NC
1
8
V
CS
CLK
CC
2
3
4
ORG*
7
SS
V
6
DO
DI
5
TSSOP/MSOP
(ST, MS)
1
CS
2
CLK
3
DI
4
DO
* ORG pin is NC on A/B devices
8
V
CC
7
NC
6
ORG*
5
V
SS
CS
CLK
DO
DO
V
SS
DI
DI
PDIP/SOIC
(P, SN)
1
2
3
4
SOT-23
(OT)
1
6
2
5
3
4
V
CC
8
7
NC
6
ORG*
SS
V
5
V
CC
CS
CLK
2003 Microchip Technology Inc. DS21794B-page 1
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rat ing on ly and funct ional operati on of th e dev ice at those or any oth er con dit ions abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
All parameters apply over the speci fied
ranges unless otherwise noted.
Param.
D1 V
D2 V
D3 Vol1
Symbol Parameter Min Typ Max Units Conditions
No.
IH1
IH2
V
IL1
IL2
V
High-level input volt ag e 2.0
Low-level input voltage -0.3
Low-level output voltag e —
Vol2
D4 VOH1
OH2
V
D5 I
LI Input leakage current — — ±1 µAVIN = VSS to VCC
High-level output volt ag e 2.4
D6 ILO Output leakage current — — ±1 µAVOUT = VSS to VCC
D7 CIN,
C
OUT
Pin capacitance (all inputs/
outputs)
D8 ICC write Write current —
D9 I
D10 I
CC read Read current —
CCS Standby current —
D11 VPOR VCC voltage detect
93AA56A/B/C, 93LC56A/B/C
93C56A/B/C
Note 1: This parameter is periodically sampled and not 100% tested.
2: ORG pin not available on ‘A’ or ‘B’ versions.
3: READY/BUSY status must be cleared from DO, see Section 3.4 "Data Out (DO)".
VCC = range by device (see Table on Page 1)
Industrial (I): T
Automotive (E): T
0.7 VCC
-0.3
—
VCC - 0.2——
A = -40°C to +85°C
A = -40°C to +125°C
——VCC +1
CC +1
V
—
—
—
—
0.8
0.2 VCC
0.4
0.2
—
—
VVV
CC ≥ 2.7V
CC < 2.7V
V
VVVCC ≥ 2.7V
CC < 2.7V
V
VVIOL = 2.1 mA, VCC = 4.5V
I
OL = 100 µA, VCC = 2.5V
VVI
OH = -400 µA, VCC = 4.5V
OH = -100 µA, VCC = 2.5V
I
——7pFVIN/VOUT = 0V (Note 1)
T
A = 25°C, FCLK = 1 MHz
—
—
—
—
—
500
—
—
100
—
—
2
—
1
500
—
1
5
mAµAFCLK = 3 MHz, Vcc = 5.5V
CLK = 2 MHz, Vcc = 2.5V
F
mA
µA
µA
CLK = 3 MHz, VCC = 5.5V
F
CLK = 2 MHz, VCC = 3.0V
F
CLK = 2 MHz, VCC = 2.5V
F
µAµAI – Temp
E – Temp
CLK = Cs = 0V
ORG = DI = V
(Note 2) (Note 3)
—
—
1.5V
3.8V
—
—
VV(Note 1)
SS or VCC
DS21794B-page 2 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
TABLE 1-2: AC CHARACTERISTICS
All parameters apply over the specified
ranges unless otherwise noted.
CC = range by device (see Table on Page 1)
V
Industrial (I): T
Automotive (E): T
A = -40°C to +85°C
A = -40°C to +125°C
Param.
No.
A1 FCLK Clock frequency — 3
A2 TCKH Clock high time 200
A3 TCKL Clock low time 100
A4 TCSS Chip Select setup time 50
Symbol Parameter Min Max Units Conditions
MHz
4.5V ≤ VCC < 5.5V, 93XX56C only
2
1
—ns
250
450
—ns
200
450
—ns
100
250
MHz
MHz
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
4.5V ≤ VCC < 5.5V, 93XX56C only
ns
ns
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
4.5V ≤ VCC < 5.5V, 93XX56C only
ns
ns
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
4.5V ≤ VCC < 5.5V
ns
ns
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
A5 TCSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V
A6 T
A7 TDIS Data input setup time 50
A8 TDIH Data input hold time 50
A9 TPD Data output delay time — 200
A10 TCZ Data output disable time — 100
A11 T
A12 T
CSL Chip Select low tim e 250 — ns 1.8V ≤ VCC < 5.5V
—ns
100
250
—ns
100
250
250
400
4.5V ≤ VCC < 5.5V, 93XX56C only
ns
ns
2.5V ≤ V
1.8V ≤ V
CC < 5.5V
CC < 2.5V
4.5V ≤ VCC < 5.5V, 93XX56C only
ns
2.5V ≤ V
1.8V ≤ V
ns
ns
4.5V ≤ VCC < 5.5V, CL = 100 pF
ns
2.5V ≤ V
1.8V ≤ V
ns
CC < 5.5V
CC < 2.5V
CC < 4.5V, CL = 100 pF
CC < 2.5V, CL = 100 pF
nsns4.5V ≤ VCC < 5.5V, (Note 1)
200
SV Status valid time — 200
300
500
WC Program cycle time — 6 ms Erase/Write mode (AA and LC
ns
ns
ns
1.8V ≤ V
4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V, (Note 1)
CC < 5.5V, CL = 100 pF
CC < 4.5V, CL = 100 pF
CC < 2.5V, CL = 100 pF
versions)
A13 T
WC — 2 ms Erase/Write mode
(93C versions)
A14 T
EC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V
A15 TWL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V
A16 — Endurance 1M — cycles 25°C, V
CC = 5.0V, (Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from
www.microchip.com.
2003 Microchip Technology Inc. DS21794B-page 3
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
FIGURE 1-1 : SY NCH R ON OUS DA TA TIMING
IH
V
CS
CSS
VIL
VIH
CLK
VIL
TDIS
VIH
DI
VIL
VOH
DO
(READ)
(PROGRAM)
Note: TSV is relative to CS.
DO
VOL
VOH
VOL
TSV
T
TCKH
TDIH
TPD
TCKL
TPD
STATUS VALID
TCSH
TCZ
TCZ
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX56B OR 93XX56C WITH ORG = 1)
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE 1 11 X A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)11
ERAL 1 00 10XXXXXX — (RDY/BSY
EWDS 1 00 00XXXXXX — HIGH-Z 11
EWEN 1 00 11XXXXXX — HIGH-Z 11
READ 1 10 X A6 A5 A4 A3 A2 A1 A0 — D15 – D0 27
WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY)27
WRAL 1 00 01XXXXXXD15 – D0(RDY/BSY
)11
)27
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX56A OR 93XX56C WITH ORG = 0)
Instruction SB Opcode Address Data In Data Out
ERASE 1 11 X A7 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
ERAL 1 00 10XXXXXXX — (RDY/BSY
EWDS 1 00 00XXXXXXX — HIGH-Z 12
EWEN 1 00 11XXXXXXX — HIGH-Z 12
READ 1 10 X A7 A6 A5 A4 A3 A2 A1 A0 — D7 – D0 20
WRITE 1 01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 – D0 (RDY/BSY)20
WRAL 1 00 0 1 X X X X X X X D7 – D0 (RDY/BSY
Req. CLK
Cycles
)12
)12
)20
DS21794B-page 4 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.0 FUNCTIONAL DESCRIPTION
When the ORG* pin is connected to VCC, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write d ata a re clocke d into the D I pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
status during a programming operation. The
BUSY
READY/BUSY
Write operation by polli ng the DO pi n; DO low indicate s
that programming is still in progress, while DO high
indicates the de vi ce is rea dy. DO will enter the HIGH-Z
state on the falling edge of CS.
2.1 START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a ST ART condi tion is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a START condition will only be
executed if the requi red opcode, address and data bits
for any particular instruction are clocked in.
status can be verified during an Erase/
2.2 Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that preced es t he R ead o per atio n, i f A0 i s a l ogi c hi gh
level. Under such a condition the voltage level seen at
Data Out i s undefined a nd will d epend upon the relativ e
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3 Data Protection
All modes of operation ar e inhibited when VCC is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note: For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
CC VSS
V
Memory
Array
Data Register
DI
Mode
ORG*
CS
CLK
*ORG input is not avai lable on A/B devices
Decode
Logic
Clock
Register
Address
Decoder
Address
Counter
Output
Buffer
DO
2003 Microchip Technology Inc. DS21794B-page 5
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.4 ERASE
The DO pin indicates the READY/BUSY
device if CS is brought high after a minimum of 250 ns
The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. CS is brought low
following the loa ding of th e last a ddress b it. This fall ing
edge of the CS pin initiates the self-timed programming cycle, except on ‘93C’ devices where the rising
low (T CSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note: Issuing a ST ART bit and then taking C S low
edge of CLK before the last address bit initiates the
write cycle.
FIGURE 2-1 : ERASE TIMI NG FOR 9 3A A AN D 93L C D EVIC E S
CSL
T
CS
CLK
N
1A
AN-1 AN-2
•••
A0
DO
1
DI
HIGH-Z
1
will clear the READY/BUSY
DO.
CHECK STATUS
T
SV TCZ
BUSY READY
status of the
status from
HIGH-Z
FIGURE 2-2: ERASE TIMING FOR 93C DEVICES
CS
CLK
DO
DI
HIGH-Z
1
1
1A
N
AN-1 AN-2
•••
A0
WC
T
CSL
T
CHECK STATUS
T
SV TCZ
BUSY READY
WC
T
HIGH-Z
DS21794B-page 6 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.5 ERASE ALL (ERAL)
The Erase Al l (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the ERASE cycle, except for the different
The DO pin indicates the READY/BUSY
device, if CS is brough t high a fter a minimum of 250 n s
low (TCSL).
Note: Issuing a ST ART bit and then taking C S low
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
CC must be ≥ 4.5V for proper operation of ERAL.
‘93C’ devices where the rising edge of CLK before the
V
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3 : ERAL TIMIN G FO R 93 AA A ND 9 3L C DEVI C E S
CSL
T
CS
CLK
DI
DO
HIGH-Z
VCC must be ≥ 4.5V for proper operation of ERAL.
10010X
•••
X
will clear the READY/BUSY
DO.
CHECK STATUS
T
SV TCZ
BUSY READY
EC
T
HIGH-Z
status of the
status from
FIGURE 2-4: ERAL TIMING FOR 93C DE VICE S
CS
CLK
DO
DI
HIGH-Z
10010X
•••
CSL
T
CHECK STATUS
X
T
SV TCZ
BUSY READY
T
EC
HIGH-Z
2003 Microchip Technology Inc. DS21794B-page 7
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.6 ERASE/WRITE DISABLE And ENABLE (EWDS/EWEN)
The 93XX56A/B/C powers up in the ERASE/WRITE
Disable (EWDS) state. All Programming modes must be
preceded by an ERASE/WRITE En able (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is
executed or Vcc is removed from the device.
FIGURE 2-5: EWDS TIMING
CS
CLK
DI
10
000X
FIGURE 2-6: EWEN TIMING
CS
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all ERASE/
WRITE functions and should follow all programming
operations. Executio n of a READ instruction i s ind ependent of both the EWEN and EWDS instructions.
T
CSL
•••
X
TCSL
CLK
1X
DI
00 1 1X
2.7 READ
The READ instruction outputs the serial data of the
addressed memory lo cation on the DO pin. A dummy
zero bit precedes the 8-bit (If O RG pin is low or A-V e rsion
devices) or 16-bit (If ORG pin is high or B-version
FIGURE 2-7 : READ TIMIN G
CS
CLK
A0
•••
An
0Dx
DO
DI
110
HIGH-Z
•••
devices) output st rin g. The ou tput dat a bi t s will toggle on
the rising edge of the CLK and are stable after the specified time dela y (T
PD). Sequentia l read is po ssibl e when
CS is held high. The memory data will automatically cycle
to the next re gi ster and output seque nt ia ll y.
•••
D0 Dx
•••
D0
Dx D0
•••
DS21794B-page 8 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.8 WRITE
The WRITE instruction is followed by 8 bits (If ORG is
low or A-version device s) or 16 b its (If OR G pi n is hig h
or B-version devices) of data which are wr itten into th e
specified address. For 93AA56A/B/C and 93LC56A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93 C56A/ B/C d evices , the se lf-
The DO pin indicates the READY/BUSY
device, if CS is brough t high a fter a minimum of 250 n s
low (T CSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
Note: Issuing a ST ART bit and then taking C S low
timed auto-erase and pr ogramming cycle is initiated by
the rising edge of CLK on the last data bit.
FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES
T
CSL
CS
CLK
0
DI
DO
1
HIGH-Z
1An
•••
A0 Dx
•••
D0
will clear the READY/BUSY
DO.
TSV
BUSY
READY
status of the
status from
TCZ
HIGH-Z
FIGURE 2-9: WRITE TIMING FOR 93C DE VICE S
CS
CLK
0
DI
DO
1
HIGH-Z
1An
•••
A0 Dx
•••
D0
Twc
T
CSL
Twc
TSV
BUSY
READY
TCZ
HIGH-Z
2003 Microchip Technology Inc. DS21794B-page 9
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.9 WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA56A/B/C and 93LC 56A/B/C de vices , after th e
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C56A/B/C devices, the self-timed auto-
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY
device if CS is brought high after a minimum of 250 ns
CSL).
low (T
Note: Issuing a ST ART bit and then taking C S low
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
CC must be ≥ 4.5V for proper operation of WRAL.
V
FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES
CS
CLK
DO
0
DI
1
HIGH-Z
01X
0
•••
Dx
X
•••
status of the
will clear the READY/BUSY status from
DO.
TCSL
D0
TSV
BUSY
READY
WL
T
TCZ
HIGH-Z
VCC must be ≥ 4.5V for proper operation of WRAL.
FIGURE 2-11: WRAL TIMING FOR 93C DEV ICES
CS
CLK
DO
0
DI
1
HIGH-Z
01X
0
•••
X
Dx
•••
D0
TCSL
TSV
BUSY
READY
WL
T
TCZ
HIGH-Z
DS21794B-page 10 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
3.0 PIN DESCRIPTIONS
TABLE 3-1: PIN DESCRIPTIONS
Name
CS 1 5 3 Chip Select
CLK 2 4 4 Serial Clock
DI 3 3 5 Data In
DO 4 1 6 Data Out
SS 527Ground
V
ORG/NC 6 N/A 8 Organizatio n / 93XX56C
NC 7 N/A 1 No Inte rna l Connecti on
VCC 8 6 2 Power Supply
3.1 Chip Select (CS)
A high level sel ects the device; a low lev el deselects
the device and fo rces it into S t andby mo de. Howev er , a
programming cycle wh ic h is al ready in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brou gh t l ow duri ng a p rogram cycle, the
device will go into Standby mode as soon as the
programming cycle is com pleted.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of C LK. Dat a bit s are also c locke d
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing opcode, address and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected (DI = 0), any number of clock cycle s can be
received by the device without changing its status (i.e.,
waiting for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the specified
number of clock cyc le s (re spe ct ive ly low to hi gh tra ns itions of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
SOIC/PDIP/
MSOP/TSSOP
CKL). This gives the controlling master
SOT-23 Rotated SOIC Function
CSL) between
CKH) and
No Internal Connection / 93XX56A/B
data bits b efor e an instruction is executed. CL K and DI
then become don't care inputs wait ing for a new ST AR T
condition to be detected.
3.3 Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address and data synchronously with the CLK input.
3.4 Data Out (DO)
Data Out (DO) is use d in the Read m ode to outpu t data
synchronou sly with th e CLK input (T
tive edge of CLK).
This pin also provides READY/BUSY
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum Chip Select
low time (T
has been initiated.
The Status signal is not available on DO, if CS is held
low during th e entire ERASE or W RITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the d ata line will be hig h
to indicate the device is ready.
Note: Issuing a ST ART bit and then taking C S low
CSL) and an ERASE or WRITE operation
will clear the READY/BUSY
DO.
3.5 Organization (ORG)
When the ORG pin i s connected to VCC or Logic HI, th e
(x16) memory organiza tion is sel ected. Whe n the ORG
pin is tied to V
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX56A devices are always x8 organization and
93XX56B devices are always x16 organization.
SS or Logic LO, the (x8) memory
PD after the posi-
status informa-
status from
2003 Microchip Technology Inc. DS21794B-page 11
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
8-Lead MSOP (150 mil)
XXXXXXT
YWWNNN
6-Lead SOT-23
XXNN
8-Lead PDIP
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC
Example:
3L56BI
2281L7
Example:
2EL7
Example:
93LC56B
I/P 1L7
0228
Example:
MSOP 1st Line Marking Codes
Device
93AA56A
93AA56B
93AA56C
93LC56A
93LC56B
93LC56C
93C56A
93C56B
93C56C
T = blank for commercial, “I” for Industrial,
“E” for Extended.
SOT23 Marking Codes
Device
93AA56A
93AA56B
93LC56A
93LC56B
93C56A
93C56B
Pb-free topside mark is same; Pb-free
noted only on carton label.
std mark
3A56AT
3A56BT
3A56CT
3L56AT
3L56BT
3L56CT
3C56AT
3C56BT
3C56CT
I-temp
2BNN
2LNN
2ENN
2PNN
2HNN
2TNN
Pb-free
mark
GA56AT
GA56BT
GA56CT
GL56AT
GL56BT
GL56CT
GC56AT
GC56BT
GC56CT
E-temp
–
–
2FNN
2RNN
2JNN
2UNN
XXXXXXXX
XXXXYYWW
NNN
8-Lead TSSOP
XXXX
TYWW
NNN
Legend: XX...X Part number
T Temperature
Blank Commercial
I Industrial
E Extended
YY Year code (last 2 digits of calendar year) except TSSOP
and MSOP which use only the last 1 digit
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: Custom marking available.
93LC56B
I/SN 0228
1L7
Example:
L56B
I228
1L7
TSSOP 1st Line Marking Codes
Device
93AA56A
93AA56B
93AA56C
93LC56A
93LC56B
93LC56C
93C56A
93C56B
93C56C
Temperature grade is marked on line 2.
std mark
A56A
A56B
A56C
L56A
L56B
L56C
C56A
C56B
C56C
Pb-free
mark
GABA
GABB
GABC
GLBA
GLBB
GLBC
GCBA
GCBB
GCBC
DS21794B-page 12 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n 1
α
A
c
(F)
β
Units
Dimension Limits
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
A2
A1
E1
MIN
n
p
A
E
D
L
φ
c
B
α
β
.026 BSC
.030
.000
.193 TYP.
.118 BSC
.118 BSC
.016 .024
.037 REFFFootprint (Reference)
0° - 8°
.003
.009
5°
5° -
L
INCHES
NOM
.033
.006
.012
φ
A1
MAX NOM
8
--
-
-
.043
.037
.006
.031
.009
.016
15°
15°
MIN
0.75
0.00
0.40
0.08
0.22
MILLIMETERS*
MAX
8
0.65 BSC
--
0.85
-
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
0°
-
-
-
A2
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°5° 15°5° -
2003 Microchip Technology Inc. DS21794B-page 13
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
6-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
B
n
c
β
Number of Pins
Pitch
Outside lead pitch (basic)
Molded Package Thickness
Standoff
Molded Package Width
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
n
p
p1
A2
A1
E1
φ
c
α
β
p1
D
1
A
φ
NOM
A1
MINMAX
L
MINDimension Limits
α
A2
MILLIMETERSINCHES*Units
NOM
0.95.038
1.90.075
MAX
66
1.451.180.90.057.046.035AOverall Height
1.301.100.90.051.043.035
0.150.080.00.006.003.000
3.002.802.60.118.110.102EOverall Width
1.751.631.50.069.064.059
3.102.952.80.122.116.110DOverall Length
0.550.450.35.022.018.014LFoot Length
10501050
0.200.150.09.008.006.004
0.500.430.35.020.017.014BLead Width
10501050
10501050
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
DS21794B-page 14 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
E
β
eB
Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
Dimension Limits MIN NOM MAX MIN NOM MAX
1
α
A
c
Units INCHES* MILLIMETERS
n
p
c
α
β
.008 .012 .015 0.20 0.29 0.38
A1
B1
B
88
.100 2.54
51015 51015
51015 51015
A2
L
p
2003 Microchip Technology Inc. DS21794B-page 15
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
n
45°
c
β
n
p
A1
φ
c
α
β
1
h
A
φ
L
048048
A1
MILLIMETERSINCHES*Units
1.27.050
α
A2
MAXNOMMINMAXNOMMINDimension Limits
88
1.751.551.35.069.061.053AOverall Height
1.551.421.32.061.056.052A2Molded Packag e Thickness
0.250.180.10.010.007.004
6.206.025.79.244.237.228EOverall Width
3.993.913.71.157.154.146E1Molded Package Width
5.004.904.80.197.193.189DOverall Length
0.510.380.25.020.015.010hChamfer Distance
0.760.620.48.030.025.019LFoot Length
0.250.230.20.010.009.008
0.510.420.33.020.017.013BLead Width
1512015120
1512015120
DS21794B-page 16 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
n
B
1
A
c
A1
φ
β
A1
n
p
φ
c
α
β
048048
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickne ss
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
L
MILLIMETERS*INCHESUnits
0.65.026
α
A2
MAXNOMMINMAXNOMMINDimension Limits
88
1.10.043AOverall Height
0.950.900.85.037.035.033A2Molded Package Thickness
0.150.100.05.006.004.002
6.506.386.25.256.251.246EOverall Width
4.504.404.30.177.173.169E1Molded Package Width
3.103.002.90.122.118.114DMolded Package Length
0.700.600.50.028.024.020LFoot Length
0.200.150.09.008.006.004
0.300.250.19.012.010.007BLead Width
10501050
10501050
2003 Microchip Technology Inc. DS21794B-page 17
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
APPENDIX A: REVISION HISTORY
Revision B
Corrections to Section 1.0, Electrical Characteristics.
Section 4.1, 6-Lead SOT-23 package to OT.
DS21794B-page 18 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used b y Mic rochip as a me ans to m ake
files and information easily available to customers. To
view the site, the use r must have access to the Intern et
and a web browser, such as Netscape
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web Site
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Micr ochip specific bu siness informatio n is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for p roducts, D evelopment Systems,
technical information and more
• Listing of seminars and events
®
or Microsoft
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
®
Plus, this line provides information on how customers
can receive the most c urrent upgrade kit s. The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
042003
2003 Microchip Technology Inc. DS21794B-page 19
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
READER RESPONSE
It is our intentio n to pro vi de you with the best documentation possible to ens ure suc c es sfu l u se of y ou r M ic roc hip product. If you wish to provid e your c omment s on org anizatio n, clarity, subject matter , and ways in w hich our d ocument atio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
RE: Reader Response
From:
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
Technical Publications Manager
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Total Pages Sent ________
FAX: (______) _________ - _________
DS21794B93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21794B-page 20 2003 Microchip Technology Inc.
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X
Device
X
Pinout
X
Tape & Reel
Temperature
/XX
Package
Range
Device 93AA56A: 2K 1.8V Mic r owire Serial EEPROM
Pinout: Blank = Standard pinout
Tape & Reel: Blank = Standard packaging
Temperature Range I = -40°C to +85°C
Package MS = Plastic MSOP (Micro Small outline, 8-lead)
93AA56B: 2K 1.8V Microwire Serial EEPROM
93AA56C: 2K 1.8V Microwire Serial EEPROM w/ORG
93LC56A: 2K 2.5V Microwire Serial EEPROM
93LC56B: 2K 2.5V Microwire Serial EEPROM
93LC56C: 2K 2.5V Microwire Serial EEPROM w/ORG
93C56A: 2K 5.0V Microwire Serial EEPROM
93C56B: 2K 5.0V Microwire Serial EEPROM
93C56C: 2K 5.0V Microwire Serial EEPROM w/ORG
X = Rotated pino ut
T=Tape & Reel
E = -40°C to +125°C
OT = SOT-23, 6-lead (Tape & Reel only)
P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (150 mil body), 8-lead
ST = TSSOP, 8-lead
X
Lead Finish
Examples:
a) 93AA56C-I/MS: 2K, 256x8 or 128x16 Serial
EEPROM, MSOP package, 1.8V
b) 93AA56B-I/MS: 2K, 128x16 Serial EEPROM,
MSOP package, 1.8V
c) 93AA56AT-I/OT: 2K, 256x8 Serial EEPROM,
SOT-23 package, tape and reel, 1.8V
d) 93AA56CT-I/MS: 2K, 256x 8 or 128x16 Serial
EEPROM, MSOP package, tape and reel, 1.8V
a) 93LC56A-I/MS: 2K, 256x8 Serial EEPROM,
MSOP package, 2.5V
b) 93LC56BT-I/OT: 2K, 128x16 Serial EEPROM,
SOT-23 package, tape and reel, 2.5V
c) 93LC56B-I/MS: 2K, 128x16 Serial EEPROM,
MSOP package, 2.5V
d) 93LC56BXT-I/SNG: 2K, 128x16 Serial
EEPROM, SOIC package, rotated pinout,
Industrial temperature, Pb-free finish, 2.5V
a) 93C56B-I/MS: 2K, 128x16 Serial EEPROM,
MSOP package, 5.0V
b) 93C56C-I/MS: 2K, 256x8 or 128x16 Serial
EEPROM, MSOP package, 5.0V
c) 93C56AT-I/OT: 2K, 256x8 Serial EEPROM,
SOT-23 package, tape and reel, 5.0V
Lead Finish: Blank = Standard 63% / 37% SnPb
G = Pure Matte Sn
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc. DS21794B-page 21
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
NOTES:
DS21794B-page 22 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• Th ere are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protection fea tures of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, MPLAB, PIC, PICmic ro, PI C START,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PI CMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
2003 Microchip Technology Inc. DS21794B-page 23
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-72 00
Fax: 480-792-7277
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China - Fuzhou
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Far East International Plaza
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China - Shenzhen
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Tel: 86-755-8 290 13 80
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China - Shunde
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Tel: 86-765-8395507 Fax: 86-765-8395571
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
India
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-47 1- 616 6 Fax: 81-4 5-4 71 -6122
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshir e, England RG41 5T U
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
DS21794B-page 24 2003 Microchip Technology Inc.
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