MICROCHIP 93AA46A, 93AA46B, 93AA46C, 93LC46A, 93LC46B Technical data

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1K Microwire Compatible Serial EEPROM

Device Selection Table

93AA46A/B/C, 93LC46A/B/C,

93C46A/B/C

Part Number V

93AA46A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT, MC 93AA46B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT, MC 93LC46A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC 93LC46B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC 93C46A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC 93C46B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC 93AA46C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS, MC 93LC46C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC 93C46C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC

Features:

• Low-power CMOS technology

• ORG pin to select word size for ‘46C’ version

• 128 x 8-bit organization ‘A’ version devices (no ORG)

• 64 x 16-bit organization ‘B’ version devices (no ORG)

• Self-timed erase/write cycles (including auto-erase)

• Automatic ERAL before WRAL

• Power-on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device St atus signal (Ready/Busy

• Sequential read function

• 1,000,000 E/W cycles

• Data retention > 200 years

• Temperature ranges supported:

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

CC Range ORG Pin Word S ize Temp Ranges Packages

Description:

The Microchip Technology Inc. 93XX46A/B/C devices are 1K bit low-voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93AA46C, 93LC46C or 93C46C are dependent upon external logic levels driving the ORG pin to set word size. For dedicated 8-bit communication, the 93AA46A, 93LC46A or 93C46A devices are available, while the 93AA46B, 93LC46B and 93C46B devices provide dedicated 16-bit communication. Advanced CMOS technology makes these devices ideal for low power, nonvolatile memory applications. The entire 93XX Series is available in standard packages includ-

)

ing 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish is also available.

Pin Function Table

Name Function

CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output V

SS Ground

NC No internal connection ORG Memory Configur atio n

CC Power Supply

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

Package Types (not to scale)

ROTATED SOIC (ex: 93LC46BX)

2 3

CLK

8 7 6 5

ORG*

V DO DI

CLK

PDIP/SOIC

(P, SN)

NC ORG V

TSSOP/MSOP

(ST, MS)

CLK

* ORG pin is NC on A/B devices

CLK

8 7 6 5

V NC ORG* V

DFN

8 7 6 5

VCC NC ORG* V

SOT-23

(OT)

1 2 3

CLK

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stres ses above those listed under “Absolute Max im um Rat ing s” m ay cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the opera tional lis tings of thi s specifica tion is not implied. Expo sure to max imum rating conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All parameters apply over the specified ranges unless otherwise noted.

Param.

No.

D1 V

D2 VIL1

D3 VOL1

D4 V

Symbol Parameter Min Typ Max Units Conditions

IH1 IH2

High-level input voltage 2.0

Low-level input voltage -0.3

IL2

Low-level output voltage —

OL2

High-lev el output voltage 2.4

OH1 OH2

Industrial (I): T Automotive (E): T

0.7 VCC

-0.3

—

VCC - 0.2—— D5 ILI Input leakage current — — ±1 μAVIN = VSS or VCC D6 ILO Output leakage current — — ±1 μAVOUT = VSS or VCC D7 CIN,

OUT

D8 I

write

Pin capacitance

——7pFVIN/VOUT = 0V (Note 1)

(all inputs/outputs) Write current —

—

D9 ICC read Read current —

— —

D10 ICCS Standby current —

—

D11 VPOR VCC voltage detect

— —

Note 1: This parameter is periodically sampled and not 100% tested.

2: ORG pin not available on ‘A’ or ‘B’ versions. 3: Ready/Busy

status must be cleared from DO, see Section3.4 "Data Out (DO)".

A = -40°C to +85°C, VCC = +1.8V TO +5.5V A = -40°C to +125°C, VCC = +2.5V TO +5.5 V

——VCC +1

CC +1

— —

0.8

0.2 VCC

0.4

0.2 —

—

500

— —

100

— —

—

500

—

1 5

VVV

CC ≥ 2.7V CC < 2.7V

VVVCC ≥ 2.7V

CC < 2.7V

VVI

OL = 2.1 mA, VCC = 4.5V OL = 100 μA, VCC = 2.5V

VVI

OH = -400 μA, VCC = 4.5V OH = -100 μA, VCC = 2.5V

A = 25°C, FCLK = 1 MHz

mAμAFCLK = 3 MHz, VCC = 5.5V

CLK = 2 MHz, VCC = 2.5V

FCLK = 3 MHz, VCC = 5.5V

μA

CLK = 2 MHz, VCC = 3.0V

μA

CLK = 2 MHz, VCC = 2.5V

μA

I-Temp

μA

E-Temp CLK = CS = 0V ORG = DI = V

(Note 2) (N (Note 1)

1.5

3.8

— —

93AA46A/B/C, 93LC46A/B/C

93C46A/B/C

SS or VCC

OTE 3)

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

TABLE 1-2: AC CHARACTERISTICS

All parameters apply over the speci fied ranges unless otherwise noted.

Industrial (I): T Automotive (E): T

A = -40°C to +85°C, VCC = +1.8V TO +5.5V A = -40°C to +125°C, VCC = +2.5V TO +5.5V

Param.

No.

A1 F

A2 TCKH Clock high time 200

A3 TCKL Clock low time 100

A4 TCSS Chip Select setup time 50

Symbol Parameter Min Max Units Conditions

CLK Clock frequency — 3

250 450

200 450

100 250

MHz

—ns

4.5V ≤ VCC < 5.5V, 93XX46C only

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC < 5.5V, 93XX46C only

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC < 5.5V, 93XX46C only

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC < 5.5V

2.5V ≤ V

1.8V ≤ V

CC < 5.5V CC < 2.5V

CC < 4.5V CC < 2.5V

A5 TCSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V A6 TCSL C h ip Sele ct low t ime 250 — ns 1 .8V ≤ VCC < 5.5V A7 T

DIS Data input setup time 50

—ns4.5V ≤ V 100 250

A8 T

DIH Data input hold time 50

—ns4.5V ≤ V 100 250

A9 T

A10 T

PD Data output delay time —

— —

CZ Data output disable time —

—

200 250 400

100 200

A11 TSV Status valid time — 200

300 500

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

1.8V ≤ V

ns 4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

ns 4.5V ≤ VCC < 5.5V, (Note 1)

1.8V ≤ V

ns 4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ V

1.8V ≤ V

CC < 5.5V, 93XX46C only CC < 5.5V CC < 2.5V

CC < 5.5V, CL = 100 pF CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF

CC < 4.5V, (Note 1)

CC < 4.5V, CL = 100 pF CC < 2.5V, CL = 100 pF

A12 TWC Program cycle time — 6 ms Erase/Write mode (AA and LC

versions)

A13 T

WC — 2 ms Erase/Write mode (93C versions)

A14 TEC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V A15 T

WL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V

A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This application is not tested but ensured by characterization. For endurance estimates in a specific

application, ple ase consult t he Total Endurance™ Model wh ich may be obtained from Microc hip’s web site at www.microchip.com.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

FIGURE 1-1 : SYNCHRONOUS DA TA TIMING

VIL

VIH

CLK

VIL

TDIS

VIH

VIL

VOH

(Read)

(Program)

Note: TSV is relative to CS .

VOL VOH

VOL

CSS

TCKH

TDIH

TPD

TCKL

Status Valid

TPD

TCSH

TCZ

TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY)9 ERAL 1 00 10XXXX — (RDY/BSY

EWDS 1 00 00XXXX — High-Z 9 EWEN 1 00 11XXXX — High-Z 9 READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY WRAL 1 00 01XXXXD15 - D0 (RDY/BSY

)25 )25

TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY ERAL 1 00 10XXXXX — (RDY/BSY

EWDS 1 00 00XXXXX —High-Z 10 EWEN 1 00 11XXXXX —High-Z 10 READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18 WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY WRAL 1 00 01XXXXX D7 - D0 (RDY/BSY

)10 )10

)18 )18

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.0 FUNCTIONAL DESCRIPTION

When the ORG pin (93XX46C) is connected to VCC, the (x16) organization is selected. When it is co nnected to ground, the (x8) organization is selected. Instructions, addresses and write dat a are cl oc ke d into the DI pin on the rising edge of the clock (CLK). Th e DO pin is normally he ld in a High-Z stat e except when read ing data from the device, or when checking the Ready/

status during a programming operation. The

Busy Ready/Busy write operation by polli ng the DO pin; DO low ind icate s that programming is still in progress, while DO high indicates the device is ready. DO will enter the High-Z state on the falling edge of CS.

2.1 Start Condition

The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.

Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL or WRAL). As soon as CS is high, the device is no longer in Standby mode.

An instruction following a Start condition will only be executed if the requi red opcode, address and data bits for any particular instruction are clocked in.

Note: When preparing to transm it an i ns truc tio n,

2.2 Data In/Data Out (DI/DO)

status can be verified during an erase/

either the CLK or DI signal levels must be at a logic low as CS is toggled active high.

2.3 Data Protection

All modes of operation ar e inhibited when VCC is below a typical voltage of 1.5V for '93AA' and '93LC' devices or 3.8V for '93C' devices.

The EWEN and EWDS commands give additional protection against accidentally programming during normal operation.

Note: For added protection, an EWDS

command should be performed after every write operation and an external 10 kΩ pull-down protection res istor sho uld be added to the CS pin.

After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed.

Block Diagram

CC VSS

Address Decoder

Address

Counter

Output

Buffer

ORG*

Memory

Array

Data Register

Mode

Decode

Logic

It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefine d and will depend upon the rela tive impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO.

CLK

*ORG input is not avai lable on A/B devices

Clock

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.4 Erase

The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed

The DO pin indicates the Ready/Busy device if CS is brought high after a minimum of 250 ns low (TCSL). D O at logical ‘ 0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been erased and the device is ready for another instruction.

programming cycle , exc ept on ‘93C ’ dev ices w here th e rising edge of CLK before the last address bit initiates

Note: After the Erase cycle is complete, issuing

the write cycle.

FIGURE 2-1 : ERASE TI MI NG FOR 9 3A A AN D 93L C D EVIC E S

CSL

CLK

111A

High-Z

AN-1 AN-2

•••

status of the

a St art bit and then taki ng CS lo w will c lear the Ready/Busy s tatus from DO .

Check Status

SV TCZ

Busy Ready

High-Z

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

CLK

111A

High-Z

AN-1 AN-2

•••

CSL

Check Status

SV TCZ

Busy Ready

High-Z

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.5 Erase All (ERAL)

The Erase Al l (ERAL) instruction will erase the entire

The DO pin indicates the Ready/Busy device, if CS is brough t high a fter a minimum of 250 n s low (TCSL).

memory array to the logical ‘1’ state. The ERAL cycle is identical to the erase cycle, except for the different

Note: After the ERAL command is complete,

opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS, except on ‘93C’ devices where the rising edge of CLK before the last data bit initiates the write cycle. Clocking of the

VCC must be ≥ 4.5V for proper operation of ERAL.

CLK pin is not necessary after the device has entered the ERAL cycle.

FIGURE 2-3 : ERAL TIM IN G FO R 93 AA A ND 9 3L C DE VI C ES

CSL

CLK

100 10x

High-Z

•••

status of the

issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO.

Check Status

SV TCZ

Busy Ready

High-Z

VCC must be ≥ 4.5V for proper operation of ERAL.

FIGURE 2-4: ERAL TIMIN G FOR 93 C DEVI CES

CLK

100 10x

High-Z

•••

CSL

Check Status

SV TCZ

Busy Ready

TEC

High-Z

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.6 Erase/Write Disable and Enable (EWDS/EWEN)

The 93XX46A/B/C powers up in the Erase/Write Disable (EWDS) state. All Programming modes must be

preceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or Vcc is removed from the device.

FIGURE 2-5: EWDS TIMING

CLK

FIGURE 2-6: EWEN TIMING

000x

To protect against accidental data disturbance, the EWDS instruction can be used to disable all erase/write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.

CSL

•••

TCSL

CLK

00 1 1x

2.7 Read

The READ instruction outputs the serial data of the addressed memory lo cation on the DO pin. A dummy zero bit precedes the 8-bit (if ORG pin is low or A-Version devices) or 16-bit (if ORG pin is high or B-version devices) output string.

FIGURE 2-7 : READ TIMI N G

CLK

110

••• A0

•••

The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (T

PD).

Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output se qu en ti ally.

High-Z

0 Dx

•••

D0 Dx

•••

Dx D0

•••

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.8 Write

The WRITE i nstruction is followed by 8 bits (i f ORG is low or A-version devices) or 16 bits (if ORG pin is high or B-version devices) of data which are wr itten into th e specified address. For 93AA46A/B/C and 93LC46A/B/C devices, after the last data bit is clocked into DI, the

The DO pin indicates the Ready/Busy device, if CS is brough t high a fter a minimum of 250 n s low (TCSL). D O at logical ‘ 0’ indicates that programming is still in pro gress. DO at log ical ‘1’ indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction.

falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93 C46A/ B/C d evices , the se lf-

Note: After the Write cy cle is c omplete, issuing a

timed auto-erase and pr ogramming cycle is initiated by the rising edge of CLK on the last data bit.

FIGURE 2-8 : WRITE T I MI NG FOR 93AA AND 93LC DEV I CES

TCSL

CLK

High-Z

1 An

•••

A0 Dx

•••

status of the

Start bit and then taking CS low will clear the Ready/Busy status from DO.

TSV

Busy

Ready

TCZ

High-Z

FIGURE 2-9: WRITE TIMING FOR 93C DEVICES

CLK

High-Z

1 An

•••

A0 Dx

•••

TCSL

TWC

TSV

Busy

Ready

TCZ

High-Z

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.9 Write All (WRAL)

The Write All (WRAL) instruction will write the entire

The DO pin indicates the Ready/Busy device if CS is brought high after a minimum of 250 ns low (TCSL).

memory array with the data specified in the command. For 93AA46A/B/C and 93LC 46A/B/C de vices , after th e

Note: After the Write All cycle is complete,

last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93C46A/B/C devices, the self-timed autoerase and programming cycle is initiated by the rising

VCC must be ≥ 4.5V for proper operation of WRAL.

edge of CLK on the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction, but the chip must be in the EWEN status.

FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES

CLK

01 x

•••

Dx •••

status of the

issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO.

TCSL

TSV

TCZ

VCC must be ≥ 4.5V for proper operation of WRAL.

High-Z

FIGURE 2-11: WRAL TIMING FOR 93C DEVICES

CLK

High-Z

01 x

•••

Dx •••

TCSL

Ready

Busy

TSV

Busy

Ready

IGH-Z

TCZ

IGH-Z

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN DESCRIPTIONS

SOIC/PDIP/

Name

CS 1 5 3 Chip Select CLK 2 4 4 Serial Clock DI 3 3 5 Data In DO 4 1 6 Data Out Vss 5 2 7 Ground ORG/NC 6 — 8 Organization / 93XX46C

NC 7 — 1 No Internal Connection

CC 8 6 2 Power Supply

MSOP/

TSSOP/DFN

SOT-23 Rotated SOIC Function

No Internal Connection / 93XX46A/B

3.1 Chip Select (CS)

A high level sel ects the device; a low lev el deselects the device and fo rces it into S t andby mo de. Howev er , a programming cycle wh ic h is al ready in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brou gh t l ow duri ng a p rogram cycle, the device will go into Standby mode as soon as the programming cycle is com pleted.

CS must be low for 250 ns minimum (T consecutive instructions. If CS is low, the internal control logic is held in a Reset status.

CSL) between

3.2 Serial Clock (CLK)

The Serial Clock is used to synchronize the communication between a master device and the 93XX series device. Opcodes, address and data bits are clocked in on the positive edge of C LK. Dat a bit s are also c locke d out on the positive edge of CLK.

CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T clock low time (T freedom in preparing opcode, address and data.

CLK is a “don't care” if CS is l ow (devic e desele cted). If CS is high, but the Start condition has not been detected (D I = 0), any number of clock cycles can be received by the device without changing its status (i.e., waiting for a Start condition).

CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle.

After detection of a Sta rt condition t he specified numb er of clock cycl es (respectivel y low-to-high tr ansitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits b efo re a n in struction is executed. CLK an d DI then become “don't care” i npu ts waiting for a new Start condition to be detected.

CKL). This gives the controlling master

CKH) and

3.3 Data In (DI)

Data In (DI) is used to clock in a Start bit, opcode, address and data synchronously with the CLK input.

3.4 Data Out (DO)

Data Out (DO) is use d in the Read m ode to outpu t data synchronously with the CLK input (T positive edge of CLK).

This pin also provides Ready/Busy during erase and write c ycles. Ready/Bu sy mation is available on the DO pin if CS is brought high after being low for minimum Chip Select low time (T and an erase or write operation has been initiated.

The Status signal is not available on DO, if CS is held low during the entire erase or write cycle. In this case, DO is in the High-Z mode. If st atus is check ed after th e erase/write cycle, the data line will be high to indicate the device is ready.

Note: After a programming cycle is complete,

issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO.

PD after the

status inf ormation

status infor-

CSL)

3.5 Organization (ORG)

When the ORG pin i s connected to VCC or Logic HI, th e (x16) memory organiza tion is sel ected. Whe n the ORG pin is tied to V organization is selected. For proper operation, ORG must be tied to a valid logic level.

93XX46A devices are always x8 organization and 93XX46B devices are always x16 organization.

SS or Logic LO, the (x8) memory

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

8-Lead MSOP (150 mil)

XXXXXXT

YWWNNN

6-Lead SOT-23

XXNN

8-Lead PDIP

XXXXXXXX T/XXXNNN

YYWW

8-Lead SOIC

Example:

3L46BI

5281L7

Example:

1EL7

Example:

93LC46B I/P 1L7

0528

Example:

XXXXXXXT XXXXYYWW

NNN

8-Lead TSSOP

XXXX TYWW NNN

8-Lead 2x3 DFN

XXX YWW

93LC46BI

SN 0528

1L7

Example:

L46B I528 1L7

Example:

314 528 L7

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

1st Line Marking Codes

Part Number

93AA46A A46A 3A46AT 1BNN — 301 — 93AA46B A46B 3A46BT 1LNN — 311 — 93AA46C A46C 3A46CT — — 321 — 93LC46A L46A 3L46AT 1ENN 1FNN 304 305 93LC46B L46B 3L46BT 1PNN 1RNN 314 315 93LC46C L46C 3L46CT — — 324 325 93C46A C46A 3C46AT 1HNN 1JNN 307 308 93C46B C46B 3C46BT 1TNN 1UNN 317 318 93C46C C46C 3C46CT — — 327 328

Note: T = Temperature grade (I, E)

NN = Alphanumeric traceability code

Legend: XX...X Part number or part number code

TSSOP MSOP

T Temperature (I, E) Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01 ’) NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

I Temp. E Temp. I Temp. E Temp.

SOT-23 DFN

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Microchip part number can not be ma rked on one line , it wil

be carried over to the next line, thus limiting the number of available characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

n 1

(F)

Units

Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length

Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom

*Controlling Parameter Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

JEDEC Equivalent: MO-187

Drawing No. C04-111

A2 A1

MIN

n p

D L

.026 BSC

.030 .000

.193 TYP.

.118 BSC .118 BSC

.016 .024

.037 REFFFootprint (Reference)

0° - 8° .003 .009

5°

5° -

INCHES

NOM

.033

.006 .012

MAX NOM

.043 .037 .006

.031

.009 .016

15° 15°

MIN

0.75

0.00

0.40

0.08

0.22

MILLIMETERS*

MAX

0.65 BSC

0.85

4.90 BSC

3.00 BSC

0.60

0.95 REF

0°

1.10

0.95

0.15

0.80

8°

0.23

0.40 15°5° 15°5° -

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

6-Lead Plastic Small Outline Transistor (OT) (SOT-23)

Number of Pins Pitch Outside lead pitch (basic)

Molded Package Thickness Standoff

erall Width

Molded Package Width

Foot Angle Lead Thickness

Mold Draft Angle Top Mold Draft Angle Bottom

*Controlling Parameter Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

n p

A2 A1

α β

NOM

MINMAX

MINDimension Limits

MILLIMETERSINCHES*Units

NOM

0.95.038

1.90.075

MAX

1.451.180.90.057.046.035AOverall Height

1.301.100.90.051.043.035

0.150.080.00.006.003.000

3.002.802.60.118.110.102EOv

1.751.631.50.069.064.059

3.102.952.80.122.116.110DOverall Length

0.550.450.35.022.018.014LFoot Length 10501050

0.200.150.09.008.006.004

0.500.430.35.020.017.014BLead Width 10501050 10501050

JEITA (formerly EIAJ) equivalent: SC-74A

Drawing No. C04-120

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Number of Pins Pitch Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32 Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68 Base to Seating Plane A1 .015 0.38 Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26 Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60 Overall Length D .360 .373 .385 9.14 9.46 9.78 Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43 Lead Thickness Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78 Lower Lead Width B .014 .018 .022 0.36 0.46 0.56 Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92 Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018

Dimension Limits MIN NOM MAX MIN NOM MAX

Units INCHES* MILLIMETERS

n p

α β

.008 .012 .015 0.20 0.29 0.38

.100 2.54

51015 51015 51015 51015

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Number of Pins Pitch

Standoff §

Foot Angle Lead Thickness

Mold Draft Angle Top Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057

45°

n p

α β

048048

MILLIMETERSINCHES*Units

1.27.050

MAXNOMMINMAXNOMMINDimension Limits

1.751.551.35.069.061.053AOverall Height

1.551.421.32.061.056.052A2Molded Packag e Thickness

0.250.180.10.010.007.004

6.206.025.79.244.237.228EOverall Width

3.993.913.71.157.154.146E1Molded Package Width

5.004.904.80.197.193.189DOverall Length

0.510.380.25.020.015.010hChamfer Distance

0.760.620.48.030.025.019LFoot Length

0.250.230.20.010.009.008

0.510.420.33.020.017.013BLead Width 1512015120 1512015120

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

Units

n p

α β

048048

Number of Pins Pitch

Standoff §

Foot Angle Lead Thickne ss

Mold Draft Angle Top Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086

MILLIMETERS*INCHES

0.65.026

MAXNOMMINMAXNOMMINDimension Limits

1.10.043AOverall Height

0.950.900.85.037.035.033A2Molded Package Thickness

0.150.100.05.006.004.002

6.506.386.25.256.251.246EOverall Width

4.504.404.30.177.173.169E1Molded Package Width

3.103.002.90.122.118.114DMolded Package Length

0.700.600.50.028.024.020LFoot Length

0.200.150.09.008.006.004

0.300.250.19.012.010.007BLead Width 10501050 10501050

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated

PIN 1

ID INDEX

AREA

(NOTE 2)

TOP VIEW

Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length

(Note

Exposed Pad Length Overall Width Exposed Pad Width Contact Width Contact Length

*Controlling Parameter Notes:

Package may have one or more exposed tie bars at ends.1. Pin 1 visual index feature may vary, but must be located within the hatched area.2.

Exposed pad dimensions vary with paddle size.

4. JEDEC equivalent: MO-229

Drawing No. C04-123

Units

n p

b L

EXPOSED

MIN

.031 .000 .001

.055

.047 .008 .012

METAL

PAD

BOTTOM VIEW

EXPOSED

TIE BAR

(NOTE 1)

INCHES

NOM

.020 BSC

.039

.002 .008 REF. .079 BSC

-- --

.118 BSC

-- -.010 .016

.064

.071 .012 .020

MINMAX NOM

0.80

0.00

1.39

1.20

0.20

0.30

MILLIMETERS*

0.50 BSC

0.90.035

0.02

0.20 REF.

2.00 BSC

3.00 BSC

0.25

0.40

Revised 05/24/04

MAX

1.00

0.05

1.62

1.80

0.30

0.50

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

APPENDIX A: REVISION HISTORY

Revision D

Corrections to Section 1.0, Electrical Characteristics. Section 4.1, 6-Lead SOT-23 package to OT.

Revision E

Added DFN package.

Revision F

Added notes throughout.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

NOTES:

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

THE MICROCHIP WEB SITE

Microchip provides onlin e support v ia our W WW site at www.m ic roc hi p.c om . Thi s web si te i s us ed as a m ean s to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, lat est softwa re releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultan t program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of s eminars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified produ ct family or develo pment tool of inte rest.

To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sal es Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line Customers should contact their distributor,

representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

T echnic al support is avail able throug h the web si te at: http://support.microchip.com

In addition, there is a Development Systems Information Line which lists the latest versions of Microchip’s development systems software products. This line also provides information on how customers can receive currently available upgrade kits.

The Development Systems Information Line numbers ar e:

1-800-755-2345 – United States and most of Canada 1-480-792-7302 – Other International Locations

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

READER RESPONSE

It is our intentio n to pro vi de you with the best documentation possible to ens ure suc c es sfu l u se of y ou r M ic roc hip product. If you wish to provid e your c omment s on org anizatio n, clarity, subject matter , and ways in wh ich our d ocument ation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: RE: Reader Response From:

Application (optional): Would you like a reply? Y N

Device: Literature Number: Questions:

1. What are the best features of this d ocument?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

Technical Publications Manager

Name Company

Address City / State / ZIP / Country

Te lephone: (_______) _________ - _________

Total Pages Sent ________

FAX: (______) _________ - _________

DS21749F93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X

Device

Pinout

Tape & Reel

Temperature

/XX

Package

Range

Device: 93AA46A: 1K 1.8V Microwire S erial EEPROM

Pinout: Bl a nk = Standard pinout

Tape & Reel: Blank = Standard packaging

Temperature Range: I = -40°C to +85°C

93AA46B: 1K 1.8V Microwire Serial EEPROM 93AA46C: 1K 1.8V Microwire Serial EEPROM w/ORG

93LC46A: 1K 2.5V Microwire Serial EEPROM 93LC46B: 1K 2.5V Microwire Serial EEPROM 93LC46C: 1K 2.5V Microwire Serial EEPROM w/ORG

93C46A: 1K 5.0V Microwire Serial EEPROM 93C46B: 1K 5.0V Microwire Serial EEPROM 93C46C: 1K 5.0V Microwire Serial EEPROM w/ORG

X = Rotated pinout

T = Tape & Reel

E = -40°C to +125°C

Lead Finish

Examples:

a) 93AA46C-I/MS: 1K, 128x8 or 64x16 Serial

EEPROM, MSOP package, 1.8V

b) 93AA46B-I/MS: 1K, 64x16 Serial EEPROM,

MSOP package, 1.8V

c) 93AA46AT-I/OT: 1K, 128x8 Serial EEPROM,

SOT-23 package, tape and reel, 1.8V

d) 93AA46CT-I/MS: 1K, 128x8 or 16x16 Serial

EEPROM, MSOP package, tape and reel, 1.8V

a) 93LC46A-I/MS: 1K, 128x8 Serial EEPROM,

MSOP package, 2.5V

b) 93LC46BT-I/OT: 1K, 64x16 Serial EEPROM,

SOT-23 package, tape and reel, 2.5V

c) 93LC46B-I/MS: 1K, 64x16 Serial EEPROM,

MSOP package, 2.5V

a) 93C46B-I/MS: 1K, 64x16 Serial EEPROM,

MSOP package, 5.0V

b) 93C46C-I/MS: 1K, 128x8 or 16x16 Serial

EEPROM, MSOP package, 5.0V

c) 93C46AT-I/OT: 1K, 128x8 Serial EEPROM,

SOT-23 package, tape and reel, 5.0V

Package: MS = Plastic MSOP (Micro Small outline, 8-lead)

Lead Finish: Blank = Pb-free – Matte Tin (see Note 1)

OT = SOT-23, 6-lead (Tape & Reel only) P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (150 mil body), 8-lead ST = TSSOP, 8-lead MC = 2x3 DFN, 8-lead

G = Pb-free – Matte Tin only

Note: Mos t products manufactured after January 2005 will have a Ma tte Tin (Pb-free) finish. Most products manufactured

before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb). Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

NOTES:

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protect ion f eatures of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Mill ennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. Use of M icrochip’s prod ucts as critical components in life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLI NK, MPSIM, PICkit , PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

8-bit MCUs, KEELOQ

code hopping

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com

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Tel: 39-0331-742611 Fax: 39-0331-466781

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Tel: 31-416-690399 Fax: 31-416-690340

England - Berkshire

Tel: 44-118-921-5869 Fax: 44-118-921-5820

04/20/05

MICROCHIP 93AA46A, 93AA46B, 93AA46C, 93LC46A, 93LC46B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 ELECTRICAL CHARACTERISTICS

TABLE 1-1: DC CHARACTERISTICS

TABLE 1-2: AC CHARACTERISTICS

FIGURE 1-1 : SYNCHRONOUS DA TA TIMING

TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)

2.0 FUNCTIONAL DESCRIPTION

FIGURE 2-1 : ERASE TI MI NG FOR 9 3A A AN D 93L C D EVIC E S

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

FIGURE 2-3 : ERAL TIM IN G FO R 93 AA A ND 9 3L C DE VI C ES

FIGURE 2-4: ERAL TIMIN G FOR 93 C DEVI CES

FIGURE 2-5: EWDS TIMING

FIGURE 2-6: EWEN TIMING

FIGURE 2-7 : READ TIMI N G

FIGURE 2-8 : WRITE T I MI NG FOR 93AA AND 93LC DEV I CES

FIGURE 2-9: WRITE TIMING FOR 93C DEVICES

FIGURE 2-10: WRAL TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-11: WRAL TIMING FOR 93C DEVICES

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN DESCRIPTIONS

4.0 PACKAGING INFORMATION

THE MICROCHIP WEB SITE

CUSTOMER CHANGE NOTIFICATION SERVICE

CUSTOMER SUPPORT

READER RESPONSE

PRODUCT IDENTIFICATION SYSTEM

Trademarks

WORLDWIDE SALES AND SERVICE