MICROCHIP 93AA46A, 93AA46B, 93AA46C, 93LC46A, 93LC46B Technical data

1K Microwire Compatible Serial EEPROM

Device Selection Table

93AA46A/B/C, 93LC46A/B/C,

93C46A/B/C

Part Number V

93AA46A 1.8-5.5 No 8-bit I P, SN, ST, MS, OT, MC
93AA46B 1.8-5-5 No 16-bit I P, SN, ST, MS, OT, MC
93LC46A 2.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC
93LC46B 2.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC
93C46A 4.5-5.5 No 8-bit I, E P, SN, ST, MS, OT, MC
93C46B 4.5-5.5 No 16-bit I, E P, SN, ST, MS, OT, MC
93AA46C 1.8-5.5 Yes 8 or 16-bit I P, SN, ST, MS, MC
93LC46C 2.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC
93C46C 4.5-5.5 Yes 8 or 16-bit I, E P, SN, ST, MS, MC

Features:

• Low-power CMOS technology

• ORG pin to select word size for ‘46C’ version

• 128 x 8-bit organization ‘A’ version devices
(no ORG)

• 64 x 16-bit organization ‘B’ version devices
(no ORG)

• Self-timed erase/write cycles (including
auto-erase)

• Automatic ERAL before WRAL

• Power-on/off data protection circuitry

• Industry standard 3-wire serial I/O

• Device St atus signal (Ready/Busy

• Sequential read function

• 1,000,000 E/W cycles

• Data retention > 200 years

• Temperature ranges supported:

- Industrial (I) -40°C to +85°C

- Automotive (E) -40°C to +125°C

CC Range ORG Pin Word S ize Temp Ranges Packages

Description:

The Microchip Technology Inc. 93XX46A/B/C devices
are 1K bit low-voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages includ-

)

ing 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3
DFN and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish
is also available.

Pin Function Table

Name Function

CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
V

SS Ground

NC No internal connection
ORG Memory Configur atio n

CC Power Supply

V

© 2005 Microchip Technology Inc. DS21749F-page 1

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

Package Types (not to scale)

ROTATED SOIC
(ex: 93LC46BX)

NC

1

V

CC

2
3

CS

4

CLK

8
7
6
5

ORG*

SS

V
DO
DI

CS

CLK

DI

DO

PDIP/SOIC

(P, SN)

1

8

2

7

3

6

4

5

V

CC

NC
ORG
V

SS

*

TSSOP/MSOP

(ST, MS)

1

CS

2

CLK

3

DI

4

DO

* ORG pin is NC on A/B devices

CS

CLK

DI

DO

8
7
6
5

V
NC
ORG*
V

1

2

3

4

CC

SS

DFN

V

8
7
6
5

DO

SS

DI

VCC
NC
ORG*
V

SS

SOT-23

(OT)

1
2
3

6

V

CC

5

CS

4

CLK

DS21749F-page 2 © 2005 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ..........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stres ses above those listed under “Absolute Max im um Rat ing s” m ay cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the opera tional lis tings of thi s specifica tion is not implied. Expo sure to max imum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

All parameters apply over the specified
ranges unless otherwise noted.

Param.

No.

D1 V

D2 VIL1

D3 VOL1

D4 V

Symbol Parameter Min Typ Max Units Conditions

IH1
IH2

V

High-level input voltage 2.0

Low-level input voltage -0.3

V

IL2

Low-level output voltage —

OL2

V

High-lev el output voltage 2.4

V

OH1
OH2

Industrial (I): T
Automotive (E): T

0.7 VCC

-0.3

—

VCC - 0.2——
D5 ILI Input leakage current — — ±1 μAVIN = VSS or VCC
D6 ILO Output leakage current — — ±1 μAVOUT = VSS or VCC
D7 CIN,

OUT

C

D8 I

CC

write

Pin capacitance

——7pFVIN/VOUT = 0V (Note 1)

(all inputs/outputs)
Write current —

—

D9 ICC read Read current —

—
—

D10 ICCS Standby current —

—

D11 VPOR VCC voltage detect

—
—

Note 1: This parameter is periodically sampled and not 100% tested.

2: ORG pin not available on ‘A’ or ‘B’ versions.
3: Ready/Busy

status must be cleared from DO, see Section3.4 "Data Out (DO)".

A = -40°C to +85°C, VCC = +1.8V TO +5.5V
A = -40°C to +125°C, VCC = +2.5V TO +5.5 V

——VCC +1

CC +1

V

—
—

—
—

0.8

0.2 VCC

0.4

0.2
—

—

—

500

—
—

100

—
—

2

—

1

500

—

1
5

VVV

CC ≥ 2.7V
CC < 2.7V

V

VVVCC ≥ 2.7V

V

CC < 2.7V

VVI

OL = 2.1 mA, VCC = 4.5V
OL = 100 μA, VCC = 2.5V

I

VVI

OH = -400 μA, VCC = 4.5V
OH = -100 μA, VCC = 2.5V

I

A = 25°C, FCLK = 1 MHz

T

mAμAFCLK = 3 MHz, VCC = 5.5V

CLK = 2 MHz, VCC = 2.5V

F

mA

FCLK = 3 MHz, VCC = 5.5V

μA

F

CLK = 2 MHz, VCC = 3.0V

μA

CLK = 2 MHz, VCC = 2.5V

F

μA

I-Temp

μA

E-Temp
CLK = CS = 0V
ORG = DI = V

(Note 2) (N
(Note 1)

1.5

3.8

—
—

V

93AA46A/B/C, 93LC46A/B/C

V

93C46A/B/C

SS or VCC

OTE 3)

© 2005 Microchip Technology Inc. DS21749F-page 3

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

TABLE 1-2: AC CHARACTERISTICS

All parameters apply over the speci fied
ranges unless otherwise noted.

Industrial (I): T
Automotive (E): T

A = -40°C to +85°C, VCC = +1.8V TO +5.5V
A = -40°C to +125°C, VCC = +2.5V TO +5.5V

Param.

No.

A1 F

A2 TCKH Clock high time 200

A3 TCKL Clock low time 100

A4 TCSS Chip Select setup time 50

Symbol Parameter Min Max Units Conditions

CLK Clock frequency — 3

250
450

200
450

100
250

MHz

2

MHz

1

MHz

—ns

—ns

—ns

4.5V ≤ VCC < 5.5V, 93XX46C only

2.5V ≤ V

1.8V ≤ V

4.5V ≤ VCC < 5.5V, 93XX46C only

ns

2.5V ≤ V

1.8V ≤ V

ns

4.5V ≤ VCC < 5.5V, 93XX46C only

ns

2.5V ≤ V

1.8V ≤ V

ns

4.5V ≤ VCC < 5.5V

ns

2.5V ≤ V

1.8V ≤ V

ns

CC < 5.5V
CC < 2.5V

CC < 5.5V
CC < 2.5V

CC < 5.5V
CC < 2.5V

CC < 4.5V
CC < 2.5V

A5 TCSH Chip Select hold time 0 — ns 1.8V ≤ VCC < 5.5V
A6 TCSL C h ip Sele ct low t ime 250 — ns 1 .8V ≤ VCC < 5.5V
A7 T

DIS Data input setup time 50

—ns4.5V ≤ V
100
250

A8 T

DIH Data input hold time 50

—ns4.5V ≤ V
100
250

A9 T

A10 T

PD Data output delay time —

—
—

CZ Data output disable time —

—

200
250
400

100
200

A11 TSV Status valid time — 200

300
500

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

1.8V ≤ V

ns 4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

ns 4.5V ≤ VCC < 5.5V, (Note 1)

1.8V ≤ V

ns 4.5V ≤ VCC < 5.5V, CL = 100 pF

2.5V ≤ V

1.8V ≤ V

CC < 5.5V, 93XX46C only
CC < 5.5V
CC < 2.5V

CC < 5.5V, 93XX46C only
CC < 5.5V
CC < 2.5V

CC < 5.5V, CL = 100 pF
CC < 4.5V, CL = 100 pF
CC < 2.5V, CL = 100 pF

CC < 4.5V, (Note 1)

CC < 4.5V, CL = 100 pF
CC < 2.5V, CL = 100 pF

A12 TWC Program cycle time — 6 ms Erase/Write mode (AA and LC

versions)

A13 T

WC — 2 ms Erase/Write mode (93C versions)

A14 TEC — 6 ms ERAL mode, 4.5V ≤ VCC ≤ 5.5V
A15 T

WL — 15 ms WRAL mode, 4.5V ≤ VCC ≤ 5.5V

A16 — Endurance 1M — cycles 25°C, VCC = 5.0V, (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This application is not tested but ensured by characterization. For endurance estimates in a specific

application, ple ase consult t he Total Endurance™ Model wh ich may be obtained from Microc hip’s web site
at www.microchip.com.

DS21749F-page 4 © 2005 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

FIGURE 1-1 : SYNCHRONOUS DA TA TIMING

V

IH

CS

T

VIL

VIH

CLK

VIL

TDIS

VIH

DI

VIL

VOH

DO

(Read)

(Program)

Note: TSV is relative to CS .

DO

VOL
VOH

VOL

T

SV

CSS

TCKH

TDIH

TPD

TCKL

Status Valid

TPD

TCSH

TCZ

TCZ

TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE 1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY)9
ERAL 1 00 10XXXX — (RDY/BSY

)9

EWDS 1 00 00XXXX — High-Z 9
EWEN 1 00 11XXXX — High-Z 9
READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25
WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY
WRAL 1 00 01XXXXD15 - D0 (RDY/BSY

)25
)25

TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)

Instruction SB Opcode Address Data In Data Out Req. CLK Cycles

ERASE 1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY
ERAL 1 00 10XXXXX — (RDY/BSY

EWDS 1 00 00XXXXX —High-Z 10
EWEN 1 00 11XXXXX —High-Z 10
READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18
WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY
WRAL 1 00 01XXXXX D7 - D0 (RDY/BSY

)10
)10

)18
)18

© 2005 Microchip Technology Inc. DS21749F-page 5

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.0 FUNCTIONAL DESCRIPTION

When the ORG pin (93XX46C) is connected to VCC,
the (x16) organization is selected. When it is co nnected
to ground, the (x8) organization is selected. Instruc­tions, addresses and write dat a are cl oc ke d into the DI
pin on the rising edge of the clock (CLK). Th e DO pin is
normally he ld in a High-Z stat e except when read ing
data from the device, or when checking the Ready/

status during a programming operation. The

Busy
Ready/Busy
write operation by polli ng the DO pin; DO low ind icate s
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.

2.1 Start Condition

The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.

Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.

An instruction following a Start condition will only be
executed if the requi red opcode, address and data bits
for any particular instruction are clocked in.

Note: When preparing to transm it an i ns truc tio n,

2.2 Data In/Data Out (DI/DO)

status can be verified during an erase/

either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.

2.3 Data Protection

All modes of operation ar e inhibited when VCC is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.

The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.

Note: For added protection, an EWDS

command should be performed after
every write operation and an external 10
kΩ pull-down protection res istor sho uld be
added to the CS pin.

After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.

Block Diagram

CC VSS

V

Address
Decoder

Address

Counter

Output

Buffer

DO

DI

ORG*

CS

Memory

Array

Data Register

Mode

Decode

Logic

It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefine d and will depend upon the rela tive
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.

DS21749F-page 6 © 2005 Microchip Technology Inc.

CLK

*ORG input is not avai lable on A/B devices

Clock

Register

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.4 Erase

The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed

The DO pin indicates the Ready/Busy
device if CS is brought high after a minimum of 250 ns
low (TCSL). D O at logical ‘ 0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.

programming cycle , exc ept on ‘93C ’ dev ices w here th e
rising edge of CLK before the last address bit initiates

Note: After the Erase cycle is complete, issuing

the write cycle.

FIGURE 2-1 : ERASE TI MI NG FOR 9 3A A AN D 93L C D EVIC E S

T

CSL

CS

CLK

DI

DO

111A

High-Z

N

AN-1 AN-2

•••

A0

status of the

a St art bit and then taki ng CS lo w will c lear
the Ready/Busy s tatus from DO .

Check Status

SV TCZ

T

Busy Ready

High-Z

FIGURE 2-2: ERASE TIMING FOR 93C DEVICES

CS

CLK

DI

DO

111A

High-Z

N

AN-1 AN-2

•••

A0

T

CSL

WC

T

Check Status

SV TCZ

T

Busy Ready

WC

T

High-Z

© 2005 Microchip Technology Inc. DS21749F-page 7

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.5 Erase All (ERAL)

The Erase Al l (ERAL) instruction will erase the entire

The DO pin indicates the Ready/Busy
device, if CS is brough t high a fter a minimum of 250 n s
low (TCSL).

memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different

Note: After the ERAL command is complete,

opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the

VCC must be ≥ 4.5V for proper operation of ERAL.

CLK pin is not necessary after the device has entered
the ERAL cycle.

FIGURE 2-3 : ERAL TIM IN G FO R 93 AA A ND 9 3L C DE VI C ES

CSL

T

CS

CLK

DI

DO

100 10x

High-Z

•••

x

status of the

issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.

Check Status

SV TCZ

T

Busy Ready

High-Z

VCC must be ≥ 4.5V for proper operation of ERAL.

FIGURE 2-4: ERAL TIMIN G FOR 93 C DEVI CES

CS

CLK

DI

DO

100 10x

High-Z

•••

EC

T

T

CSL

Check Status

x

SV TCZ

T

Busy Ready

TEC

High-Z

DS21749F-page 8 © 2005 Microchip Technology Inc.

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C

2.6 Erase/Write Disable and Enable
(EWDS/EWEN)

The 93XX46A/B/C powers up in the Erase/Write Disable
(EWDS) state. All Programming modes must be

preceded by an Erase/Write Enable (EWEN) instruction.

Once the EWEN instruction is executed, programming
remains enabled until an EWDS instruction is executed or
Vcc is removed from the device.

FIGURE 2-5: EWDS TIMING

CS

CLK

DI

10

FIGURE 2-6: EWEN TIMING

CS

000x

To protect against accidental data disturbance, the EWDS
instruction can be used to disable all erase/write functions
and should follow all programming operations. Execution
of a READ instruction is independent of both the EWEN and
EWDS instructions.

CSL

T

•••

x

TCSL

CLK

00 1 1x

DI

1x

2.7 Read

The READ instruction outputs the serial data of the
addressed memory lo cation on the DO pin. A dummy
zero bit precedes the 8-bit (if ORG pin is low or A-Version
devices) or 16-bit (if ORG pin is high or B-version
devices) output string.

FIGURE 2-7 : READ TIMI N G

CS

CLK

DI

110

An

••• A0

•••

The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (T

PD).

Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output se qu en ti ally.

DO

© 2005 Microchip Technology Inc. DS21749F-page 9

High-Z

0 Dx

•••

D0 Dx

•••

D0

Dx D0

•••