25AA6401.8-5.5V1 MHzI
25LC6402.5-5.5V2 MHzI
25LC6404.5-5.5V3/2.5 MHzI, E
VCC
Range
Max Clock
Frequency
Features
• Low-power CMOS technology
- Write current: 3 mA typical
- Read current: 500
- Standby current: 500 nA typical
• 8192 x 8 bit organization
• 32 byte page
• Write cycle time: 5 ms max.
• Self-timed erase and write cycles
• Block write protection
- Protect none, 1/4, 1/2 or all of array
• Built-in write protect ion
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC and TSSOP packages
• Temperature ranges supported:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
µA typical
Temp
Ranges
Description
The Microchip Technology Inc. 25AA640/25LC640
(25XX640
PROM [EEPROM]. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the dev ice is contro lled th rough a C hip
Select (CS
Communication to the device can be paused via the
hold pin (HOLD
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
*
) is a 64 Kbit Serial Electrically Erasable
) input.
). While the device is paused,
Block Diagram
SO
CS
SCK
HOLD
WP
SI
Status
Register
I/O Control
Logic
VCC
VSS
Memory
Control
Logic
XDEC
HV Generator
EEPROM
Array
Page
Latches
Y Decoder
Sense Amp.
R/W Control
Package Types
PDIP/SOICTSSOP
CS
1
25XX640
SO
2
WP
3
VSS
4
*25XX640 is used in this document as a generic part number for the 25AA640/25LC640 devices.
SPI is a registered trademark of Motorola Corporation.
SS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-65°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
HOOutput Hold Time0—ns(Note 1)
DISOutput Disable Time—
—
—
16T
HSHOLD Setup Time100
100
200
17T
HHHOLD Hold Time100
100
200
18T
HZHOLD Low to Outpu t
High-Z
100
150
200
19T
HVHOLD High to Output
Valid
100
150
200
20T
WCInternal Write Cycle
—5ms
Time
21—Endurance1M—E/W
Note 1: This parameter is periodically sampled and not 100% tested.
2: F
CLK max. = 2.5 MHz for TA > 85°C.
3: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from our web site.
A = -40°C to +85°CVCC = 1.8V to 5.5V
A = -40°C to +125°CVCC = 4.5V to 5.5V
3
2
1
MHz
MHz
MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
230
475
200
250
500
—
—
—
—
—
—
—
—
—
—
—
—
Cycles
CC = 4.5V to 5.5V (Note 2)
V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
ns
VCC = 4.5V to 5.5V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
V
CC = 1.8V to 5.5V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
V
CC = 1.8V to 5.5V
CC = 4.5V to 5.5V
V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
CC = 4.5V to 5.5V
V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
V
CC = 2.5V to 5.5V
CC = 1.8V to 5.5V
V
CC = 4.5V to 5.5V (Note 1)
V
CC = 2.5V to 5.5V (Note 1)
V
CC = 1.8V to 5.5V (Note 1)
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V (Note 1)
CC = 2.5V to 5.5V (Note 1)
V
CC = 1.8V to 5.5V (Note 1)
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
V
CC = 1.8V to 5.5V
(Note 3)
2004 Microchip Technology Inc.DS21223G-page 3
25AA640/25LC640
FIGURE 1-1:HOLD TIMING
CS
161617
SCK
SO
n + 2n + 1nn - 1
17
High-impedance
1918
n
SI
HOLD
n + 2n + 1n
FIGURE 1-2:SERIAL INPUT TIMING
CS
SCK
SI
SO
2
Mode 1,1
Mode 0,0
65
MSB In
High-impedance
7
Don’t Care
8
3
LSB In
5
n
n - 1
4
12
11
FIGURE 1-3:SERIAL OUTPUT TIMING
CS
9
10
SCK
13
SO
SI
DS21223G-page 4 2004 Microchip Technology Inc.
MSB Out
Don’t Care
14
3
Mode 1,1
Mode 0,0
15
LSB Out
25AA640/25LC640
TABLE 1-3:AC TEST CONDITIONSFIGURE 1-4:AC TEST CIRCUIT
AC Waveform:
VLO = 0.2V
HI = VCC – 0.2V (Note 1)
V
VHI = 4.0V (Note 2)
Timing Measurement Reference Lev el
Input0.5 V
Output0.5 VCC
Note 1: For VCC≤ 4.0V
2: For V
CC > 4.0V
CC
SO
VCC
2.25 kΩ
1.8 kΩ
100 pF
2004 Microchip Technology Inc.DS21223G-page 5
25AA640/25LC640
2.0PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:PIN FUNCTION TABLE
NamePDIPSOICTSSOPDescription
CS
SO224Serial Data Output
WP
SS44 6Ground
V
SI557Serial Data Input
SCK668Serial Clock Input
HOLD
V
CC882Supply Voltage
2.1Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardle ss of
the CS
high during a program cycle, the device will go into
Standby mode when the programming cycle is
complete. When the device is deselected, SO goes to
the high-impedance state, allowing multiple parts to
share the same SPI bus. A low-to-hi gh transition on CS
after a valid write sequence initiates an internal write
cycle. After power-up, a high-to-lo w trans itio n on CS
required prior to any sequence being initiated.
113Chip Select Input
335Write-Protect Pin
771Hold Input
input signal. If CS is brought high, or remains
is
2.4Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.5Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX640. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of t he c lo ck input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX640 while in the middle of a seri al sequ ence wit hout having to retransmit the entire sequence over
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX640 must remain selected
during this sequenc e. The SI, SC K, an d SO p ins a re i n
a high-impedance state during the time the device is
paused and transitions on these p ins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
pin may be pulled
must be brought
2.2Serial Output (SO)
The SO pin is used to transfer data out of the 25XX640.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the no nvolatil e bits in the Status register
is disabled. All other operations function normally.
When WP
nonvolatile bits in the Status register operate normally.
If the WPEN bit is set, WP low during a Status register
write sequence will disable writing to the Status register. If an internal write cycle has already begun, WP
going low will have no effect on the write.
The WP
the Status register is low. This allows the user to install
the 25XX640 in a system with WP
still be able to write to the Status register. The WP
functions will be enabled when the WPEN bit is set
high.
is high, all functions, including writes to the
pin function is blocked when the WPEN bit in
pin grounded and
pin
DS21223G-page 6 2004 Microchip Technology Inc.
25AA640/25LC640
3.0FUNCTIONAL DESCRIPTION
3.1Principles Of Operation
The 25XX640 is a 8192 byte Serial EEPROM desi gned
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers
that do not hav e a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX640 conta ins an 8-bit instr uction regi ster . The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
be low and the HOLD
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data is sampled on the fir st rising edge of SCK after CS
goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD
mode. After releasing the HOLD
resume from the point when the HOLD
input and place the 25XX640 in ‘HOLD’
pin must be high fo r the entire
pin, operation will
3.2Read Sequence
The device is sele cted by p ulling CS low. The 8-bit read
instruction is transmitted to the 25XX640 followed by
the 16-bit address with the three MSBs of the address
being don’t care bits. After the correct read instruction
and address are sent, the d ata st ored i n the memo ry at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continu ing to provide clock pul ses.
The internal address pointer is automatically incremented to the next higher address after each byte of
data is shifted out. When the highest address is
reached (1FFFh), the address counter rolls over to
address 0000h allow in g th e rea d c yc le to b e co nti nue d
indefinitely. The read operation i s term inated by rai sing
pin (Figure 3-1).
the CS
pin must
was asserted.
3.3Write Sequence
Prior to any attempt to wri t e d at a to the 25XX6 40 arra y
or St atus regis ter, the write enable lat ch mus t be s et by
issuing the WREN instruction (Figure 3-4). This is done
by setting CS
instruction into the 25XX640. After all eight bits of the
instruction are transmitted, the CS
high to set the write enable latch. If the write operation
is initiated immediately after the WREN instruction without CS
to the array because the write enable latch will no t have
been properly set.
Once the write enable latch is set, the user may
proceed by setting the CS
instruction, followed by the address, and then the data
to be written. Up to 32 bytes of data can be sent to the
25XX640 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with XXX0 0000
and ends with XXX1 1111. If the internal address
counter reaches XXX1 1111 and the clock continues,
the counter will roll bac k to the first add ress of the p age
and overwrite any da ta in the p age that m ay have bee n
written.
For the data to be actually written to the array, the CS
must be brought high after the Leas t Significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
low and then clocking out the proper
must be brought
being brought high, the data will not be written
low, issuing a WRITE
th
data byte has been clocked in. If CS is
TABLE 3-1:INSTRUCTION SET
Instruction NameInstruction FormatDescription
READ0000 0011Read data from memory array beginning at selected address
WRITE0000 0010Write data to memory array beginning at selected address
WREN0000 0110Set the write enable latch (enable write operations)
WRDI0000 0100Reset the write enable latch (disable write operations)
RDSR0000 0101Read Status register
WRSR0000 0001Write Status register
2004 Microchip Technology Inc.DS21223G-page 7
25AA640/25LC640
FIGURE 3-1:READ SEQUENCE
CS
023456789101121222324252627282930311
SCK
Instruction16 Bit Address
SI
0100000115 14 13 12210
High-impedance
SO
FIGURE 3-2:BYTE WRITE SEQUENCE
CS
Instruction16 Bit AddressData Byte
SI
SO
0000000115 14 13 1221076543210
High-impedance
FIGURE 3-3:PAGE WRITE SEQUENCE
CS
8
910112122232425262728293031
SCK
SI
02345671
Instruction16 Bit AddressData Byte 1
0000000115 14 13 12
Data Out
76543210
Twc
21076543210
CS
3234 35 36 37 38 3933
SCK
Data Byte 2
SI
DS21223G-page 8 2004 Microchip Technology Inc.
76543210
41 42 4346 47
40
Data Byte 3
76543210
44 45
Data Byte n (32 max)
76543210
25AA640/25LC640
3.4Write Enable (WREN) and
Write Disable (WRDI)
The 25XX640 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation w ill be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 3-4:WRITE ENABLE SEQUENCE
CS
02345671
SCK
SI
SO
01000001
High-impedance
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
FIGURE 3-5:WRITE DISABLE SEQUENCE
CS
02345671
SCK
SI
SO
01000001
High-impedance
0
2004 Microchip Technology Inc.DS21223G-page 9
25AA640/25LC640
3.5Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
7654 3 2 1 0
WPENXXXBP1BP0WELWIP
The Write-In-Process (WIP) bit indicates whether the
25XX640 is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Wri te Enable Lat ch (WEL) bit indicat es the st atus
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array and Status register, when set
to a ‘0’, the latch proh ibits writes to the array and St atus
register . Th e st a te of this b it ca n alw ays be updat ed via
the WREN or WRDI com m and s regardless of the state
of write protection on the Status register. This bit is
read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
FIGURE 3-6:READ STATUS REGISTER TIMING SEQUENCE
CS
9101112131415
SCK
SI
023456718
Instruction
11000000
SO
High-impedance
Data from Status Register
7654210
3
DS21223G-page 10 2004 Microchip Technology Inc.
25AA640/25LC640
3.6Write Status Register Instruction
TABLE 3-2:ARRAY PROTECTION
(WRSR)
The Write S t atus Regis ter inst ruction (WRSR) all ows the
user to select one of four levels of protection for the
array by writing to the appropriate bi ts in the S t atus register. The array is divided up into four segments. The
user has the ability to write-protect none, one, two, or
all four of the segment s of the arra y. The partitioning is
controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bi t for the WP
Write-Protect (WP
(WPEN) bit in the Status register control the programmable hardware write-protect feature. Hardware write
protection is enabled when the WP
WPEN bit is high. Hardw are write protec tion is disa bled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See T a ble 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-7 for WRSR timing sequence.
) pin and the Write-Protect Enable
pin is low and the
pin. The
FIGURE 3-7:WRITE STATUS REGISTER TIMING SEQUENCE
BP1BP0
00none
01upper 1/4
10 upper 1/2
11all
Array Addresses
Write-Protected
(1800h-1FFFh)
(1000h-1FFFh)
(0000h-1FFFh)
CS
SCK
SI
SO
02345671
8
9101112131415
InstructionData to Status Register
01000000
High-impedance
7654
210
3
2004 Microchip Technology Inc.DS21223G-page 11
25AA640/25LC640
3.7Data Protection
The following protection has been implemented to
prevent in advertent w rites to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write, or Status register
write, the write enable latch is reset
must be set high after the proper number of
•CS
clock cycles to start an internal write cycle
• Access to the array during an intern al write cycl e
XX 0 ProtectedProtectedProtected
0X 1 ProtectedWritableWritable
1Low1ProtectedWritableProtected
XHigh1ProtectedWritableWritable
DS21223G-page 12 2004 Microchip Technology Inc.
4.0PACKAGING INFORMATION
4.1Package Marking Information
25AA640/25LC640
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXX
XXXXYYWW
NNN
8-Lead TSSOP
XXXX
YYWW
NNN
Example:
25LC640
/P017
0410
Example:
25LC640
I/SN0410
017
Example:
5LCX
0410
017
Legend: XX...X Customer specific information*
YYYear code (last 2 digits of calendar year)
WWWeek code (week of January 1 is week ‘01’)
NNNAlphanumeric traceability code
Note:In the event the full Microchip part numbe r cannot be ma rked on on e line, it will
be carried over to the next line thus limiti ng the number of available characters
for customer specific information.
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
2004 Microchip Technology Inc.DS21223G-page 13
25AA640/25LC640
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
E
β
eB
Number of Pins
Pitch
Top to Seating PlaneA.140.155.1703.563.944.32
Molded Package ThicknessA2.115.130.1452.923.303.68
Base to Seating PlaneA1.0150.38
Shoulder to Shoulder WidthE.300.313.3257.627.948.26
Molded Package WidthE1.240.250.2606.106.356.60
Overall LengthD.360.373.3859.149.469.78
Tip to Seating PlaneL.125.130.1353.183.303.43
Lead Thickness
Upper Lead WidthB1.045.058.0701.141.461.78
Lower Lead WidthB.014.018.0220.360.460.56
Overall Row Spacing§eB.310.370.4307.879.4010.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
Dimension LimitsMINNOMMAXMINNOMMAX
1
α
A
c
UnitsINCHES*MILLIMETERS
n
p
c
α
β
.008.012.0150.200.290.38
A1
B1
B
88
.1002.54
51015 51015
51015 51015
A2
L
p
DS21223G-page 14 2004 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
25AA640/25LC640
B
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
Corrections to Section 1.0, Electrical Characteristics.
Revision G
Product ID System, Example C: Corrected part
number, added “Alternate Pinout” and corrected part
number in Header.
Updated Trademark and Sales List pages.
25AA640/25LC640
2004 Microchip Technology Inc.DS21223G-page 17
25AA640/25LC640
NOTES:
DS21223G-page 18 2004 Microchip Technology Inc.
25AA640/25LC640
ON-LINE SUPPORT
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World Wide Web site.
The web site is used b y Mic rochip as a me ans to m ake
files and information easily available to customers. To
view the site, the use r must have access to the Intern et
and a web browser, such as Netscape
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web Site
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Micr ochip specific bu siness informatio n is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
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Questions
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®
Plus, this line provides information on how customers
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Numbers are:
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042003
2004 Microchip Technology Inc.DS21223G-page 19
25AA640/25LC640
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DS21223G25AA640/25LC640
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DS21223G-page 20 2004 Microchip Technology Inc.
25AA640/25LC640
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.X/XX
Device
Device25AA640:64K bit 1.8V SPI Serial EEPROM
Range
25AA640T: 64K bit 1.8V SPI Serial EEPROM
25AA640X: 64K bit 1.8V SPI Serial EEPROM
25AA640XT: 64K bit 1.8V SPI Serial EEPROM
25LC640:64K bit 2.5V SPI Serial EEPROM
25LC640T: 64K bit 2.5V SPI Serial EEPROM
25LC640X: 64K bit 2.5V SPI Serial EEPROM
25LC640XT: 64K bit 2.5V SPI Serial EEPROM
PackageTemperature
(Tape and Reel)
in alternate pinout (ST only)
in alternate pinout Tape and Reel (ST only)
(Tape and Reel)
in alternate pinout (ST only)
in alternate pinout Tape and Reel (ST only)
Examples:
a)25AA640-I/SN: Industrial Temp.,
SOIC package
b)25AA640T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
c)25AA640X-I/ST: Alternate Pinout
Industrial Temp., TSSOP package
d)25LC640-I/SN: Industrial Temp.,
SOIC package
e)25LC640T-I/SN: Tape and Reel,
Industrial Temp., SOIC package
f)25LC640X-I/ST: Alternate Pinout,
Industrial Temp., TSSOP package
Temperature RangeI= -40°C to +85°C
PackageP=Plastic DIP (300 mil Body), 8-lead
E= -40°C to +125°C
SN=Plastic SOIC (150 mil Body), 8-lead
ST=Plastic TSSOP (4.4 mm Body), 8-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.Your local Microchip sales office
2.The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3.The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.DS21223G-page 21
25AA640/25LC640
Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, MPLAB, PIC, PICmic ro, PI C START,
PRO MATE, PowerSmart and rfPIC are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL, SmartShunt and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net,
dsPICworks, ECAN, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, Migratable Memory, MPASM , MPLIB, MP LIN K,
MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode,
SmartSensor, SmartTel and Total Endurance are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
Microchip re cei v ed I S O/T S - 16 949 : 20 02 qu ality system certif i cat i o n for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in October
2003. The Com pany’s quality sy stem proces ses and pro cedures are for
its PICmicro
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
®
8-bit MCUs, KEELOQ
®
code hopping devices, Serial
2004 Microchip Technology Inc.DS21223G-page 23
WORLDWIDE SALESAND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-72 00
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640- 003 4
Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692- 384 8
Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285- 007 1
Fax: 630-285-0075