MICROCHIP 25AA1024, 25LC1024 Technical data

25AA1024/25LC1024

1 Mbit SPI™ Bus Serial Flash

Device Selection Table

Part Number VCC Range Page Size Temp. Ranges Packages

25LC1024 2.5-5.5V 256 Byte I,E P, SM, MF

25AA1024 1.8-5.5V 256 Byte I P, SM, MF

Features

• Max. clock 20 MHz

• Flash and byte-level serial EEPROM operation

• Low-power CMOS technology

- Max. Write Current: 5 mA at 5.5V, 20 MHz

- Read Current: 10 mA at 5.5V, 20 MHz

- Standby Current: 1µA at 5.5V (Deep power­down)

• 131,072 x 8-bit organization

• Byte and Page (256 byte page) Write Operations
(5 ms max.)

• Electronic Signature for device ID

• Self-timed ERASE and WRITE cycles

- Sector Erase (1 second/sector typical)

- Bulk Erase (2 seconds typical)

• Sector write protection (32K byte/sector)

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• High reliability

- Endurance: 100,000 erase/write cycles

• Temperature ranges supported;

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

• Standard and Pb-free packages available

Pin Function Table

Name Function

Description

The Microchip Technology Inc. 25AA1024/25LC1024
(25XX1024
Flash memory with both Flash and byte-level serial
EEPROM functions. The memory is accessed via a
simple Serial Peripheral Interface™ (SPI™) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled by a Chip Select (CS
input.

Communication to the device can be paused via the
hold pin (HOLD
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.

The 25XX1024 is available in standard packages
including 8-lead PDIP and SOIC, and advanced 8-lead
DFN package. Pb-free (Pure Sn) finish is also
available.

*

) is a 1024 Kbit serial reprogrammable

). While the device is paused, transi-

Package Types (not to scale)

CS

SO

WP

VSS

1

2

3

4

DFN

(MF)

25LC1024

8

7

6

5

VCC

HOLD

SCK

SI

PDIP/SOIC

(P, SM)

CS

1
2

SO

3

WP

V

SS

4

25LC1024

V

8
7

HOLD

6

SCK

SI

5

CC

)

CS

Chip Select Input

SPI is a registered trademark of Motorola Semiconductor.

SO Serial Data Output

WP

V

SS Ground

Write-Protect

SI Serial Data Input

SCK Serial Clock Input

HOLD

V

CC Supply Voltage

 2003 Microchip Technology Inc. Preliminary DS21836A-page 1

Hold Input

*25XX1024 is used in this document as a generic part number
for the 25AA1024, 25LC1024 devices.

25AA1024/25LC1024

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

D001 V

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input

Industrial (I): T
Automotive (E): T

.7 VCC VCC +1 V

voltage

D002 V

D003 V

D004 V

D005 V

D006 V

IL1 Low-level input

IL2 -0.3 0.2 VCC VVCC < 2.7V

OL Low-level output

OL —0.2VIOL = 1.0 mA, VCC < 2.5V

OH High-level output

voltage

voltage

-0.3 0.3 VCC VVCC ≥ 2.7V

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH = -400 µA

voltage

D007 I

LI Input leakage current ±1 µACS = VCC, VIN = VSS TO VCC

D008 ILO Output leakage

current

D009 CINT Internal capacitance

— 7 pF TA = 25°C, CLK = 1.0 MHz,
(all inputs and
outputs)

D010 I

CC Read

—

—
Operating current

D011 I

CC Write —

—

D012 I

D13 I

CCS

Standby current

CCSPD Deep power-down

—

—

—1µACS = VCC = 5.5V, Inputs tied to VCC or
current

Note: This parameter is periodically sampled and not 100% tested.

A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 2.5V to 5.5V

±1 µACS = VCC, VOUT = VSS TO VCC

CC = 5.0V (Note)

V

10

mAmAVCC = 5.5V; FCLK = 20.0 MHz;

SO = Open

5

VCC = 2.5V; FCLK = 10.0 MHz;
SO = Open

5
3

20

10

mAmAVCC = 5.5V

CC = 2.5V

V

µAµACS

= VCC = 5.5V, Inputs tied to VCC or

V

SS, 125°C

= VCC = 5.5V, Inputs tied to VCC or

CS

SS, 85°C

V

SS

V

DS21836A-page 2 Preliminary  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

25AA1024/25LC1024

Industrial (I): T
Automotive (E): T

A = -40°C to +85°C VCC = 1.8V TO 5.5V
A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No.

1F

2T

3T

4T

5 Tsu Data setup time 5

6T

7T

8T

9T

10 T

Sym Characteristic Min Max Units Conditions

CLK Clock frequency —

—
—

CSS CS setup time 25

50

250

CSH CS hold time 50

100
500

CSD CS disable time 50 — ns

20
10

2

—
—
—

—
—
—

—
10
50

HD Data hold time 10

20

100

R CLK rise time — 20 ns (Note 1)

F CLK fall time — 20 ns (Note 1)

HI

Clock high time 25

50

250

LO Clock low time 25

50

—

—

—

—

—

—

—

—

—

—

250

11 T

12 T

13 T

14 T

15 T

16 T

17 T

CLD Clock delay time 50 — ns

CLE Clock enable time 50 — ns

V Output valid from clock

low

HO Output hold time 0 — ns (Note 1)

DIS Output disable time —

HS HOLD setup time 10

HH HOLD hold time 10

—
—
—

—
—

20

100

20

100

25
50

250

25
50

250

—

—

—

—

—

—

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance estimates

in a specific application, please consult the Total Endurance™ Model which can be obtained from our web
site.

3: Includes T

HI time.

MHz
MHz
MHz

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

1.8 ≤ V

CC < 2.5

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V
(Note 3)

CC ≤ 5.5

4.5 ≤ V

2.5 ≤ V

CC < 4.5
CC < 2.5

1.8 ≤ V

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.8 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

1.8 ≤ V

CC < 2.5

(Note 1)

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V

CC < 4.5
CC < 2.5

1.8 ≤ V

 2003 Microchip Technology Inc. Preliminary DS21836A-page 3

25AA1024/25LC1024

TABLE 1-2: (CONTINUED) AC CHARACTERISTICS

AC CHARACTERISTICS

Industrial (I): T
Automotive (E): T

A = -40°C to +85°C VCC = 1.8V TO 5.5V
A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No.

18 Thz HOLD low to output

Sym Characteristic Min Max Units Conditions

High-Z

15
30

150

—
—
—

ns

4.5 ≤ VCC ≤ 5.5

ns

2.5 ≤ V

1.8 ≤ V

ns

CC < 4.5
CC < 2.5

(Note 1)

19 Thv HOLD

20 Trel CS

21 Tpd CS

High to Standby mode — 1.6 µsVCC = 1.8V to 5.5V

High to Deep power-

high to output valid 15

30

150

—1.6µsVCC = 1.8V to 5.5V

—
—
—

ns

4.5 ≤ VCC ≤ 5.5

ns

2.5 ≤ V

ns

1.8 ≤ V

CC < 4.5
CC < 2.5

down

22 Tce Chip erase cycle time — 4 s V

23 Tse Sector erase cycle time — 2 s V

CC = 1.8V to 5.5V

CC = 1.8V to 5.5V

24 Twc Internal write cycle time — 5 ms Byte or Page mode

25 — Endurance 100K — E/W

(Note 2)

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance estimates

in a specific application, please consult the Total Endurance™ Model which can be obtained from our web
site.

3: Includes T

HI time.

TABLE 1-3: AC TEST CONDITIONS

AC Waveform:

LO = 0.2V —

V

V

HI = VCC - 0.2V (Note 1)

HI = 4.0V (Note 2)

V

L = 100 pF —

C

Timing Measurement Reference Level

Input 0.5 V

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V

CC > 4.0V

CC

DS21836A-page 4 Preliminary  2003 Microchip Technology Inc.

FIGURE 1-1: HOLD TIMING

CS

SCK

SO

n+2 n+1 n n-1

16

17

18

25AA1024/25LC1024

high-impedance

16

17

19

n

SI

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

CS

2

Mode 1,1

Mode 0,0

SCK

65

SI

SO

MSB in

high-impedance

don’t care

7

8

LSB in

5

n

3

n-1

4

12

11

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

9

10

SCK

13

SO

SI

 2003 Microchip Technology Inc. Preliminary DS21836A-page 5

MSB out

don’t care

14

3

Mode 1,1

Mode 0,0

15

LSB out

25AA1024/25LC1024

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 25XX1024 is a 131,072 byte Serial Flash designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PICMicro
lers. It may also interface with microcontrollers that do
not have a built-in SPI port by using discrete I/O lines
programmed properly in firmware to match the SPI
protocol.

The 25XX1024 contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
be low and the HOLD
operation.

Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.

Data (SI) is sampled on the first rising edge of SCK
after CS
peripheral devices on the SPI bus, the user can assert
the HOLD
mode. After releasing the HOLD
resume from the point when the HOLD

goes low. If the clock line is shared with other

input and place the 25XX1024 in ‘HOLD’

pin must be high for the entire

®

microcontrol-

pin must

pin, operation will

was asserted.

2.2 Read Sequence

The device is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25XX1024 followed by
the 24-bit address, with seven MSBs of the address
being don’t care bits. After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incre­mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached (1FFFFh), the address counter rolls over to
address 00000h allowing the read cycle to be contin­ued indefinitely. The read operation is terminated by
raising the CS

pin (Figure 2-1).

2.3 Write Sequence

Prior to any attempt to write data to the 25XX1024, the
write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX1024. After all eight bits of the instruction are
transmitted, the CS
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.

Once the write enable latch is set, the user may
proceed by setting the CS
tion, followed by the 24-bit address, with seven MSBs
of the address being don’t care bits, and then the data
to be written. Up to 256 bytes of data can be sent to the
device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.

Note: Page write operations are limited to writing

bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’), and end at addresses that are
integer multiples of page size - 1. If a Page
Write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status Register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.

th

data byte has been clocked in. If CS is

must be brought high to set the

low, issuing a WRITE instruc-

DS21836A-page 6 Preliminary  2003 Microchip Technology Inc.

BLOCK DIAGRAM

25AA1024/25LC1024

SI

SO

CS

SCK

HOLD

WP

Status

Register

I/O Control

Logic

VCC
VSS

Memory

Control

Logic

X

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp.
R/W Control

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register

PE 0100 0010 Page Erase - erase one page in memory array
SE 1101 1000 Sector Erase - erase one sector in memory array
CE 1100 0111 Chip Erase - erase all sectors in memory array

RDID 1010 1011 Release from Deep power-down and read electronic signature

DPD 1011 1001 Deep Power-down mode

FIGURE 2-1: READ SEQUENCE

CS

0 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 391

SCK

instruction 24 Bit Address

SI

SO

 2003 Microchip Technology Inc. Preliminary DS21836A-page 7

0100000 1 23 22 21 20 210

high-impedance

Data Out

76543210

25AA1024/25LC1024

FIGURE 2-2: BYTE WRITE SEQUENCE

CS

8

9 1011 2930313233343536373839

SCK

SI

SO

0 2345671

instruction 24-bit address data byte

0000000 1 23 22 21 20

high-impedance

FIGURE 2-3: PAGE WRITE SEQUENCE

CS

8

9 1011 2930313233343536373839

SCK

SI

CS

0 2345671

instruction 24-bit address data byte 1

0000000 1 23 22 21 20

Twc

21076543210

21076543210

SCK

SI

40 42 43 44 45 46 4741

data byte 2

76543210

49 50 51 54 55

48

76543210

52 53

data byte 3

data byte n (256 max)

76543210

DS21836A-page 8 Preliminary  2003 Microchip Technology Inc.

25AA1024/25LC1024

2.4 Write Enable (WREN) and Write
Disable (WRDI)

The 25XX1024 contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

CS

0 2345671

SCK

SI

SO

010000 01

high-impedance

The following is a list of conditions under which the
write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

CS

02345671

SCK

SI

SO

010000 01

high-impedance

0

 2003 Microchip Technology Inc. Preliminary DS21836A-page 9

25AA1024/25LC1024

2.5 Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides
access to the Status Register. The Status Register may
be read at any time, even during a write cycle. The
Status Register is formatted as follows:

TABLE 2-2: STATUS REGISTER

7 654 3 2 1 0

W/R – – – W/R W/R R R
WPEN X X X BP1 BP0 WEL WIP
W/R = writable/readable. R = read-only.

The Write-In-Process (WIP) bit indicates whether the
25XX1024 is busy with a write operation. When set to

1’, a write is in progress, when set to a ‘0’, no write

a ‘
is in progress. This bit is read-only.

The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘

1’, the latch allows writes to the array, when set to a

0’, the latch prohibits writes to the array. The state of

‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the Status Register. These commands are shown in
Figure 2-4 and Figure 2-5.

The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.

See Figure 2-6 for the RDSR timing sequence.

FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

8

0 2345671

9101112131415

SCK

SO

SI

instruction

high-impedance

11000000

Data from Status Register

7654 2 10

3

DS21836A-page 10 Preliminary  2003 Microchip Technology Inc.

25AA1024/25LC1024

2.6 Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the Status
Register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the Status Register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.

TABLE 2-3: ARRAY PROTECTION

BP1 BP0

00

01

10

11

Array Addresses

Write-Protected

Upper 1/4 (Sector 3)

(18000h - 1FFFFh)

Upper 1/2 (Sectors 2 & 3)

(10000h - 1FFFFh)

All (Sectors 0, 1, 2 & 3)

(00000h - 1FFFFh)

The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP
Write-Protect (WP
(WPEN) bit in the Status Register control the
programmable hardware write-protect feature. Hard­ware write protection is enabled when WP
and the WPEN bit is high. Hardware write protection is
disabled when either the WP
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the Status Register are
disabled. See Table 2-4 for a matrix of functionality on
the WPEN bit.

See Figure 2-7 for the WRSR timing sequence.

none All (Sectors 0, 1, 2 & 3)

) pin and the Write-Protect Enable

pin is high or the WPEN

Array Addresses

Unprotected

(00000h - 1FFFFh)

Lower 3/4 (Sectors 0, 1 & 2)

(00000h - 17FFFh)

Lower 1/2 (Sectors 0 & 1)

(00000h - 0FFFFh)

none

pin. The

pin is low

FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

8

9101112131415

7654

SCK

SO

SI

0 2345671

instruction data to Status Register

01000000

high-impedance

210

3

 2003 Microchip Technology Inc. Preliminary DS21836A-page 11

25AA1024/25LC1024

2.7 Data Protection

The following protection has been implemented to
prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set
the write enable latch

• After a byte write, page write or Status Register
write, the write enable latch is reset

must be set high after the proper number of

•CS
clock cycles to start an internal write cycle

• Access to the array during an internal write cycle
is ignored and programming is continued

2.8 Power-On State

The 25XX1024 powers on in the following state:

• The device is in low-power Standby mode
(CS

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS
enter active state

TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

(SR bit 1)

0xx
10x
1
1

WPEN

(SR bit 7)

1
1

WP

(pin 3)

0 (low)

1 (high)

Protected Blocks Unprotected Blocks Status Register

Protected Protected Protected

Protected Writable Writable

Protected Writable Protected

Protected Writable Writable

x = don’t care

= 1)

is required to

DS21836A-page 12 Preliminary  2003 Microchip Technology Inc.

2.9 PAGE ERASE

25AA1024/25LC1024

The Page Erase function will erase all bits (FFh) inside
the given page. A Write Enable (WREN) instruction
must be given prior to attempting a Page Erase. This
is done by setting CS
proper instruction into the 25XX1024. After all eight
bits of the instruction are transmitted, the CS
brought high to set the write enable latch.

The Page Erase function is entered by driving CS
followed by the instruction code Figure 2-8, and three
address bytes. Any address inside the page to be
erased is a valid address.

low and then clocking out the

must be

low,

FIGURE 2-8: PAGE ERASE SEQUENCE

CS

0 2 3 4 5 6 7 8 9 1011 2930311

SCK

instruction 24-bit address

SI

SO

0000010 1 23 22 21 20

high-impedance

must then be driven high after the last bit if the

CS
address or the Page Erase will not execute. Once the
CS

is driven high the self-timed Page Erase cycle is
started. The WIP bit in the Status Register can be read
to determine when the Page Erase cycle is complete.

If a Page Erase function is given to an address that
has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.

210

 2003 Microchip Technology Inc. Preliminary DS21836A-page 13

25AA1024/25LC1024

2.10 SECTOR ERASE

The Sector Erase function will erase all bits (FFh)
inside the given sector. A Write Enable (WREN) instruc­tion must be given prior to attempting a Sector Erase.
This is done by setting CS
the proper instruction into the 25XX1024. After all
eight bits of the instruction are transmitted, the CS
must be brought high to set the write enable latch.

The Sector Erase function is entered by driving CS
low, followed by the instruction code Figure 2-9, and
three address bytes. Any address inside the sector to
be erased is a valid address.

low and then clocking out

FIGURE 2-9: SECTOR ERASE SEQUENCE

CS

0 234567891011 2930311

SCK

instruction 24-bit address

SI

SO

0011011 0 23 22 21 20

high-impedance

must then be driven high after the last bit if the

CS
address or the Sector Erase will not execute. Once the
CS

is driven high the self-timed Sector Erase cycle is
started. The WIP bit in the Status Register can be read
to determine when the Sector Erase cycle is complete.

If a Sector Erase instruction is given to an address that
has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.

See Table 2-3 for Sector Addressing.

210

DS21836A-page 14 Preliminary  2003 Microchip Technology Inc.

2.11 CHIP ERASE

25AA1024/25LC1024

The Chip Erase function will erase all bits (FFh) in the
array. A Write Enable (WREN) instruction must be given
prior to executing a Chip Erase. This is done by setting

low and then clocking out the proper instruction

CS
into the 25XX1024. After all eight bits of the instruction
are transmitted, the CS
the write enable latch.

The Chip Erase function is entered by driving the CS
low, followed by the instruction code (Figure 2-10)
onto the SI line.

must be brought high to set

FIGURE 2-10: CHIP ERASE SEQUENCE

CS

0 2345671

SCK

SI

111000 11

The CS
the instruction code has been given or the Chip Erase
function will not be executed. Once the CS
driven high the self-timed Chip Erase function begins.
While the device is executing the Chip Erase function
the WIP bit in the Status Register can be read to
determine when the Chip Erase function is complete.

The Chip Erase function is ignored if either of the
Block Protect bits (BP0, BP1) are not 0, meaning ¼,
½, or all of the array is protected.

pin must be driven high after the eighth bit of

pin is

SO

high-impedance

 2003 Microchip Technology Inc. Preliminary DS21836A-page 15

25AA1024/25LC1024

2.12 DEEP POWER-DOWN MODE

Deep Power-down Mode of the 25XX1024 is its lowest
power consumption state. The device will not respond
to any of the read or write commands while in Deep
Power-down mode, and therefore it can be used as an
additional software write protection feature.

The Deep Power-down mode is entered by driving CS
low, followed by the instruction code (Figure 2-11) onto
the SI line, followed by driving CS

If the CS
the instruction code has been given, the device will not
execute Deep power-down. Once the CS
high there is a delay (T
its lowest consumption.

pin is not driven high after the eighth bit of

) before the current settles to

DP

high.

line is driven

FIGURE 2-11: DEEP POWER-DOWN SEQUENCE

CS

0 2345671

SCK

SI

100111 10

All instructions given during Deep Power-down mode
are ignored except the Read Electronic Signature
Command (RDID). The RDID command will release
the device from Deep power-down and outputs the
electronic signature on the SO pin, and then returns
the device to Standby mode after delay (T

Deep Power-down mode automatically releases at
device power-down. Once power is restored to the
device it will power-up in the Standby mode.

REL

)

SO

high-impedance

DS21836A-page 16 Preliminary  2003 Microchip Technology Inc.

25AA1024/25LC1024

2.13 RELEASE FROM DEEP POWER­DOWN AND READ ELECTRONIC
SIGNATURE

Once the device has entered Deep Power-down mode
all instructions are ignored except the Release from
Deep Power-down and Read Electronic Signature
command. This command can also be used when the
device is not in Deep Power-down to read the
electronic signature out on the SO pin unless another
command is being executed such as Erase, Program
or Write Status Register.

Release from Deep Power-down mode and Read
Electronic Signature is entered by driving CS
followed by the RDID instruction code (Figure 2-12)
and then a dummy address of 24 bits (A23-A0). After
the last bit of the dummy address is clock in, the 8-bit
Electronic signature is clocked out on the SO pin.

After the signature has been read out at least once,
the sequence can be terminated by driving CS
The device will then return to Standby mode and will
wait to be selected so it can be given new instructions.
If additional clock cycles are sent after the electronic
signature has been read once, it will continue to output
the signature on the SO line until the sequence is
terminated.

low,

high.

FIGURE 2-12: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

0 2 3 4 5 6 7 8 9 1011 29303132333435363738391

SCK

instruction 24-bit address

SI

0110101 1 23 22 21 20

210

high-impedance

SO

Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure
the device will be taken out of Deep Power-down mode. However, there is a delay T
returns to Standby mode (I

), as shown in Figure 2-13.

CCS

Electronic Signature Out

76543210

0 1010010

Manufacturers ID 0x29

that occurs before the device

REL

FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

T

REL

SCK

SI

SO

0 2345671

instruction

01101011

high-impedance

 2003 Microchip Technology Inc. Preliminary DS21836A-page 17

25AA1024/25LC1024

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

Name Pin Number Function

CS

SO 2 Serial Data Output

WP

V

SS 4 Ground

SI 5 Serial Data Input

SCK 6 Serial Clock Input

HOLD

CC 8 Supply Voltage

V

3.1 Chip Select (CS)

A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of

input signal. If CS is brought high during a

the CS
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS
sequence initiates an internal write cycle. After power­up, a low level on CS
being initiated.

3.2 Serial Output (SO)

The SO pin is used to transfer data out of the
25XX1024. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.

1 Chip Select Input

3 Write-Protect Pin

7 Hold Input

after a valid write

is required prior to any sequence

The WP
the Status Register is low. This allows the user to install
the 25XX1024 in a system with WP
still be able to write to the Status Register. The WP
functions will be enabled when the WPEN bit is set
high.

pin function is blocked when the WPEN bit in

pin grounded and

pin

3.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.

3.5 Serial Clock (SCK)

The SCK is used to synchronize the communication
between a master and the 25XX1024. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.

3.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the
25XX1024 while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD
low to pause further serial communication without
resetting the serial sequence. The HOLD
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to­low transition. The 25XX1024 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low, otherwise serial
communication will not resume. Pulling the HOLD
low at any time will tri-state the SO line.

pin may be pulled

pin must be

must be brought

line

3.3 Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the
Status Register to prohibit writes to the nonvolatile bits
in the Status Register. When WP
high, writing to the nonvolatile bits in the Status
Register is disabled. All other operations function
normally. When WP
writes to the nonvolatile bits in the Status Register,
operate normally. If the WPEN bit is set, WP
a Status Register write sequence will disable writing to
the Status Register. If an internal write cycle has
already begun, WP
write.

DS21836A-page 18 Preliminary  2003 Microchip Technology Inc.

is high, all functions, including

going low will have no effect on the

is low and WPEN is

low during

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

25AA1024/25LC1024

8-Lead DFN

XXXXXXX

T/XXXXX

YYWW

NNN

8-Lead PDIP

XXXXXXXX
T/XXXNNN

YYWW

8-Lead SOIC

XXXXXXXX
T/XXYYWW

NNN

Example

5LC1024

I/MF

0328

1L7

Example:

25AA1024
I/P 1L7

Example:

25LC1024
I/SN 0328

:

0328

1L7

Legend: XX...X Part number

T Temperature (I,E)
Blank Commercial
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

Note: Custom marking available.

 2003 Microchip Technology Inc. Preliminary DS21836A-page 19

25AA1024/25LC1024

8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S)

A1

n

12

TOP VIEW

α

E1

E

B

R

D1 D

EXPOSED

METAL

PADS

BOTTOM VIEW

A2

A3

A

p

L

D2

PIN 1

ID

E2

Units

Dimension Limits

Number of Pins

Pitch

Overall Height

Molded Package Thickness

Standoff

Base Thickness

Overall Length

Molded Package Length

Exposed Pad Length

Molded Package Width

Exposed Pad Width D2 .085 .091 .097 2.16 2.31 2.46

Lead Width

Lead Length

Tie Bar Width

Mold Draft Angle Top

*Controlling Parameter

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: pending

Drawing No. C04-113

n

p

A

A2

A1

A3

E

E1

E2

DOverall Width

D1

B

L

R

α

MIN

INCHES

NOM

.050 BSC

.033

.026

.000

.152 .158 .163 3.85 4.00 4.15

.014

.020

.0004

.008 REF.

.194 BSC

.184 BSC

.236 BSC

.226 BSC

.016

.024

.014

MAX MIN

8

.039

.031

.002

.019

.030

12

MILLIMETERS*

1.27 BSC

0.00

0.20 REF.

4.92 BSC

4.67 BSC

5.99 BSC

5.74 BSC

0.35

0.50

0.85

0.65

0.01

0.40

0.60

.356

MAXNOM

8

1.00

0.80

0.05

0.47

0.75

12

DS21836A-page 20 Preliminary  2003 Microchip Technology Inc.

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

25AA1024/25LC1024

n

E

β

eB

Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing §
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter

§ Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

Dimension Limits MIN NOM MAX MIN NOM MAX

1

α

A

c

Units INCHES* MILLIMETERS

n
p

c

eB

α

β

.008 .012 .015 0.20 0.29 0.38

.310 .370 .430 7.87 9.40 10.92

A1

B1

B

88

.100 2.54

5 10 15 5 10 15
5 10 15 5 10 15

A2

L

p

 2003 Microchip Technology Inc. Preliminary DS21836A-page 21

25AA1024/25LC1024

8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)

E

E1

p

D

2

n

B

c

β

Number of Pins
Pitch

Molded Package Thickness

Foot Angle
Lead Thickness

Mold Draft Angle Top
Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.
Drawing No. C04-056

n
p

A2

φ

c

α

β

1

A

φ

L

.070 .075
.069 .074

048048

A1

1.78

1.75

MILLIMETERSINCHES*Units

1.27.050

1.97

1.88

α

A2

MAXNOMMINMAXNOMMINDimension Limits

88

2.03.080AOverall Height

1.98.078

0.250.130.05.010.005.002A1Standoff §

8.267.957.62.325.313.300EOverall Width

5.385.285.11.212.208.201E1Molded Package Width

5.335.215.13.210.205.202DOverall Length

0.760.640.51.030.025.020LFoot Length

0.250.230.20.010.009.008

0.510.430.36.020.017.014BLead Width
1512015120
1512015120

DS21836A-page 22 Preliminary  2003 Microchip Technology Inc.

25AA1024/25LC1024

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip
World Wide Web site.

The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape
Internet Explorer. Files are also available for FTP
download from our FTP site.

Connecting to the Microchip Internet
Web Site

The Microchip web site is available at the following
URL:

www.microchip.com

The file transfer site is available by using an FTP
service to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A
variety of Microchip specific business information is
also available, including listings of Microchip sales
offices, distributors and factory representatives. Other
data available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked
Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to
Microchip Products

• Conferences for products, Development Systems,
technical information and more

• Listing of seminars and events

®

or Microsoft

SYSTEMS INFORMATION AND UPGRADE HOT LINE

The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.

®

Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

042003

 2003 Microchip Technology Inc. Preliminary DS21836A-page 23

25AA1024/25LC1024

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod­uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at [phone].

Please list the following information, and use this outline to provide us with your comments about this document.

To :

RE: Reader Response

From:

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

Technical Publications Manager

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Total Pages Sent ________

FAX: (______) _________ - _________

DS21836A25AA1024/25LC1024

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21836A-page 24 Preliminary  2003 Microchip Technology Inc.

25AA1024/25LC1024

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX X

–

Device

Device 25AA1024

Tape & Reel Blank =

Temperature Range I =

Package MF =

25LC1024

T=

E=

P=
SM =

1 Mbit, 1.8V, 256-Byte Page SPI Serial Flash
1 Mbit, 2.5V, 256-Byte Page SPI Serial Flash

Standard packaging (tube)
Tape & Reel

-40°C to+85°C

-40°C to+125°C

Micro Lead Frame (6 x 5 mm body), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (207 mil body), 8-lead

X

Temp Range

Lead PackageTape & Reel
Finish

Examples:

a) 25AA1024-I/SMG = 1 Mbit, 1.8V Serial Flash,

Industrial temp., SOIC package, Pb-free

b) 25AA1024T-I/SM = 1 Mbit, 1.8V Serial Flash,

Industrial temp., Tape & Reel, SOIC package

c) 25AA1024T-I/MF = 1 Mbit, 1.8V Serial Flash,

Industrial temp., Tape & Reel, DFN package

d) 25LC1024-I/SMG = 1 Mbit, 2.5V Serial Flash,

Industrial temp., SOIC package, Pb-free

e) 25LC1024-I/P = 1 Mbit, 2.5V Serial Flash,

Industrial temp., P-DIP package

f) 25LC1024T-E/MF = 1 Mbit, 2.5V Serial Flash,

Extended temp., Tape & Reel, DFN package

Lead Finish Blank =

G=

Standard 63% / 37% Sn/Pb
Matte Tin (Pure Sn)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: [phone]

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2003 Microchip Technology Inc. Preliminary DS21836A-page 25

25AA1024/25LC1024

NOTES:

DS21836A-page 26 Preliminary  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com­ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con­veyed, implicitly or otherwise, under any intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

 2003 Microchip Technology Inc. Preliminary DS21836A-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]
Technical Support: 480-792-7627
Web Address: http://www.microchip.com

Atlanta

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Fax: [phone]

Detroit

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Fax: [phone]

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2767 S. Albright Road
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Fax: [phone]

Los Angeles

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Tor ont o

6285 Northam Drive, Suite 108
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ASIA/PACIFIC

Australia

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Ming Xing Financial Tower
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Unit 28F, World Trade Plaza
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China - Hong Kong SAR

Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
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China - Shanghai

Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
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China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
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China - Shunde

Room 401, Hongjian Building
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Tel: [phone] Fax: [phone]

China - Qingdao

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India

Divyasree Chambers
1 Floor, Wing A (A3/A4)
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Japan

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Korea

168-1, Youngbo Bldg. 3 Floor
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Tel: [phone] Fax: [phone] or
82-2-558-5934

Singapore

200 Middle Road
#07-02 Prime Centre
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Tai wan

Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
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Fax: [phone]

Tai wan

Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: [phone] Fax: [phone]

EUROPE

Austria

Durisolstrasse 2
A-4600 Wels
Austria
Tel: [phone]
Fax: [phone]

Denmark

Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: [phone] Fax: [phone]

France

Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: [phone]
Fax: [phone]

Germany

Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: [phone]
Fax: [phone]

Italy

Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: [phone]
Fax: [phone]

Netherlands

P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: [phone]
Fax: [phone]

United Kingdom

505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: [phone]
Fax: [phone]

07/28/03

DS21836A-page 28 Preliminary  2003 Microchip Technology Inc.