The Microchip Technology Inc. 25AA080A/B,
25LC080A/B (25XX080A/B
Electrically Erasable PROMs. The memory is accessed
via a simple Serial Peripheral Interface™ (SPI™)
compatible serial bus. The bus signals required are a
clock input (SCK) plus separate data in (SI) and data
out (SO) lines. Access to the device is controlled
through a Chip Select (CS
Communication to the device can be paused via the
hold pin (HOLD
). While the device is paused, transitions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.
The 25XX080A/B is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead MSOP, and 8-lead TSSOP.
Pb-free (Pure Matte Sn) finish is also available.
*
) are 8 Kbit Serial
) input.
Package Types (not to scale)
CS
SO
WP
V
SS
PDIP/SOIC
(P, SN)
1
8
2
7
3
6
4
5
V
CC
HOLD
SCK
SI
TSSOP/MSOP
(ST, MS)
1
CS
2
SO
3
WP
4
V
SS
SPI is a registered trademark of Motorola Semiconductor.
*25XX080A/B is used in this document as a generic part
number for the 25AA080A/B, 25LC080A/B.
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-65°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
Note:This parameter is periodically sampled and not 100% tested.
AMB = -40°C to +85°C VCC = 1.8V to 5.5V
AMB = -40°C to +125°C VCC = 2.5V to 5.5V
±1µACS = VCC, VOUT = VSSTO VCC
AMB = 25°C, CLK = 1.0 MHz,
CC = 5.0V (Note)
V
6
mAmAVCC = 5.5V; FCLK = 10.0 MHz;
SO = Open
2.5
CC = 2.5V; FCLK = 5.0 MHz;
V
SO = Open
3mAVCC = 5.5V
5
1
µAµACS
V
CS
V
= VCC = 5.5V, Inputs tied to VCC or
SS, TAMB = -40°C TO +125°C
= VCC = 2.5V, Inputs tied to VCC or
SS, TAMB = -40°C TO +85°C
DS21808B-page 2 2003 Microchip Technology Inc.
TABLE 1-2:AC CHARACTERISTICS
25XX080A/B
AC CHARACTERISTICS
Param.
No.
1F
Sym.CharacteristicMin.Max.UnitsTest Conditions
CLKClock Frequency—
Industrial (I):T
Automotive (E): T
—
—
2T
CSSCS Setup Time50
100
150
3T
CSHCS Hold Time100
200
250
4T
CSDCS Disable Time50—ns—
5TsuData Setup Time10
20
30
6T
HDData Hold Time20
40
50
7T
8T
9T
RCLK Rise Time—500ns(Note 1)
FCLK Fall Time—500ns(Note 1)
HIClock High Time50
100
150
10T
LOClock Low Time50
100
150
11T
12T
13T
CLDClock Delay Time50—ns—
CLEClock Enable Time50—ns—
VOutput Valid from Clock
Low
—
—
—
14T
15T
HOOutput Hold Time0—ns(Note 1)
DISOutput Disable Time—
—
—
16T
HSHOLD Setup Time20
40
80
AMB = -40°C to +85°CVCC = 1.8V to 5.5V
AMB = -40°C to +125°C VCC = 2.5V to 5.5V
10
5
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
100
160
40
80
160
—
—
—
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
WC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
3: T
is complete.
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5V ≤ VCC≤ 5.5V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
4.5V ≤ VCC≤ 5.5V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
4.5V ≤ VCC≤ 5.5V
2.5V ≤ V
1.8V ≤ V
4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
CC ≤ 5.5V
CC < 4.5V
CC < 2.5V
CC ≤ 5.5V
CC < 4.5V
CC < 2.5V
4.5V ≤ VCC≤ 5.5V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
4.5V ≤ VCC≤ 5.5V
2.5V ≤ V
1.8V ≤ V
4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
CC ≤ 5.5V
CC < 4.5V
CC < 2.5V
CC ≤ 5.5V (Note 1)
CC < 4.5V (Note 1)
CC < 2.5V (Note 1)
4.5V ≤ VCC≤ 5.5V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V
CC < 2.5V
2003 Microchip Technology Inc.DS21808B-page 3
25XX080A/B
TABLE 1-2:AC CHARACTERISTICS (CONTINUED)
Industrial (I):T
Automotive (E): T
Param.
No.
AC CHARACTERISTICS
Sym.CharacteristicMin.Max.UnitsTest Conditions
17THHHOLD Hold Time20
40
80
18T
HZHOLD Low to Output
High-Z
30
60
160
19T
HVHOLD High to Output
Val id
30
60
160
20T
WCInternal Write Cycle Time—5ms(Note 3)
AMB = -40°C to +85°CVCC = 1.8V to 5.5V
AMB = -40°C to +125°C VCC = 2.5V to 5.5V
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
21—Endurance1,000,000—E/W
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
3: T
WC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
CC ≤ 5.5V
CC < 4.5V
CC < 2.5V
4.5V ≤ VCC≤ 5.5V (Note 1)
2.5V ≤ V
1.8V ≤ V
4.5V ≤ V
2.5V ≤ V
1.8V ≤ V
CC < 4.5V (Note 1)
CC < 2.5V (Note 1)
CC ≤ 5.5V
CC < 4.5V
CC < 2.5V
(Note 2)
TABLE 1-3:AC TEST CONDITIONS
AC Waveform:
LO = 0.2V—
V
HI = VCC - 0.2V (Note 1)
V
HI = 4.0V (Note 2)
V
Timing Measurement Reference Level
Input0.5 V
Output0.5 VCC
Note 1: For VCC≤ 4.0V
2: For V
CC > 4.0V
CC
DS21808B-page 4 2003 Microchip Technology Inc.
FIGURE 1-1:HOLD TIMING
CS
16
SCK
SO
n+2n+1nn-1
17
18
high-impedance
16
25XX080A/B
17
19
n
SI
HOLD
n+2n+1n
FIGURE 1-2:SERIAL INPUT TIMING
CS
2
Mode 1,1
Mode 0,0
SCK
65
SI
SO
MSB in
high-impedance
don’t care
7
8
LSB in
5
n
3
n-1
4
12
11
FIGURE 1-3:SERIAL OUTPUT TIMING
CS
9
10
SCK
13
SO
SI
2003 Microchip Technology Inc.DS21808B-page 5
MSB out
don’t care
14
3
Mode 1,1
Mode 0,0
15
ISB out
25XX080A/B
2.0FUNCTIONAL DESCRIPTION
2.1Principles of Operation
The 25XX080A/B are 1024 byte Serial EEPROMs
designed to interface directly with the Serial
Peripheral Interface (SPI) Port of many of today’s
popular microcontroller families, including
Microchip’s PICmicro
interface with microcontrollers that do not have a
built-in Synchronous Serial Port by using discrete
I/O lines programmed properly with the software.
The 25XX080A/B contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
be low and the HOLD
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS
peripheral devices on the SPI bus, the user can assert
the HOLD
mode. After releasing the HOLD
resume from the point when the HOLD
goes low. If the clock line is shared with other
input and place the 25XX080A/B in ‘HOLD’
2.2Read Sequence
The device is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25XX080A/B followed
by the 16-bit address, with the six MSBs of the address
being don’t care bits. After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached (03FFh), the address counter rolls over to
address 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
pin (Figure 2-1).
the CS
®
microcontrollers. It may also
pin must
pin must be high for the entire
pin, operation will
was asserted.
2.3Write Sequence
Prior to any attempt to write data to the 25XX080A/B,
the write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS
and then clocking out the proper instruction into the
25XX080A/B. After all eight bits of the instruction are
transmitted, the CS
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS
instruction, followed by the 16-bit address, with the six
MSBs of the address being don’t care bits, and then the
data to be written. Up to 16 bytes (25XX080A) or 32
bytes (25XX080B) of data can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page.
Note:Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size - 1. If a Page
Write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status Register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read Status Register
Write Status Register
FIGURE 2-1:READ SEQUENCE
CS
02 3 4 5 6 7 8 910 1121222324252627282930311
SCK
instruction16-bit address
SI
SO
2003 Microchip Technology Inc.DS21808B-page 7
0100000115 14 13 12210
high-impedance
data out
76543210
25XX080A/B
FIGURE 2-2:BYTE WRITE SEQUENCE
CS
8
9 10112122232425262728293031
SCK
SI
SO
02345671
instruction16-bit addressdata byte
0000000115 14 13 12
high-impedance
FIGURE 2-3:PAGE WRITE SEQUENCE
CS
8
SCK
SI
CS
02345671
instruction16-bit addressdata byte 1
0000000115 14 13 12
Twc
21076543210
9 10112122232425262728293031
21076543210
SCK
SI
3234 35 36 37 38 3933
data byte 2
76543210
41 42 4346 47
40
76543210
44 45
data byte 3
data byte n (16/32 max)
76543210
DS21808B-page 8 2003 Microchip Technology Inc.
25XX080A/B
2.4Write Enable (WREN) and Write
Disable (WRDI)
The 25XX080A/B contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 2-4:WRITE ENABLE SEQUENCE (WREN)
CS
02345671
SCK
SI
SO
01000001
high-impedance
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
FIGURE 2-5:WRITE DISABLE SEQUENCE (WRDI)
CS
02345671
SCK
SI
SO
01000001
high-impedance
0
2003 Microchip Technology Inc.DS21808B-page 9
25XX080A/B
2.5Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the Status Register. The Status Register may
be read at any time, even during a write cycle. The
Status Register is formatted as follows:
TABLE 2-2:STATUS REGISTER
7654 321 0
W/R–––W/RW/RRR
WPENXXXBP1BP0WELWIP
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25XX080A/B is busy with a write operation. When set
1’, a write is in progress, when set to a ‘0’, no write
to a ‘
is in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read only. When set to
a ‘
1’, the latch allows writes to the array or the Status
Register, when set to a ‘
the array or the Status Register. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the Status
Register. These commands are shown in Figure 2-4
and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is in Figure 2-7. These bits are nonvolatile and are
shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
FIGURE 2-6:READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
8
02345671
9101112131415
0’, the latch prohibits writes to
SCK
SO
SI
instruction
high-impedance
11000000
data from Status Register
76542 10
3
DS21808B-page 10 2003 Microchip Technology Inc.
25XX080A/B
2.6Write Status Register Instruction
See Figure 2-7 for the WRSR timing sequence.
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the Status
Register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the Status Register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is also a
nonvolatile bit that is available as an enable bit for the WP
pin. The Write-Protect (WP) pin and the Write-Protect
Enable (WPEN) bit in the Status Register control the
programmable hardware write-protect feature. Hardware
write protection is enabled when WP
WPEN bit is high. Hardware write protection is disabled
when either the WP
When the chip is hardware write-protected, only writes to
nonvolatile bits in the Status Register are disabled. See
Table 2-4 for a matrix of functionality on the WPEN bit.
pin is high or the WPEN bit is low.
pin is low and the
FIGURE 2-7:WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
TABLE 2-3:ARRAY PROTECTION
BP1BP0
00
01
10
11
Array Addresses
Write-Protected
none
upper 1/4
(0300h - 03FFh)
upper 1/2
(0200h - 03FFh)
all
(0000h - 03FFh)
CS
SCK
SO
SI
02345671
8
9101112131415
instructiondata to Status Register
210
01000000
high-impedance
7654
3
2003 Microchip Technology Inc.DS21808B-page 11
25XX080A/B
2.7Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or Status Register
write, the write enable latch is reset
must be set high after the proper number of
•CS
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
2.8Power-On State
The 25XX080A/B powers on in the following state:
• The device is in low-power Standby mode
(CS
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS
enter active state
TABLE 2-4:WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
0xx
10x
1
1
WPEN
(SR bit 7)
1
1
WP
(pin 3)
0 (low)
1 (high)
Protected BlocksUnprotected BlocksStatus Register
ProtectedProtectedProtected
ProtectedWritableWritable
ProtectedWritableProtected
ProtectedWritableWritable
x = don’t care
= 1)
is required to
DS21808B-page 12 2003 Microchip Technology Inc.
25XX080A/B
3.0PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:PIN FUNCTION TABLE
NamePin NumberFunction
CS
SO2Serial Data Output
WP
SS4Ground
V
SI5Serial Data Input
SCK6Serial Clock Input
HOLD
CC8Supply Voltage
V
3.1Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
input signal. If CS is brought high during a
the CS
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS
sequence initiates an internal write cycle. After powerup, a low level on CS
being initiated.
1Chip Select Input
3Write-Protect Pin
7Hold Input
after a valid write
is required prior to any sequence
3.4Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.5Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX080A/B. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.6Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX080A/B while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD
low to pause further serial communication without
resetting the serial sequence. The HOLD
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX080A/B must remain selected
during this sequence. The SI, SCK and SO pins are in
a high impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
pin may be pulled
pin must be
must be brought
3.2Serial Output (SO)
The SO pin is used to transfer data out of the
25XX080A/B. During a read cycle, data is shifted out
on this pin after the falling edge of the serial clock.
3.3Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status Register to prohibit writes to the nonvolatile bits
in the Status Register. When WP
high, writing to the nonvolatile bits in the Status Register is disabled. All other operations function normally.
When WP
nonvolatile bits in the Status Register operate normally.
If the WPEN bit is set, WP
write sequence will disable writing to the Status
Register. If an internal write cycle has already begun,
WP
The WP
the Status Register is low. This allows the user to install
the 25XX080A/B in a system with WP
and still be able to write to the Status Register. The WP
pin functions will be enabled when the WPEN bit is set
high.
is high, all functions, including writes to the
going low will have no effect on the write.
pin function is blocked when the WPEN bit in
is low and WPEN is
low during a Status Register
pin grounded
2003 Microchip Technology Inc.DS21808B-page 13
25XX080A/B
4.0PACKAGING INFORMATION
4.1Package Marking Information
8-Lead MSOP (150 mil)
XXXXXXT
YWWNNN
8-Lead PDIP
XXXXXXXX
T/XXXNNN
YYWW
8-Lead SOIC
XXXXXXXX
T/XXYYWW
NNN
Example:
5L8AI
3281L7
Example:
25LC080A
I/P 1L7
0328
Example:
25LC080A
I/SN 0328
1L7
MSOP
D
evice
25AA
080A
2
5AA080B
2
5LC080A
25LC080
1st Line Ma
std
mark
5A8A
5A8B
5L8A
5L8B
B
rking Codes
Pb-fr
ma
G5A8A
G5A8B
G5L8A
G5L8B
ee
rk
8-Lead TSSOP
XXXX
TYWW
NNN
Legend: XX...X Part number
TTemperature (I, E)
Blank Commercial
YYYear code (last 2 digits of calendar year) except TSSOP
and MSOP which use only the last 1 digit
WWWeek code (week of January 1 is week ‘01’)
NNNAlphanumeric traceability code
Note:Custom marking available.
Example:
5L8A
I328
1L7
TSSOP 1st Line Marking Codes
Device
25AA080A
25AA080B
25LC080A
25LC080B
std mark
5A8A
5A8B
5L8A
5L8B
Pb-free
mark
NA8A
NA8B
NL8A
NL8B
DS21808B-page 14 2003 Microchip Technology Inc.
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
A2
A1
E1
MIN
n
p
A
E
D
L
FFootprint (Reference)
φ
c
B
α
β
.026 BSC
.030
.000
.193 TYP.
.118 BSC
.118 BSC
.016.024
.037 REF
0°-8°
.003
.009
5°
5°-
L
INCHES
NOM
.033
.006
.012
φ
A1
MAX
8
--
-
-
.043
.037
.006
.031
.009
.016
15°
15°
MIN
0.75
0.00
0.40
0.08
0.22
MILLIMETERS*
NOM
0.65 BSC
--
0.85
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
0°
MAX
8
-
-
-
-
A2
1.10
0.95
0.15
0.80
8°
0.23
0.40
15°5°15°5°-
2003 Microchip Technology Inc.DS21808B-page 15
25XX080A/B
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
E
β
eB
Number of Pins
Pitch
Top to Seating PlaneA.140.155.1703.563.944.32
Molded Package ThicknessA2.115.130.1452.923.303.68
Base to Seating PlaneA1.0150.38
Shoulder to Shoulder WidthE.300.313.3257.627.948.26
Molded Package WidthE1.240.250.2606.106.356.60
Overall LengthD.360.373.3859.149.469.78
Tip to Seating PlaneL.125.130.1353.183.303.43
Lead Thickness
Upper Lead WidthB1.045.058.0701.141.461.78
Lower Lead WidthB.014.018.0220.360.460.56
Overall Row Spacing§
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
Dimension LimitsMINNOMMAXMINNOMMAX
1
α
A
c
UnitsINCHES*MILLIMETERS
n
p
c
eB
α
β
.008.012.0150.200.290.38
.310.370.4307.879.4010.92
A1
B1
B
88
.1002.54
5101551015
5101551015
A2
L
p
DS21808B-page 16 2003 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
25XX080A/B
B
Number of Pins
Pitch
Standoff §
Molded Package Width
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
n
B
1
A
c
A1
φ
β
A2
E1
n
p
φ
c
α
β
048048
Number of Pins
Pitch
Molded Package Thickness
Molded Package Width
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web Site
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A
variety of Microchip specific business information is
also available, including listings of Microchip sales
offices, distributors and factory representatives. Other
data available for consideration is:
• Latest Microchip Press Releases
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• Conferences for products, Development Systems,
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®
or Microsoft
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
®
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
042003
2003 Microchip Technology Inc.DS21808B-page 19
25AA080A/B, 25LC080A/B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To :
RE:Reader Response
From:
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
Technical Publications Manager
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Total Pages Sent ________
FAX: (______) _________ - _________
DS21808B25AA080A/B, 25LC080A/B
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21808B-page 20 2003 Microchip Technology Inc.
25XX080A/B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.X/XXX
–
Device
Device25AA080A
Tape & ReelBlank =
Temperature Range I=
PackageMS=
25AA080B
25LC080A
25LC080B
T=
E=
P=
SN=
ST=
8 Kbit, 1.8V, 16 Byte Page SPI Serial EEPROM
8 Kbit, 1.8V, 32 Byte Page SPI Serial EEPROM
8 Kbit, 2.5V, 16 Byte Page SPI Serial EEPROM
8 Kbit, 2.5V, 32 Byte Page SPI Serial EEPROM
Standard packaging
Tape and Reel
-40°C to+85°C
-40°C to+125°C
Plastic MSOP (Micro Small Outline), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
TSSOP, 8-lead
X
Temp Range
Examples:
Lead FinishPackageTape & Reel
a)25AA080A-I/MS = 8 Kbit, 16-byte page, 1.8V
Serial EEPROM, Industrial temp., MSOP
package
b)25AA080B-I/STG = 8 Kbit, 32-byte page, 1.8V
Serial EEPROM, Industrial temp., TSSOP
package, Pb-free
c)25AA080AT-I/SN = 8 Kbit, 16-byte page, 1.8V
Serial EEPROM, Industrial temp., Tape & Reel,
SOIC package
d)25LC080A-I/MSG = 8 Kbit, 16-byte page, 2.5V
Serial EEPROM, Industrial temp., MSOP
package, Pb-free
e)25LC080BT-I/SN = 8 Kbit, 32-byte page, 2.5V
Serial EEPROM, Industrial temp., Tape & Reel,
SOIC package
f)25LC080BT-I/ST = 8 Kbit, 32-byte page, 2.5V
Serial EEPROM, Industrial temp., Tape & Reel,
TSSOP package
Lead FinishBlank =
G=
Standard 63% / 37% Sn/Pb
Matte Tin (Pure Sn)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.Your local Microchip sales office
2.The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3.The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc.DS21808B-page 21
25XX080A/B
NOTES:
DS21808B-page 22 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
2003 Microchip Technology Inc.DS21808B-page 23
WORLDWIDE SALES AND SERVICE
AMERICAS
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