MICROCHIP 25AA040, 25LC040, 25C040 Technical data

25AA040/25LC040/25C040

4K SPI™ Bus Serial EEPROM

Device Selection Table

Part

Number

25AA040 1.8-5.5V 1 MHz I
25LC040 2.5-5.5V 2 MHz I

25C040 4.5-5.5V 3 MHz I,E

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

Features

• Low-power CMOS technology

- Write current: 3 mA typical

- Read current: 500 µA typical

- Standby current: 500 nA typical

• 512 x 8-bit organization

• 16 byte page

• Write cycle time: 5 ms max.

• Self-timed ERASE and WRITE cycles

• Block write protection

- Protect none, 1/4, 1/2 or all of array

• Built-in write protect ion

- Power on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential read

• High reliability

- Endurance: 1M cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• 8-pin PDIP, SOIC, and TSSOP packages

• Temperature ranges supported:

- Industrial (I): -40°Cto +85°C

- Automotive (E) (25C040): -40°C to +125°C

Description

The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040
Erasable PROM. The m emory is acce ssed via a simple
Serial Peripheral Interface™ (SPI™) compatible serial
bus. The bus signals required are a clock input (SCK)
plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a Chip
Select (CS

*25XX040 is used in this document as a generic part number
for the 25AA040/25LC040/25C040 devices. SPI is a
trademark of Motorola Corporation.

) input.

*

) is a 4 Kbit serial Electrically

Communication to the device can be paused via the
hold pin (HOLD

). While the device is paused, transi­tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write-protect pin (WP).

Package Types

PDIP

SOIC

TSSOP

CS
SO

WP

VSS

CS

SO

WP

VSS

HOLD

VCC

CS
SO

1
2

3
4

1
2

3
4

1
2

3
4

25XX040

25XX040

25XX040

8

VCC
HOLD

7

SCK

6

SI

5

8

VCC
HOLD

7

SCK

6

SI

5

8

SCK

7

SI

6

SS

V

5

WP

Block Diagram

SO
CS

SCK

HOLD

WP

I/O Control

SI

Status

Register

Logic

Memory

VCC

VSS

Control

Logic

HV Generato r

EEPROM

Array

XDEC

Page

Latches

Y Decoder

Sense Amp.
R/W Control

 2003 Microchip Technology Inc. DS21204D-page 1

25AA040/25LC040/25C040

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ................................ ................................................... ...... ..... ............ -0.6V to VCC+1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-65°C to 125°C

ESD protection on all pins.........................................................................................................................................4KV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

D001 V
D002 VIH2 0.7 VCC VCC+1 V VCC< 2.7V (Note)
D003 V
D004 VIL2 -0.3 0.3 VCC VVCC < 2.7V (Note)

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input

voltage

IL1 Low-level input

voltage

D005 VOL Low-level output
D006 V

OL —0.2VIOL = 1.0 mA, VCC < 2.5V

voltage

D007 VOH High-level output

Industrial (I): T
Automotive (E):T

2.0 VCC+1 V VCC ≥ 2.7V (Note)

-0.3 0.8 V VCC ≥ 2.7V (Note)

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH =-400 µA

voltage
D008 I
D009 ILO Output leakage

LI Input leakage current — ±1 µACS = VCC, VIN = VSS TO VCC

—±1µACS = VCC, VOUT = VSS TO VCC

current
D010 CINT Intern al Cap a ci t anc e

—7pFT
(all inputs and
outputs)

D011 I

CC Read Operating Current —

—

D012 ICC Write —

—

D013 ICCS Standby Current —

—

Note: This parameter is periodically sampled and not 100% tested.

A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)

A = 25°C, CLK = 1.0 MHz,

CC = 5.0V (Note)

V

1

500

5
3

5
1

mAµAVCC = 5.5V; FCLK = 3.0MHz; SO = Open

CC = 2.5V; FCLK = 2.0MHz; SO = Open

V

mAmAVCC = 5.5V

V

CC = 2.5V

µAµACS = VCC = 5.5V, Inputs tied to VCC or

SS

V
CS = VCC = 2.5V, Inputs tied to VCC or

SS

V

DS21204D-page 2  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

25AA040/25LC040/25C040

AC CHARACTERISTICS

Param

No.

Sym. Characteristic Min. Max. Units Test Conditions

Industrial (I): T
Automotive (E): T

1FCLK Clock Frequency —

2T

CSS CS Setup Time 100

250
500

3T

CSH CS Hold Time 150

250

475
4T
5T

6T

CSD CS Disable Time 500 — ns —
SU Data Setup Time 30

HD Data Hold Time 50

100

100
7T
8T
9T

R CLK Rise Time — 2 µs (Note 1)
F CLK Fall Time — 2 µs (Note 1)
HI Clock High Time 150

230

475
10 T

LO Clock Low Time 150

230

475
11 T
12 T
13 T

14 T
15 T

16 T

CLD Clock Delay Time 50 — ns —
CLE Clock Enable Time 50 — ns —

V Output Valid from Clock Low —

HO Output Hold Time 0 — ns (Note 1)
DIS Outp ut Disable Time —

HS HOLD Setup Time 100

100

200
17 T

HH HOLD Hold Time 100

100

200
18 T

HZ HOLD Low to Output High-Z 100

150

200
19 T

HV HOLD High to Output Valid 100

150

200
20 T

WC Internal Write Cycle Time — 5 ms —

—
—

50
50

—
—

—
—

A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)

3
2
1

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

150
230
475

200
250
500

—
—
—

—
—
—

—
—
—

—
—
—

MHz
MHz
MHz

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

21 — Endurance 1M — E/W

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please

consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V
V

CC = 1.8V to 2.5V

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V
V

CC = 1.8V to 2.5V

CC = 4.5V to 5.5V

V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V

VCC = 4.5V to 5.5V
V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V

CC = 4.5V to 5.5V (Note 1)

V

CC = 2.5V to 4.5V (Note 1)

V

CC = 1.8V to 2.5V (Note 1)

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V (Note 1)

CC = 2.5V to 4.5V (Note 1)

V
V

CC = 1.8V to 2.5V (Note 1)

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V
V

CC = 1.8V to 2.5V

(Note 2)

 2003 Microchip Technology Inc. DS21204D-page 3

25AA040/25LC040/25C040

FIGURE 1-1: HOLD TIMING

CS

17

18

high-impedance

SCK

SO

16

n+2 n+1 n n-1

16

17

19

n

SI

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

CS

SCK

SI

SO

2
Mode 1,1
Mode 0,0

65

MSB in

high-impedance

7

don’t care

8

LSB in

5

n

3

n-1

4

12

11

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

9

10

SCK

13

SO

SI

DS21204D-page 4  2003 Microchip Technology Inc.

MSB out

don’t care

14

3

Mode 1,1
Mode 0,0

15

ISB out

25AA040/25LC040/25C040

TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT AC

AC Waveform:

V

LO = 0.2V —

VHI = VCC - 0.2V (Note 1)

HI = 4.0V (Note 2)

V

Timing Measurement Reference Lev el

Input 0.5 VCC
Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V

CC > 4.0V

SO

VCC

2.25 KΩ

1.8 KΩ

100 pF

 2003 Microchip Technology Inc. DS21204D-page 5

25AA040/25LC040/25C040

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP SOIC TSSOP Description

CS

SO 2 2 4 Serial Data Output
WP
V

SS 4 4 6 Ground

SI 5 5 7 Serial Data Input

SCK 6 6 8 Serial Clock Input

HOLD

V

CC 8 8 2 Supply Voltage

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardle ss of
the CS
program cycle, the device will go in Standby mode as
soon as the programming cycle is complete. When the
device is dese lected, SO goes into the hi gh-impedance
state, allowing multiple parts to share the same SPI
bus. A lo w-to-high transiti on on CS
sequence initiates an internal write cycle. After power­up, a low level on CS is r equ ired p r ior to any sequence
being initiated.

1 1 3 Chip Select Input

3 3 5 Write-Protect Pin

7 7 1 Hold Input

input signal. If CS is brought high during a

after a valid write

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication
between a master and the 25XX040. Instructions,
addresses or data pres en t on th e SI pin are latched on
the rising edge of t he c lo ck input, while data on the SO
pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the
25XX040 while in the middle of a seri al sequ ence wit h­out having to retransmit the entire sequ ence aga in at a
later time. It must be held high any time this function is
not being used. Once the device is selected and a
serial sequence is underway, the HOLD
pulled low to pause further serial communication with­out resetting the serial sequence. The HOLD pin must
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to­low transition. Th e 25XX040 must remain se lected d ur­ing this sequence. The SI, SCK and SO pins are in a
high-impedance state during the time the part is
paused and transitions on these p ins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.

pin may be

must be brought

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.

2.3 Write-Protect (WP)

This pin is a hardware write-protect input pin. When

is low, all writes to the arr ay or Status regis ter are

WP
disabled, but any other operation functions normally.
When WP is high, all functions, including nonvolatile
writes operate normally. WP
reset the write enable latch and inhibit programming,
except when an internal write has already begun. If an
internal write cycle has already begun, WP
will have no effect on the write. See Table 3-2 for Write­Protect Functionality Matrix.

going low at any time will

going low

DS21204D-page 6  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

3.0 FUNCTIONAL DESCRIPTION

3.1 Principles of Operation

The 25XX040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro­controllers. It may also interface with microcontrollers
that do not hav e a built-in SPI port by using discrete
I/O lines programmed properly with the software.

The 25XX040 conta ins an 8-bit instr uction regi ster . The
part is access ed v ia the SI pin, with data being clocked
in on the rising edge of SCK. The CS
and the HOLD
The WP
memory array.

Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The Most
Significant address bit (A8) is located in the instruction
byte. All instructions, addresses, and data are
transferred MSB first, LSB last.

Data is sampled on the fir st rising edge of SCK after CS
goes low. If the clock line is shared with other periph­eral devices on the SPI bus, the user can assert the
HOLD input and pl ace the 25X X040 in ‘HO LD’ mode.
After releasing the HOLD
from the point when the HOLD

pin must be high for the entire operation.

pin must be held high to allow writing to the

pin, operation will resume

3.2 Read Sequence

The part is selected by pulling CS low. The 8-bit read
instruction with the A8 address bit is transmitted to the
25XX040 followed by the lower 8-bit address (A7
through A0). After the correct READ instruction and
address are sent, the data stored in the memory at the
selected address is shif ted out on the SO pin. The da ta
stored in the memory at the next address can be read
sequentially by continuing to provide cloc k p uls es . Th e
internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued
indefinitely. The read operation i s term inated by rai sing

pin (Figure 3-1).

the CS

TABLE 3-1: INSTRUCTION SET

pin must be low

was asserted.

3.3 Write Sequence

Prior to any attempt to write data to the 25XX040, the
write enable latch must be set by issuing the WREN
instruction (Figure3-4). This is done by setting CS
and then clocking out the proper instruction into the
25XX040. After all eight bits of the instruction are
transmitted, the CS
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write e nable latc h will not hav e been
properly set.

Once the write enable latch is set, the user may
proceed by setting the CS
instruction, followed by the address, and then the data
to be written. Keep in mind that the Most Significant
address bit (A8) is included in the instruction byte. Up
to 16 bytes of data can be sent to the 25XX040 before
a write cycle is nece ssary . Th e only restrictio n is that all
of the bytes must reside in the same page. A page
address begins wit h

1111

. If the internal address counter reaches XXXX

1111

and the clock conti nues, the counte r will roll back
to the first address of the page and overwrite any data
in the page that may have been written.

For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WIP, WEL, BP1 and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.

th

data byte has been clocked in. If CS is

must be brought high to set the

low, issuing a WRITE

XXXX 0000 and ends with XXXX

low

Instruction Name Instruction Format Description

READ

WRITE

WRDI
WREN
RDSR

WRSR

Note: A

 2003 Microchip Technology Inc. DS21204D-page 7

8 is the 9

0000 A8011
0000 A8010

0000 0100
0000 0110
0000 0101
0000 0001

th

address bit necessary to fully address 512 bytes.

Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read Status register
Write Status register