MICROCHIP 25AA040, 25LC040, 25C040 Technical data

25AA040/25LC040/25C040

4K SPI™ Bus Serial EEPROM

Device Selection Table

Part

Number

25AA040 1.8-5.5V 1 MHz I
25LC040 2.5-5.5V 2 MHz I

25C040 4.5-5.5V 3 MHz I,E

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

Features

• Low-power CMOS technology

- Write current: 3 mA typical

- Read current: 500 µA typical

- Standby current: 500 nA typical

• 512 x 8-bit organization

• 16 byte page

• Write cycle time: 5 ms max.

• Self-timed ERASE and WRITE cycles

• Block write protection

- Protect none, 1/4, 1/2 or all of array

• Built-in write protect ion

- Power on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential read

• High reliability

- Endurance: 1M cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• 8-pin PDIP, SOIC, and TSSOP packages

• Temperature ranges supported:

- Industrial (I): -40°Cto +85°C

- Automotive (E) (25C040): -40°C to +125°C

Description

The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25XX040
Erasable PROM. The m emory is acce ssed via a simple
Serial Peripheral Interface™ (SPI™) compatible serial
bus. The bus signals required are a clock input (SCK)
plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a Chip
Select (CS

*25XX040 is used in this document as a generic part number
for the 25AA040/25LC040/25C040 devices. SPI is a
trademark of Motorola Corporation.

) input.

*

) is a 4 Kbit serial Electrically

Communication to the device can be paused via the
hold pin (HOLD

). While the device is paused, transi­tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write-protect pin (WP).

Package Types

PDIP

SOIC

TSSOP

CS
SO

WP

VSS

CS

SO

WP

VSS

HOLD

VCC

CS
SO

1
2

3
4

1
2

3
4

1
2

3
4

25XX040

25XX040

25XX040

8

VCC
HOLD

7

SCK

6

SI

5

8

VCC
HOLD

7

SCK

6

SI

5

8

SCK

7

SI

6

SS

V

5

WP

Block Diagram

SO
CS

SCK

HOLD

WP

I/O Control

SI

Status

Register

Logic

Memory

VCC

VSS

Control

Logic

HV Generato r

EEPROM

Array

XDEC

Page

Latches

Y Decoder

Sense Amp.
R/W Control

 2003 Microchip Technology Inc. DS21204D-page 1

25AA040/25LC040/25C040

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ................................ ................................................... ...... ..... ............ -0.6V to VCC+1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-65°C to 125°C

ESD protection on all pins.........................................................................................................................................4KV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

D001 V
D002 VIH2 0.7 VCC VCC+1 V VCC< 2.7V (Note)
D003 V
D004 VIL2 -0.3 0.3 VCC VVCC < 2.7V (Note)

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input

voltage

IL1 Low-level input

voltage

D005 VOL Low-level output
D006 V

OL —0.2VIOL = 1.0 mA, VCC < 2.5V

voltage

D007 VOH High-level output

Industrial (I): T
Automotive (E):T

2.0 VCC+1 V VCC ≥ 2.7V (Note)

-0.3 0.8 V VCC ≥ 2.7V (Note)

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH =-400 µA

voltage
D008 I
D009 ILO Output leakage

LI Input leakage current — ±1 µACS = VCC, VIN = VSS TO VCC

—±1µACS = VCC, VOUT = VSS TO VCC

current
D010 CINT Intern al Cap a ci t anc e

—7pFT
(all inputs and
outputs)

D011 I

CC Read Operating Current —

—

D012 ICC Write —

—

D013 ICCS Standby Current —

—

Note: This parameter is periodically sampled and not 100% tested.

A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)

A = 25°C, CLK = 1.0 MHz,

CC = 5.0V (Note)

V

1

500

5
3

5
1

mAµAVCC = 5.5V; FCLK = 3.0MHz; SO = Open

CC = 2.5V; FCLK = 2.0MHz; SO = Open

V

mAmAVCC = 5.5V

V

CC = 2.5V

µAµACS = VCC = 5.5V, Inputs tied to VCC or

SS

V
CS = VCC = 2.5V, Inputs tied to VCC or

SS

V

DS21204D-page 2  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

25AA040/25LC040/25C040

AC CHARACTERISTICS

Param

No.

Sym. Characteristic Min. Max. Units Test Conditions

Industrial (I): T
Automotive (E): T

1FCLK Clock Frequency —

2T

CSS CS Setup Time 100

250
500

3T

CSH CS Hold Time 150

250

475
4T
5T

6T

CSD CS Disable Time 500 — ns —
SU Data Setup Time 30

HD Data Hold Time 50

100

100
7T
8T
9T

R CLK Rise Time — 2 µs (Note 1)
F CLK Fall Time — 2 µs (Note 1)
HI Clock High Time 150

230

475
10 T

LO Clock Low Time 150

230

475
11 T
12 T
13 T

14 T
15 T

16 T

CLD Clock Delay Time 50 — ns —
CLE Clock Enable Time 50 — ns —

V Output Valid from Clock Low —

HO Output Hold Time 0 — ns (Note 1)
DIS Outp ut Disable Time —

HS HOLD Setup Time 100

100

200
17 T

HH HOLD Hold Time 100

100

200
18 T

HZ HOLD Low to Output High-Z 100

150

200
19 T

HV HOLD High to Output Valid 100

150

200
20 T

WC Internal Write Cycle Time — 5 ms —

—
—

50
50

—
—

—
—

A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)

3
2
1

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

150
230
475

200
250
500

—
—
—

—
—
—

—
—
—

—
—
—

MHz
MHz
MHz

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

21 — Endurance 1M — E/W

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please

consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V
V

CC = 1.8V to 2.5V

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V
V

CC = 1.8V to 2.5V

CC = 4.5V to 5.5V

V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V

VCC = 4.5V to 5.5V
V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V

CC = 4.5V to 5.5V (Note 1)

V

CC = 2.5V to 4.5V (Note 1)

V

CC = 1.8V to 2.5V (Note 1)

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V (Note 1)

CC = 2.5V to 4.5V (Note 1)

V
V

CC = 1.8V to 2.5V (Note 1)

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V
V

CC = 1.8V to 2.5V

(Note 2)

 2003 Microchip Technology Inc. DS21204D-page 3

25AA040/25LC040/25C040

FIGURE 1-1: HOLD TIMING

CS

17

18

high-impedance

SCK

SO

16

n+2 n+1 n n-1

16

17

19

n

SI

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

CS

SCK

SI

SO

2
Mode 1,1
Mode 0,0

65

MSB in

high-impedance

7

don’t care

8

LSB in

5

n

3

n-1

4

12

11

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

9

10

SCK

13

SO

SI

DS21204D-page 4  2003 Microchip Technology Inc.

MSB out

don’t care

14

3

Mode 1,1
Mode 0,0

15

ISB out

25AA040/25LC040/25C040

TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT AC

AC Waveform:

V

LO = 0.2V —

VHI = VCC - 0.2V (Note 1)

HI = 4.0V (Note 2)

V

Timing Measurement Reference Lev el

Input 0.5 VCC
Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V

CC > 4.0V

SO

VCC

2.25 KΩ

1.8 KΩ

100 pF

 2003 Microchip Technology Inc. DS21204D-page 5

25AA040/25LC040/25C040

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP SOIC TSSOP Description

CS

SO 2 2 4 Serial Data Output
WP
V

SS 4 4 6 Ground

SI 5 5 7 Serial Data Input

SCK 6 6 8 Serial Clock Input

HOLD

V

CC 8 8 2 Supply Voltage

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardle ss of
the CS
program cycle, the device will go in Standby mode as
soon as the programming cycle is complete. When the
device is dese lected, SO goes into the hi gh-impedance
state, allowing multiple parts to share the same SPI
bus. A lo w-to-high transiti on on CS
sequence initiates an internal write cycle. After power­up, a low level on CS is r equ ired p r ior to any sequence
being initiated.

1 1 3 Chip Select Input

3 3 5 Write-Protect Pin

7 7 1 Hold Input

input signal. If CS is brought high during a

after a valid write

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication
between a master and the 25XX040. Instructions,
addresses or data pres en t on th e SI pin are latched on
the rising edge of t he c lo ck input, while data on the SO
pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the
25XX040 while in the middle of a seri al sequ ence wit h­out having to retransmit the entire sequ ence aga in at a
later time. It must be held high any time this function is
not being used. Once the device is selected and a
serial sequence is underway, the HOLD
pulled low to pause further serial communication with­out resetting the serial sequence. The HOLD pin must
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to­low transition. Th e 25XX040 must remain se lected d ur­ing this sequence. The SI, SCK and SO pins are in a
high-impedance state during the time the part is
paused and transitions on these p ins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.

pin may be

must be brought

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.

2.3 Write-Protect (WP)

This pin is a hardware write-protect input pin. When

is low, all writes to the arr ay or Status regis ter are

WP
disabled, but any other operation functions normally.
When WP is high, all functions, including nonvolatile
writes operate normally. WP
reset the write enable latch and inhibit programming,
except when an internal write has already begun. If an
internal write cycle has already begun, WP
will have no effect on the write. See Table 3-2 for Write­Protect Functionality Matrix.

going low at any time will

going low

DS21204D-page 6  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

3.0 FUNCTIONAL DESCRIPTION

3.1 Principles of Operation

The 25XX040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro­controllers. It may also interface with microcontrollers
that do not hav e a built-in SPI port by using discrete
I/O lines programmed properly with the software.

The 25XX040 conta ins an 8-bit instr uction regi ster . The
part is access ed v ia the SI pin, with data being clocked
in on the rising edge of SCK. The CS
and the HOLD
The WP
memory array.

Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The Most
Significant address bit (A8) is located in the instruction
byte. All instructions, addresses, and data are
transferred MSB first, LSB last.

Data is sampled on the fir st rising edge of SCK after CS
goes low. If the clock line is shared with other periph­eral devices on the SPI bus, the user can assert the
HOLD input and pl ace the 25X X040 in ‘HO LD’ mode.
After releasing the HOLD
from the point when the HOLD

pin must be high for the entire operation.

pin must be held high to allow writing to the

pin, operation will resume

3.2 Read Sequence

The part is selected by pulling CS low. The 8-bit read
instruction with the A8 address bit is transmitted to the
25XX040 followed by the lower 8-bit address (A7
through A0). After the correct READ instruction and
address are sent, the data stored in the memory at the
selected address is shif ted out on the SO pin. The da ta
stored in the memory at the next address can be read
sequentially by continuing to provide cloc k p uls es . Th e
internal address pointer is automatically incremented
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued
indefinitely. The read operation i s term inated by rai sing

pin (Figure 3-1).

the CS

TABLE 3-1: INSTRUCTION SET

pin must be low

was asserted.

3.3 Write Sequence

Prior to any attempt to write data to the 25XX040, the
write enable latch must be set by issuing the WREN
instruction (Figure3-4). This is done by setting CS
and then clocking out the proper instruction into the
25XX040. After all eight bits of the instruction are
transmitted, the CS
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write e nable latc h will not hav e been
properly set.

Once the write enable latch is set, the user may
proceed by setting the CS
instruction, followed by the address, and then the data
to be written. Keep in mind that the Most Significant
address bit (A8) is included in the instruction byte. Up
to 16 bytes of data can be sent to the 25XX040 before
a write cycle is nece ssary . Th e only restrictio n is that all
of the bytes must reside in the same page. A page
address begins wit h

1111

. If the internal address counter reaches XXXX

1111

and the clock conti nues, the counte r will roll back
to the first address of the page and overwrite any data
in the page that may have been written.

For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WIP, WEL, BP1 and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.

th

data byte has been clocked in. If CS is

must be brought high to set the

low, issuing a WRITE

XXXX 0000 and ends with XXXX

low

Instruction Name Instruction Format Description

READ

WRITE

WRDI
WREN
RDSR

WRSR

Note: A

 2003 Microchip Technology Inc. DS21204D-page 7

8 is the 9

0000 A8011
0000 A8010

0000 0100
0000 0110
0000 0101
0000 0001

th

address bit necessary to fully address 512 bytes.

Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read Status register
Write Status register

25AA040/25LC040/25C040

FIGURE 3-1: READ SEQUENCE

CS

0 23456789101112131415161718192021221

SCK

instruction lower address byte

SI

SO

01A800001A76541A0

high-impedance

FIGURE 3-2: BYTE WRITE SEQUENCE

CS

0 23456789101112131415161718192021221

SCK

instruction lower address byte

00A80000A7654

SI

SO

1

high-impedance

32

32

1A0

23

don’t care

data out

76543210

TWC

23

data byte

76543210

FIGURE 3-3: PAGE WRITE SEQUENCE

CS

91011 1415161718192021222324

34 35 36 39 40

33

76543210

SCK

SI

CS

SCK

SI

0 23456718

instruction lower address byte data byte 1

00A800001A7654

25 27 28 29 30 31 3226

data byte 2

76543210

13

3

21076543210

37 38

data byte 3

data byte n (16 max)

76543210

DS21204D-page 8  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

3.4 Write Enable (WREN) and Write
Disable (WRDI)

The 25XX040 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation w ill be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.

FIGURE 3-4: WRITE ENABLE SEQUENCE

CS

0 2345671

SCK

SI

SO

010000 01

high-impedance

The following is a list of conditions under which the
write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed
line is low

•WP

FIGURE 3-5: WRITE DISABLE SEQUENCE

CS

0 2345671

SCK

SI

SO

010000 010

high-impedance

 2003 Microchip Technology Inc. DS21204D-page 9

25AA040/25LC040/25C040

3.5 Read Sta tus Regist er (RDSR)

The RDSR instruction provides access to the Status
register. The Status register may be read at any time,
even during a write cycle. The Status register is
formatted as follows:

7654 3 2 1 0

XXXXBP1 BP0 WEL WIP

The Write-In-Process (WIP) bit indicates whether the
25XX040 is busy with a write operation. When set to a

1’, a write is in progress, when set to a ‘0’, no write is

‘
in progress. This bit is read only.

The W rite Enable Latch (WEL ) bit indi cates the st atus
of the write enable latch. When set to a ‘
allows writes to the array, when set to a ‘
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI comm ands
regardless of the st ate of write protection on the Status
register. This bit is read only.

The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the us er iss ui ng the WRSR instruction. Thes e
bits are nonvolatile.

See Figure 3-6 for RDSR timing sequence.

1’, the latch
0’, the latch

3.6 Write Status Register (WRSR)

The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the Status register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
illustrated in Table3-2.

See Figure 3-7 for WRSR timing sequence.

TABLE 3-2: ARRAY PROTECTION

BP1 BP0

00
01

10

11

Array Addresses

Write-Protected

none

upper 1/4

(0180h - 01FFh)

upper 1/2

(0100h - 01FFh)

all

(0000h - 01FFh)

FIGURE 3-6: READ STATUS REGISTER SEQUENCE

CS

8

7654 210

SCK

SO

0 2345671

instruction

SI

high-impedance

11000000

FIGURE 3-7: WRITE STATUS REGISTER SEQUENCE

CS

8

7654

SCK

0 2345671

instruction data to Status register

SI

01000000

9101112131415

data from Status register

3

9101112131415

210

3

high-impedance

SO

DS21204D-page 10  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

3.7 Data Protection

The following protection has been implemented to
prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set
the write enable latch

• After a byte write, page write or Status register
write, the write enable latch is reset

must be set high after the proper number of

•CS
clock cycles to start an internal write cycle

• Access to the array duri ng an internal write cycle
is ignored and programming is continued

• The write enable latc h is rese t wh en th e WP
low

pin is

3.8 Power-On State

The 25XX040 powers on in the following state:

• The device is in low-power Standby mode
=1)

(CS

• The write enable latch is reset

• SO is in high-impedance state

• A low level on CS

is required to enter active state

TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX

WP WEL Protected Blocks Unprotected Blocks Status Register

Low
High
High

X
0
1

Protected Protected Protected
Protected Protected Protected
Protected Writable Writable

 2003 Microchip Technology Inc. DS21204D-page 11

25AA040/25LC040/25C040

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

8-Lead PD IP (300 mil)

XXXXXXXX
XXXXXNNN

YYWW

8-Lead SOIC (150 mil)

XXXXXXXX
XXXXYYWW

NNN

8-Lead TSSOP

XXXX
XYWW

NNN

Example:

25AA040
I/PNNN

YYWW

Example:

25AA040
I/SNYYWW

NNN

Example:

5A4X
IYWW

NNN

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

Note: In the event the full Micro chip pa rt num ber can not be ma rked on on e line, it will

be carried over to the next line thus limiti ng the number of available characters
for customer specific information.

* Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.

DS21204D-page 12  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

E

β

eB

Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

Dimension Limits MIN NOM MAX MIN NOM MAX

1

α

A

c

Units INCHES* MILLIMETERS

n
p

c

α

β

.008 .012 .015 0.20 0.29 0.38

A1

B1

B

88

.100 2.54

51015 51015
51015 51015

A2

L

p

 2003 Microchip Technology Inc. DS21204D-page 13

25AA040/25LC040/25C040

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

Number of Pins
Pitch

Standoff §

Foot Angle
Lead Thickness

Mold Draft Angle Top
Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

n

45×

c

β

n
p

A1

f

c

α

β

1

h

A

f

L

048048

A1

MILLIMETERSINCHES*Units

1.27.050

α

A2

MAXNOMMINMAXNOMMINDimension Limits

88

1.751.551.35.069.061.053AOverall Height

1.551.421.32.061.056.052A2M old ed Packag e Thickness

0.250.180.10.010.007.004

6.206.025.79.244.237.228EOverall Width

3.993.913.71.157.154.146E1Molded Package Width

5.004.904.80.197.193.189DOverall Length

0.510.380.25.020.015.010hChamfer Distance

0.760.620.48.030.025.019LFoot Length

0.250.230.20.010.009.008

0.510.420.33.020.017.013BLead Width
1512015120
1512015120

DS21204D-page 14  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

n

B

1

A

c

A1

f

β

A1

n

p

f
c

α

β

048048

Number of Pins
Pitch

Standoff §

Foot Angle
Lead Thickne ss

Mold Draft Angle Top
Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086

L

MILLIMETERS*INCHESUnits

0.65.026

α

A2

MAXNOMMINMAXNOMMINDim ension Limits

88

1.10.043AOverall Height

0.950.900.85.037.035.033A2Molded Packag e Thick ness

0.150.100.05.006.004.002

6.506.386.25.256.251.246EOverall Width

4.504.404.30.177.173.169E1Molded Package Width

3.103.002.90.122.118.114DMolded Package Length

0.700.600.50.028.024.020LFoot Length

0.200.150.09.008.006.004

0.300.250.19.012.010.007BLead Wid th
10501050
10501050

 2003 Microchip Technology Inc. DS21204D-page 15

25AA040/25LC040/25C040

APPENDIX A: REVISION HISTORY

Revision D

Corrections to Section 1.0, Electrical Characteristics.

DS21204D-page 16  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip
World Wide Web site.

The web site is used b y Mic rochip as a me ans to m ake
files and information easily available to customers. To
view the site, the use r must have access to the Intern et
and a web browser, such as Netscape
Internet Explorer. Files are also available for FTP
download from our FTP site.

Connecting to the Microchip Internet
Web Site

The Microchip web site is available at the following
URL:

www.microchip.com

The file transfer site is available by using an FTP ser­vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari­ety of Micr ochip specific bu siness informatio n is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked
Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to
Microchip Products

• Conferences for p roducts, D evelopment Systems,
technical information and more

• Listing of seminars and events

®

or Microsoft

SYSTEMS INFORMATION AND UPGRADE HOT LINE

The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.

®

Plus, this line provides information on how customers
can receive the most c urrent upgrade kit s. The Hot Line
Numbers are:

1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.

042003

 2003 Microchip Technology Inc. DS21204D-page 17

25AA040/25LC040/25C040

READER RESPONSE

It is our intentio n to pro vi de you with the best documentation possible to ens ure suc c es sfu l u se of y ou r M ic roc hip prod­uct. If you wish to provid e your c omment s on org anizatio n, clarity, subject matter, a nd ways i n whic h our doc umenta tion
can better serve you, please FAX your comments to the Technical Publications Manager at [phone].

Please list the following information, and use this outline to provide us with your comments about this document.

To:
RE: Reader Response
From:

Application (optional):
Would you like a reply? Y N

Device: Literature Number:
Questions:

1. What are the best feat ures of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

Technical Publications Manager

Name
Company

Address
City / State / ZIP / Country

Telephone: (_______) _________ - _________

Total Pages Sent ________

FAX: (______) _________ - _________

DS21204D25AA040/25LC040/25C040

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21204D-page 18  2003 Microchip Technology Inc.

25AA040/25LC040/25C040

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX XXX

Device

Device: 25AA040: 4096-bit 1.8V SPI Serial EEPROM

Temperature
Range:

Package: P = Plastic DIP (300 mil body), 8-lead

Range

25AA040T: 4096-bit 1.8V SPI Serial EEPROM

(Tape and Reel)

25XX040X: 4096-bit 1.8V SPI Serial EEPRO M

in alternate pinout (ST only)

25AA040XT :4096-bit 1.8V SPI Serial EEPROM

in alternate pinout Tape and Reel

(ST only)
25LC040: 4096-bit 2.5V SPI Serial EEPROM
25LC040T: 4096-bit 2.5V SPI Serial EEPROM

(Tape and Reel)
25LC040X: 4096-bit 2.5V SPI Serial EEPROM

in alternate pinout (ST only)
25LC040XT:4096-bit 2.5V SPI Serial EEPROM

in alternate pinout Tape and Reel

(ST only)
25C040: 4096-bit 5.0V SPI Serial EEPROM
25C040T: 4096-bit 5.0V SPI Serial EEPROM

(Tape and Reel)
25C040X: 4096-bit 5.0V SPI Serial EEPROM

in alternate pinout (ST only)
25C040XT: 4096-bit 5.0V SPI Serial EEPROM

in alternate pinout Tape and Reel

(ST only)

I = -40 °C to+85 °C
E = -40 °C to+125 °C

SN = Plastic SOIC (150 mil body), 8-lead
ST = Plastic TSSOP (4.4 mm body), 8-lead

PatternPackageTemperature

Examples:

a) 25AA040-I/P: Industrial Temp.,

PDIP package

b) 25AA040-I/SN: Industrial Temp.,

SOIC package

c) 25AA040T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

d) 25AA040X-I/ST: Alternate Pinout,

Industrial Temp., TSSOP package

e) 25AA040XT-I/ST: Alternate Pinout, Tape

and Reel, Industrial Temp., TSSOP
package

f) 25LC040-I/P: Industrial Temp.,

PDIP package

g) 25LC040-I/SN: Industrial Temp.,

SOIC package

h) 25LC040T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

i) 25LC040X-I/ST: Alternate Pinout,

Industrial Temp., TSSOP package

j) 25LC040XT-I/ST: Alternate Pinout, Tape

and Reel, Industrial Temp., TSSOP
package

k) 25C040-I/P: Industrial Temp.,

PDIP package

l) 25C040-I/SN: Industrial Temp.,

SOIC package

m) 25C040T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

n) 25C040X-I/ST : Alternate Pinout,

Industrial Temp., TSSOP package

o) 25C040XT-I/ST: Alternate Pinout, Tape

and Reel, Industrial Temp., TSSOP
package

p) 25C040-E/P: Extended Temp.,

PDIP package

q) 25C040-E/SN: Extended Temp.,

SOIC package

r) 25C040T-E/SN: Tape and Reel,

Extended T emp., SOIC package

s) 25C040X-E/ST: Alternate Pinout,

Extended T emp., TSSOP package

t) 25C040XT-E/ST: Alternate Pinout, Tape

and Reel, Extended Temp., TSSOP pack­age

 2003 Microchip Technology Inc. DS21204D-page 19

25AA040/25LC040/25C040

NOTES:

DS21204D-page 20  2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protection fea tures of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com­ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con­veyed, implicitly or otherwise, under any intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, MPLAB, PIC, PICmic ro, PI C START,

PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

 2003 Microchip Technology Inc. DS21204D-page 21

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]
Technical Support: 480-792-7627
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Dallas

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Detroit

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Kokomo

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Los Angeles

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Toronto

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ASIA/PACIFIC

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China - Fuzhou

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China - Hong Kong SAR

Unit 901-6, Tower 2, Metroplaza
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China - Shanghai

Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
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China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
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China - Shunde

Room 401, Hongjian Building
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Tel: [phone] Fax: [phone]

China - Qingdao

Rm. B505A, Fullhope Plaza,
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India

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Japan

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Korea

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Tel: [phone] Fax: [phone] or
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Singapore

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Taiwan

Kaohsiung Branch
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Fax: [phone]

Taiwan

Taiwan Branch
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EUROPE

Austria

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Denmark

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France

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Germany

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Italy

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Netherlands

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United Kingdom

505 Eskdale Road
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Berkshir e, England RG41 5T U
Tel: [phone]
Fax: [phone]

07/28/03

DS21204D-page 22  2003 Microchip Technology Inc.