MICROCHIP 25AA640, 25LC640 Technical data
25AA640/25LC640
64K SPI™ Bus Serial EEPROM
Device Selection Table
Part
Number
25AA640 1.8-5.5V 1 MHz I
25LC640 2.5-5.5V 2 MHz I
25LC640 4.5-5.5V 3/2.5 MHz I, E
VCC
Range
Max Clock
Frequency
Features
• Low-power CMOS technology
- Write current: 3 mA typical
- Read current: 500
- Standby current: 500 nA typical
• 8192 x 8 bit organization
• 32 byte page
• Write cycle time: 5 ms max.
• Self-timed erase and write cycles
• Block write protection
- Protect none, 1/4, 1/2 or all of array
• Built-in write protect ion
- Power on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability
- Data retention: > 200 years
- ESD protection: > 4000V
• 8-pin PDIP, SOIC and TSSOP packages
• Temperature ranges supported:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
µA typical
Temp
Ranges
Description
The Microchip Technology Inc. 25AA640/25LC640
(25XX640
PROM [EEPROM]. The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the dev ice is contro lled th rough a C hip
Select (CS
Communication to the device can be paused via the
hold pin (HOLD
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
*
) is a 64 Kbit Serial Electrically Erasable
) input.
). While the device is paused,
Block Diagram
SO
CS
SCK
HOLD
WP
SI
Status
Register
I/O Control
Logic
VCC
VSS
Memory
Control
Logic
XDEC
HV Generator
EEPROM
Array
Page
Latches
Y Decoder
Sense Amp.
R/W Control
Package Types
PDIP/SOIC TSSOP
CS
1
25XX640
SO
2
WP
3
VSS
4
*25XX640 is used in this document as a generic part number for the 25AA640/25LC640 devices.
SPI is a registered trademark of Motorola Corporation.
2004 Microchip Technology Inc. DS21223G-page 1
VCC
8
HOLD
7
SCK
6
5
SI
HOLD
VCC
CS
SO
1
2
3
4
25XX640
8
SCK
7
SI
6
V
SS
5
WP
25AA640/25LC640
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-65°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
D1 V
D2 VIH2 0.7 VCC VCC + 1 V VCC < 2.7V (Note 1)
D3 V
D4 VIL2 -0.3 0.2 VCC VVCC < 2.7V (Note 1)
Sym Characteristics Min Max Units Conditions
IH1 High-level input
voltage
IL1 Low-level input
voltage
D5 VOL Low-level output
voltage
D6 VOH High-level output
Industrial (I): T
Automotive (E): T
2.0 VCC + 1 V VCC ≥ 2.7V (Note 1)
-0.3 0.8 V VCC ≥ 2.7V (Note 1)
—0.4VIOL = 2.1 mA
—0.2VI
VCC - 0.5 — V IOH = -400 µA
voltage
D7 I
D8 ILO Output leakage
LI Input leakage current — ±1 µACS = VCC, VIN = VSS TO VCC
—±1µACS = VCC, VOUT = VSS TO VCC
current
D9 CINT Internal Capacitance
—7pFT
(all inputs and
outputs)
D10 I
CC Read Operating Current —
—
D11 I
CC Write —
—
D12 I
CCS Standby Current —
—
Note 1: This parameter is periodically sampled and not 100% tested.
A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 4.5V to 5.5V
OL = 1.0 mA, VCC = < 2.5V
A = 25°C, CLK = 1.0 MHz,
CC = 5.0V (Note 1)
V
1
500
mAµAVCC = 5.5V; FCLK = 3.0MHz;
SO = Open
CC = 2.5V; FCLK = 2.0MHz;
V
SO = Open
5
3
5
1
mAmAVCC = 5.5V
CC = 2.5V
V
µAµACS = VCC = 5.5V, Inputs tied to VCC or
SS
V
CS = VCC = 2.5V, Inputs tied to VCC or
V
SS
DS21223G-page 2 2004 Microchip Technology Inc.
25AA640/25LC640
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
No.
1F
Sym Characteristic Min Max Units Conditions
CLK Clock Frequency —
Industrial (I): T
Automotive (E): T
—
—
2T
CSS CS Setup Time 100
250
500
3T
CSH CS Hold Time 150
250
475
4T
5T
CSD CS Disable Time 500 — ns
SU Data Setup Time 30
50
50
6T
HD Data Hold Time 50
100
100
7T
8T
9T
R CLK Rise Time — 2 µs (Note 1)
F CLK Fall Time — 2 µs (Note 1)
HI Clock High Time 150
230
475
10 T
LO Clock Low Time 150
230
475
11 T
12 T
13 T
CLD Clock Delay Time 50 — ns
CLE Clock Enable Time 50 — ns
V Output Valid fro m
Clock Low
—
—
—
14 T
15 T
HO Output Hold Time 0 — ns (Note 1)
DIS Output Disable Time —
—
—
16 T
HS HOLD Setup Time 100
100
200
17 T
HH HOLD Hold Time 100
100
200
18 T
HZ HOLD Low to Outpu t
High-Z
100
150
200
19 T
HV HOLD High to Output
Valid
100
150
200
20 T
WC Internal Write Cycle
—5ms
Time
21 — Endurance 1M — E/W
Note 1: This parameter is periodically sampled and not 100% tested.
2: F
CLK max. = 2.5 MHz for TA > 85°C.
3: This parameter is not tested but established by characterization. For endurance estimates in a specific application,
please consult the Total Endurance™ Model which can be obtained from our web site.
A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 4.5V to 5.5V
3
2
1
MHz
MHz
MHz
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
230
475
200
250
500
—
—
—
—
—
—
—
—
—
—
—
—
Cycles
CC = 4.5V to 5.5V (Note 2)
V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
ns
VCC = 4.5V to 5.5V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
V
CC = 1.8V to 5.5V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
V
CC = 1.8V to 5.5V
CC = 4.5V to 5.5V
V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
CC = 4.5V to 5.5V
V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
V
CC = 2.5V to 5.5V
CC = 1.8V to 5.5V
V
CC = 4.5V to 5.5V (Note 1)
V
CC = 2.5V to 5.5V (Note 1)
V
CC = 1.8V to 5.5V (Note 1)
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
CC = 1.8V to 5.5V
V
VCC = 4.5V to 5.5V (Note 1)
CC = 2.5V to 5.5V (Note 1)
V
CC = 1.8V to 5.5V (Note 1)
V
VCC = 4.5V to 5.5V
CC = 2.5V to 5.5V
V
V
CC = 1.8V to 5.5V
(Note 3)
2004 Microchip Technology Inc. DS21223G-page 3
25AA640/25LC640
FIGURE 1-1: HOLD TIMING
CS
16 16 17
SCK
SO
n + 2 n + 1 n n - 1
17
High-impedance
1918
n
SI
HOLD
n + 2 n + 1 n
FIGURE 1-2: SERIAL INPUT TIMING
CS
SCK
SI
SO
2
Mode 1,1
Mode 0,0
65
MSB In
High-impedance
7
Don’t Care
8
3
LSB In
5
n
n - 1
4
12
11
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
9
10
SCK
13
SO
SI
DS21223G-page 4 2004 Microchip Technology Inc.
MSB Out
Don’t Care
14
3
Mode 1,1
Mode 0,0
15
LSB Out
25AA640/25LC640
TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC TEST CIRCUIT
AC Waveform:
VLO = 0.2V
HI = VCC – 0.2V (Note 1)
V
VHI = 4.0V (Note 2)
Timing Measurement Reference Lev el
Input 0.5 V
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For V
CC > 4.0V
CC
SO
VCC
2.25 kΩ
1.8 kΩ
100 pF
2004 Microchip Technology Inc. DS21223G-page 5
25AA640/25LC640
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name PDIP SOIC TSSOP Description
CS
SO 2 2 4 Serial Data Output
WP
SS 44 6Ground
V
SI 5 5 7 Serial Data Input
SCK 6 6 8 Serial Clock Input
HOLD
V
CC 8 8 2 Supply Voltage
2.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardle ss of
the CS
high during a program cycle, the device will go into
Standby mode when the programming cycle is
complete. When the device is deselected, SO goes to
the high-impedance state, allowing multiple parts to
share the same SPI bus. A low-to-hi gh transition on CS
after a valid write sequence initiates an internal write
cycle. After power-up, a high-to-lo w trans itio n on CS
required prior to any sequence being initiated.
1 1 3 Chip Select Input
3 3 5 Write-Protect Pin
7 7 1 Hold Input
input signal. If CS is brought high, or remains
is
2.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX640. Instructions,
addresses, or data present on the SI pin are latched on
the rising edge of t he c lo ck input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX640 while in the middle of a seri al sequ ence wit hout having to retransmit the entire sequence over
again. It must be held high any time this function is not
being used. Once the device is selected and a serial
sequence is underway, the HOLD
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX640 must remain selected
during this sequenc e. The SI, SC K, an d SO p ins a re i n
a high-impedance state during the time the device is
paused and transitions on these p ins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
pin may be pulled
must be brought
2.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25XX640.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the no nvolatil e bits in the Status register
is disabled. All other operations function normally.
When WP
nonvolatile bits in the Status register operate normally.
If the WPEN bit is set, WP low during a Status register
write sequence will disable writing to the Status register. If an internal write cycle has already begun, WP
going low will have no effect on the write.
The WP
the Status register is low. This allows the user to install
the 25XX640 in a system with WP
still be able to write to the Status register. The WP
functions will be enabled when the WPEN bit is set
high.
is high, all functions, including writes to the
pin function is blocked when the WPEN bit in
pin grounded and
pin
DS21223G-page 6 2004 Microchip Technology Inc.
25AA640/25LC640
3.0 FUNCTIONAL DESCRIPTION
3.1 Principles Of Operation
The 25XX640 is a 8192 byte Serial EEPROM desi gned
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers
that do not hav e a built-in SPI port by using discrete
I/O lines programmed properly with the software.
The 25XX640 conta ins an 8-bit instr uction regi ster . The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
be low and the HOLD
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data is sampled on the fir st rising edge of SCK after CS
goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD
mode. After releasing the HOLD
resume from the point when the HOLD
input and place the 25XX640 in ‘HOLD’
pin must be high fo r the entire
pin, operation will
3.2 Read Sequence
The device is sele cted by p ulling CS low. The 8-bit read
instruction is transmitted to the 25XX640 followed by
the 16-bit address with the three MSBs of the address
being don’t care bits. After the correct read instruction
and address are sent, the d ata st ored i n the memo ry at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continu ing to provide clock pul ses.
The internal address pointer is automatically incremented to the next higher address after each byte of
data is shifted out. When the highest address is
reached (1FFFh), the address counter rolls over to
address 0000h allow in g th e rea d c yc le to b e co nti nue d
indefinitely. The read operation i s term inated by rai sing
pin (Figure 3-1).
the CS
pin must
was asserted.
3.3 Write Sequence
Prior to any attempt to wri t e d at a to the 25XX6 40 arra y
or St atus regis ter, the write enable lat ch mus t be s et by
issuing the WREN instruction (Figure 3-4). This is done
by setting CS
instruction into the 25XX640. After all eight bits of the
instruction are transmitted, the CS
high to set the write enable latch. If the write operation
is initiated immediately after the WREN instruction without CS
to the array because the write enable latch will no t have
been properly set.
Once the write enable latch is set, the user may
proceed by setting the CS
instruction, followed by the address, and then the data
to be written. Up to 32 bytes of data can be sent to the
25XX640 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A page address begins with XXX0 0000
and ends with XXX1 1111. If the internal address
counter reaches XXX1 1111 and the clock continues,
the counter will roll bac k to the first add ress of the p age
and overwrite any da ta in the p age that m ay have bee n
written.
For the data to be actually written to the array, the CS
must be brought high after the Leas t Significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1, and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
low and then clocking out the proper
must be brought
being brought high, the data will not be written
low, issuing a WRITE
th
data byte has been clocked in. If CS is
TABLE 3-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WREN 0000 0110 Set the write enable latch (enable write operations)
WRDI 0000 0100 Reset the write enable latch (disable write operations)
RDSR 0000 0101 Read Status register
WRSR 0000 0001 Write Status register
2004 Microchip Technology Inc. DS21223G-page 7
25AA640/25LC640
FIGURE 3-1: READ SEQUENCE
CS
0 234567891011 21222324252627282930311
SCK
Instruction 16 Bit Address
SI
0100000 1 15 14 13 12 210
High-impedance
SO
FIGURE 3-2: BYTE WRITE SEQUENCE
CS
Instruction 16 Bit Address Data Byte
SI
SO
0000000 1 15 14 13 12 21076543210
High-impedance
FIGURE 3-3: PAGE WRITE SEQUENCE
CS
8
91011 2122232425262728293031
SCK
SI
0 2345671
Instruction 16 Bit Address Data Byte 1
0000000 1 15 14 13 12
Data Out
76543210
Twc
21076543210
CS
32 34 35 36 37 38 3933
SCK
Data Byte 2
SI
DS21223G-page 8 2004 Microchip Technology Inc.
76543210
41 42 43 46 47
40
Data Byte 3
76543210
44 45
Data Byte n (32 max)
76543210
Loading...