MICROCHIP 25AA256, 25LC256 Technical data

25AA256/25LC256

256K SPI™ Bus Serial EEPROM

Device Selection Table

Part Number VCC Range Page Size Temp. Ranges Packages

25LC256 2.5-5.5V 64 Byte I, E P, SN, ST, MF 25AA256 1.8-5.5V 64 Byte I P, SN, ST, MF

Features

• Max. clock 10 MHz

• Low-power CMOS technology

- Max. Write Current: 5 mA at 5.5V, 10 MHz

- Read Current: 5 mA at 5.5V, 10 MHz

- Standby Current: 1 µA at 5.5V

• 32,768 x 8-bit organization

• 64 byte page

• Self-timed ERASE and WRITE cycles (5 ms max.)

• Block write protection

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential read

• High reliability

- Endurance: 1,000,000 erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• Temperature ranges supported;

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

• Standard and Pb-free packages available

Pin Function Table

Name Function

CS Chip Select Input SO Serial Data Output

SS Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD

CC Supply Voltage

* 25XX256

Write-Protect

Hold Input

is used in this document as a generic part number for the 25AA256, 25LC256 devices.

Description

The Microchip Technology Inc. 25AA256/25LC256 (25XX256 PROMs. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS input.

Communication to the device can be paused via the hold pin (HOLD transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts.

The 25XX256 is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead DFN and 8-lead TSSOP. Pb-free (Pure Sn) finish is also available.

) are 256k-bit Serial Electrically Erasable

). While the device is paused,

Package Types (not to scale)

TSSOP

(ST)

SPI is a registered trademark of Motorola Corporation.

CS SO

VSS

HOLD

SCK

DFN

(MF)

1 2 3 4

25LC256

PDIP/SOIC

(P, SN)

2 3

VCC

HOLD

SCK

25LC256

8 7 6 5

V HOLD

SCK SI

)

 2003 Microchip Technology Inc. Preliminary DS21822C-page 1

25AA256/25LC256

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

D001 V

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input

voltage D002 V D003 VIL2 -0.3 0.2VCC VVCC < 2.7V D004 V D005 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V

IL1 Low-level input

voltage

OL Low-level output

voltage D006 VOH High-level output

voltage D007 I

LI Input leakage current — ±1 µACS = VCC, VIN = VSS TO VCC

D008 ILO Output leaka ge

current D009 CINT Internal Capacitanc e

(all inputs and

outputs) D010 I

CC Read

Operating Current

D011 I

CC Write —

D012 ICCS

Standby Current

Note: This parameter is periodically sampled and not 100% tested.

Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E): T

A = -40°C to +125°C VCC = 2.5V to 5.5V

.7 VCC VCC+1 V

-0.3 0.3VCC VVCC ≥ 2.7V

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH = -400 µA

—±1µACS = VCC, VOUT = VSS TO VCC

—7pFTA = 25°C, CLK = 1.0 MHz,

CC = 5.0V (Note)

— —

2.5

mAmAVCC = 5.5V; FCLK = 10.0MHz;

SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open

— —

—

5 3

5 1

mAmAVCC = 5.5V

CC = 2.5V

µAµACS

= VCC = 5.5V, Inputs tied to VCC or

SS, 125°C

V CS

= VCC = 5.5V, Inputs tied to VCC or

SS, 85°C

DS21822C-page 2 Preliminary  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

25AA256/25LC256

AC CHARACTERISTICS

Param.

No.

Sym. Characteristic Min. Max. Units Test Conditions

CLK Clock Frequency —

CSS CS Setup Time 50

CSH CS Hold Time 100

CSD CS Disable Time 50 — ns —

5 Tsu Data Setup Time 10

6THD Data Hold Time 20

7T 8T 9T

10 T

11 T 12 T 13 T

R CLK Rise Time — 2 µs (Note 1) F CLK Fall Time — 2 µs (Note 1) HI Clock High Time 50

LO Clock Low Time 50

CLD Clock Delay Time 50 — ns — CLE Clock Enable Time 50 — ns —

V Output Valid from Clock

Low

14 T 15 T

16 T

HO Output Hold Time 0 — ns (Note 1) DIS Output Disable Time —

HS HOLD Setup Time 20

Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E): T

A = -40°C to +125°C VCC = 2.5V to 5.5V

10 — —

5 3

—

100 150

—

200 250

—

— 20 30

—

— 40 50

—

100 150

—

100 150

— — —

—

100 160

40 — —

160

— 40 80

—

Note 1: This parameter is periodically sampled and not 100% tested.

2: TWC begins on the risi ng edg e o f C S after a valid write sequence a nd ends when the internal wri te c yc le is

complete.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.

MHz MHz MHz

ns ns ns

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V(Note 1)

2.5V ≤ Vcc ≤ 4.5V(Note 1)

1.8V ≤ Vcc ≤ 2.5V(Note 1)

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

 2003 Microchip Technology Inc. Preliminary DS 21822C-page 3

25AA256/25LC256

TABLE 1-2: AC CHARACTERISTICS (CONTINUED)

AC CHARACTERISTICS

Param.

No.

Sym. Characteristic Min. Max. Units Test Conditions

Industrial (I): T Automotive (E): T

17 THH HOLD Hold Time 20

40 80

18 T

HZ HOLD Low to Output

High-Z

30 60

160

19 T

HV HOLD High to Output

Valid

30 60

160

20 T

WC Internal Write Cycle Time — 5 ms (NOTE 2)

A = -40°C to +85°C VCC = 1.8V to 5.5V A = -40°C to +125°C VCC = 2.5V to 5.5V

— — —

ns ns ns

21 — Endurance 1M — E/W

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

WC begins on the rising edg e of CS after a valid write sequence and ends when the int ernal write cycle is

2: T

complete.

3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

4.5V ≤ Vcc ≤ 5.5V(Note 1)

2.5V ≤ Vcc < 4.5V(Note 1)

1.8V ≤ Vcc < 2.5V(Note 1)

4.5V ≤ Vcc ≤ 5.5V

2.5V ≤ Vcc < 4.5V

1.8V ≤ Vcc < 2.5V

OTE 3)

TABLE 1-3: AC TEST CONDITIONS

AC Waveform:

VLO = 0.2V — VHI = VCC - 0.2V (Note 1)

HI = 4.0V (Note 2)

V CL = 100 pF —

Timing Measurement Reference Lev el

Input 0.5 V Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For Vcc > 4.0V

DS21822C-page 4 Preliminary  2003 Microchip Technology Inc.

FIGURE 1-1: HOLD TIMING

SCK

n+2 n+1 n n-1

high-impedance

25AA256/25LC256

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

2 Mode 1,1 Mode 0,0

SCK

MSB in

high-impedance

don’t care

LSB in

n-1

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

 2003 Microchip Technology Inc. Preliminary DS 21822C-page 5

MSB out

don’t care

Mode 1,1 Mode 0,0

ISB out

25AA256/25LC256

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 25XX256 is a 32768 byte Serial EEPROM designed to interf ace di rec tly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PICmicro microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol.

The 25XX256 conta ins an 8-bit instr uction regi ster . The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS be low and the HOLD operation.

Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last.

Data (SI) is sampled on the first rising edge of SCK after CS peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX256 in ‘HOLD’ mode. After releasing the HOLD resume from the point when the HOLD

microcont rollers. It may also interfac e with

pin must

pin must be high fo r the entire

goes low. If the clock line is shared with other

pin, operation will

was asserted.

2.2 Read Sequence

The device is sele cted by p ulling CS low. The 8-bit read instruction is transmitted to the 25XX256 followed by the 16-bit address, with the first MSB of the address being a don’t care bit. After the correct read instruction and address are sent, the d ata st ored i n the memo ry at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide c lock pulses . The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (7FFFh), the address counter rolls over to address 0000h allow in g th e rea d c yc le to b e co nti nue d indefinitely. The read operation i s term inated by rai sing

pin (Figure 2 -1).

the CS

2.3 Write Sequence

Prior to any attempt to write data to the 25XX256, the write enable latch must be set by issuing the WREN instruction (Figure2-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX256. After all eight bits of the instruction are transmitted, the CS write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latc h will not hav e been properly set.

Once the write enable latch is set, the user may proceed by setting the CS instruction, followed by the 16-bit address, with the first MSB of the address bein g a don’t c are bit, and then the data to be writ ten. Up to 64 bytes of d ata ca n be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page.

Note: Page write operations are limited t o writing

bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buf fer size (or ‘page size’) and, end at addresses that are integer multiples of page size - 1. If a Page Write comman d attem pt s to wri te a cross a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.

For the data to be actually written to the array, the CS must be brought high after the Leas t Significant bit (D0) of the n brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.

data byte has been clocked in. If CS is

must be brought high to set the

low, issuing a WRITE

DS21822C-page 6 Preliminary  2003 Microchip Technology Inc.

BLOCK DIAGRAM

25AA256/25LC256

SO CS

SCK

HOLD

I/O Control

Status

Logic

Memory

Control

Logic

VCC VSS

Dec

HV Generato r

EEPROM

Array

Page Latches

Y Decoder

Sense Amp. R/W Control

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ

WRITE

WRDI WREN RDSR WRSR

0000 0011 0000 0010 0000 0100 0000 0110 0000 0101 0000 0001

Read data from memory array beginning at selected address Write data to memory array beginning at selected address Reset the write enable latch (disable write operations) Set the write enable latch (enable write operations) Read Status register Write Status register

FIGURE 2-1: READ SEQUENCE

0 234567891011 21222324252627282930311

SCK

instruction 16-bit address

 2003 Microchip Technology Inc. Preliminary DS 21822C-page 7

0100000 1 15 14 13 12 210

high-impedance

data out

76543210

25AA256/25LC256

FIGURE 2-2: BYTE WRITE SEQUENCE

91011 2122232425262728293031

SCK

0 23456718

instruction 16-bit address data byte

0000000 1 15 14 13 12

high-impedance

FIGURE 2-3: PAGE WRITE SEQUENCE

SCK

0 2345671

instruction 16-bit address data byte 1

0000000 1 15 14 13 12

Twc

21076543210

9 1011 2122232425262728293031

21076543210

SCK

32 34 35 36 37 38 3933

data byte 2

76543210

41 42 43 46 47

data byte 3

76543210

44 45

data byte n (64 max)

76543210

DS21822C-page 8 Preliminary  2003 Microchip Technology Inc.

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