25AA256/25LC256
256K SPI™ Bus Serial EEPROM
Device Selection Table
Part Number VCC Range Page Size Temp. Ranges Packages
25LC256 2.5-5.5V 64 Byte I, E P, SN, ST, MF
25AA256 1.8-5.5V 64 Byte I P, SN, ST, MF
Features
• Max. clock 10 MHz
• Low-power CMOS technology
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 1 µA at 5.5V
• 32,768 x 8-bit organization
• 64 byte page
• Self-timed ERASE and WRITE cycles (5 ms
max.)
• Block write protection
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature ranges supported;
- Industrial (I): -40°Cto +85°C
- Automotive (E): -40°C to +125°C
• Standard and Pb-free packages available
Pin Function Table
Name Function
CS Chip Select Input
SO Serial Data Output
WP
SS Ground
V
SI Serial Data Input
SCK Serial Clock Input
HOLD
CC Supply Voltage
V
* 25XX256
Write-Protect
Hold Input
is used in this document as a generic part number for the 25AA256, 25LC256 devices.
Description
The Microchip Technology Inc. 25AA256/25LC256
(25XX256
PROMs. The memory is accessed via a simple Serial
Peripheral Interface™ (SPI™) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS
input.
Communication to the device can be paused via the
hold pin (HOLD
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 25XX256 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead DFN and 8-lead TSSOP.
Pb-free (Pure Sn) finish is also available.
*
) are 256k-bit Serial Electrically Erasable
). While the device is paused,
Package Types (not to scale)
TSSOP
(ST)
1
CS
2
SO
3
WP
4
V
SS
SPI is a registered trademark of Motorola Corporation.
CS
SO
WP
VSS
8
CC
V
7
HOLD
6
SCK
5
SI
DFN
(MF)
1
2
3
4
V
25LC256
PDIP/SOIC
(P, SN)
CS
1
SO
2
3
WP
SS
4
8
VCC
7
HOLD
6
SCK
5
SI
25LC256
8
7
6
5
CC
V
HOLD
SCK
SI
)
2003 Microchip Technology Inc. Preliminary DS21822C-page 1
25AA256/25LC256
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias...............................................................................................................-40°C to 125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
D001 V
Sym. Characteristic Min. Max. Units Test Conditions
IH1 High-level input
voltage
D002 V
D003 VIL2 -0.3 0.2VCC VVCC < 2.7V
D004 V
D005 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V
IL1 Low-level input
voltage
OL Low-level output
voltage
D006 VOH High-level output
voltage
D007 I
LI Input leakage current — ±1 µACS = VCC, VIN = VSS TO VCC
D008 ILO Output leaka ge
current
D009 CINT Internal Capacitanc e
(all inputs and
outputs)
D010 I
CC Read
Operating Current
D011 I
CC Write —
D012 ICCS
Standby Current
Note: This parameter is periodically sampled and not 100% tested.
Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C VCC = 2.5V to 5.5V
.7 VCC VCC+1 V
-0.3 0.3VCC VVCC ≥ 2.7V
—0.4VIOL = 2.1 mA
VCC -0.5 — V IOH = -400 µA
—±1µACS = VCC, VOUT = VSS TO VCC
—7pFTA = 25°C, CLK = 1.0 MHz,
CC = 5.0V (Note)
V
—
—
5
2.5
mAmAVCC = 5.5V; FCLK = 10.0MHz;
SO = Open
VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
—
—
—
5
3
5
1
mAmAVCC = 5.5V
V
CC = 2.5V
µAµACS
= VCC = 5.5V, Inputs tied to VCC or
SS, 125°C
V
CS
= VCC = 5.5V, Inputs tied to VCC or
SS, 85°C
V
DS21822C-page 2 Preliminary 2003 Microchip Technology Inc.
TABLE 1-2: AC CHARACTERISTICS
25AA256/25LC256
AC CHARACTERISTICS
Param.
No.
1F
2T
3T
4T
Sym. Characteristic Min. Max. Units Test Conditions
CLK Clock Frequency —
CSS CS Setup Time 50
CSH CS Hold Time 100
CSD CS Disable Time 50 — ns —
5 Tsu Data Setup Time 10
6THD Data Hold Time 20
7T
8T
9T
10 T
11 T
12 T
13 T
R CLK Rise Time — 2 µs (Note 1)
F CLK Fall Time — 2 µs (Note 1)
HI Clock High Time 50
LO Clock Low Time 50
CLD Clock Delay Time 50 — ns —
CLE Clock Enable Time 50 — ns —
V Output Valid from Clock
Low
14 T
15 T
16 T
HO Output Hold Time 0 — ns (Note 1)
DIS Output Disable Time —
HS HOLD Setup Time 20
Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E): T
A = -40°C to +125°C VCC = 2.5V to 5.5V
10
—
—
5
3
—
100
150
—
—
—
200
250
—
—
—
20
30
—
—
—
40
50
—
—
—
100
150
—
—
—
100
150
—
—
—
—
—
50
100
160
40
—
—
80
160
—
40
80
—
—
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the risi ng edg e o f C S after a valid write sequence a nd ends when the internal wri te c yc le is
complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V(Note 1)
2.5V ≤ Vcc ≤ 4.5V(Note 1)
1.8V ≤ Vcc ≤ 2.5V(Note 1)
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
2003 Microchip Technology Inc. Preliminary DS 21822C-page 3
25AA256/25LC256
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS
Param.
No.
Sym. Characteristic Min. Max. Units Test Conditions
Industrial (I): T
Automotive (E): T
17 THH HOLD Hold Time 20
40
80
18 T
HZ HOLD Low to Output
High-Z
30
60
160
19 T
HV HOLD High to Output
Valid
30
60
160
20 T
WC Internal Write Cycle Time — 5 ms (NOTE 2)
A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 2.5V to 5.5V
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
21 — Endurance 1M — E/W
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
WC begins on the rising edg e of CS after a valid write sequence and ends when the int ernal write cycle is
2: T
complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
4.5V ≤ Vcc ≤ 5.5V(Note 1)
2.5V ≤ Vcc < 4.5V(Note 1)
1.8V ≤ Vcc < 2.5V(Note 1)
4.5V ≤ Vcc ≤ 5.5V
2.5V ≤ Vcc < 4.5V
1.8V ≤ Vcc < 2.5V
(N
OTE 3)
TABLE 1-3: AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V —
VHI = VCC - 0.2V (Note 1)
HI = 4.0V (Note 2)
V
CL = 100 pF —
Timing Measurement Reference Lev el
Input 0.5 V
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For Vcc > 4.0V
CC
DS21822C-page 4 Preliminary 2003 Microchip Technology Inc.
FIGURE 1-1: HOLD TIMING
CS
SCK
SO
n+2 n+1 n n-1
16
17
18
high-impedance
25AA256/25LC256
16
17
19
n
SI
HOLD
n+2 n+1 n
FIGURE 1-2: SERIAL INPUT TIMING
CS
2
Mode 1,1
Mode 0,0
SCK
65
SI
SO
MSB in
high-impedance
don’t care
7
8
LSB in
5
n
3
n-1
4
12
11
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
9
10
SCK
13
SO
SI
2003 Microchip Technology Inc. Preliminary DS 21822C-page 5
MSB out
don’t care
14
3
Mode 1,1
Mode 0,0
15
ISB out
25AA256/25LC256
2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 25XX256 is a 32768 byte Serial EEPROM
designed to interf ace di rec tly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s
PICmicro
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol.
The 25XX256 conta ins an 8-bit instr uction regi ster . The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
be low and the HOLD
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX256 in ‘HOLD’
mode. After releasing the HOLD
resume from the point when the HOLD
®
microcont rollers. It may also interfac e with
pin must
pin must be high fo r the entire
goes low. If the clock line is shared with other
pin, operation will
was asserted.
2.2 Read Sequence
The device is sele cted by p ulling CS low. The 8-bit read
instruction is transmitted to the 25XX256 followed by
the 16-bit address, with the first MSB of the address
being a don’t care bit. After the correct read instruction
and address are sent, the d ata st ored i n the memo ry at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide c lock pulses .
The internal address pointer is automatically incremented to the next higher address after each byte of
data is shifted out. When the highest address is
reached (7FFFh), the address counter rolls over to
address 0000h allow in g th e rea d c yc le to b e co nti nue d
indefinitely. The read operation i s term inated by rai sing
pin (Figure 2 -1).
the CS
2.3 Write Sequence
Prior to any attempt to write data to the 25XX256, the
write enable latch must be set by issuing the WREN
instruction (Figure2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX256. After all eight bits of the instruction are
transmitted, the CS
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latc h will not hav e been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS
instruction, followed by the 16-bit address, with the first
MSB of the address bein g a don’t c are bit, and then the
data to be writ ten. Up to 64 bytes of d ata ca n be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
Note: Page write operations are limited t o writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buf fer size (or
‘page size’) and, end at addresses that are
integer multiples of page size - 1. If a Page
Write comman d attem pt s to wri te a cross a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Leas t Significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
th
data byte has been clocked in. If CS is
must be brought high to set the
low, issuing a WRITE
DS21822C-page 6 Preliminary 2003 Microchip Technology Inc.
BLOCK DIAGRAM
25AA256/25LC256
SO
CS
SCK
HOLD
WP
I/O Control
SI
Status
Register
Logic
Memory
Control
Logic
VCC
VSS
X
Dec
HV Generato r
EEPROM
Array
Page Latches
Y Decoder
Sense Amp.
R/W Control
TABLE 2-1: INSTRUCTION SET
Instruction Name Instruction Format Description
READ
WRITE
WRDI
WREN
RDSR
WRSR
0000 0011
0000 0010
0000 0100
0000 0110
0000 0101
0000 0001
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read Status register
Write Status register
FIGURE 2-1: READ SEQUENCE
CS
0 234567891011 21222324252627282930311
SCK
instruction 16-bit address
SI
SO
2003 Microchip Technology Inc. Preliminary DS 21822C-page 7
0100000 1 15 14 13 12 210
high-impedance
data out
76543210
25AA256/25LC256
FIGURE 2-2: BYTE WRITE SEQUENCE
CS
91011 2122232425262728293031
SCK
SI
SO
0 23456718
instruction 16-bit address data byte
0000000 1 15 14 13 12
high-impedance
FIGURE 2-3: PAGE WRITE SEQUENCE
CS
8
SCK
SI
CS
0 2345671
instruction 16-bit address data byte 1
0000000 1 15 14 13 12
Twc
21076543210
9 1011 2122232425262728293031
21076543210
SCK
SI
32 34 35 36 37 38 3933
data byte 2
76543210
41 42 43 46 47
40
data byte 3
76543210
44 45
data byte n (64 max)
76543210
DS21822C-page 8 Preliminary 2003 Microchip Technology Inc.
25AA256/25LC256
2.4 Write Enable (WREN) and Write
Disable (WRDI)
The 25XX256 contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation w ill be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)
CS
0 2345671
SCK
SI
SO
010000 01
high-impedance
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)
CS
0 2345671
SCK
SI
SO
010000 01
high-impedance
0
2003 Microchip Technology Inc. Preliminary DS 21822C-page 9
25AA256/25LC256
2.5 Read Status Register Instruction
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
TABLE 2-2: STATUS REGISTER
7 654 3 2 1 0
W/R –––W/RW/R R R
WPEN X X X BP1 BP0 WEL WIP
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25XX256 is busy with a write operation. When set to a
1’, a write is in progress, when set to a ‘0’, no write is
‘
in progress. This bit is read-only.
The Wri te Enable Lat ch (WEL) bit indicat es the st atus
of the write enabl e la tch and i s read -o nly. When set to
a ‘
1’, the latch allows writes to the array, when set to a
0’, the latch prohibits writes to the array. The state of
‘
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the Status register. These commands are shown in
Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
8
0 2345671
9101112131415
SCK
SO
SI
instruction
high-impedance
11000000
data from Status register
7654 2 10
3
DS21822C-page 10 Preliminary 2003 Microchip Technology Inc.
25AA256/25LC256
2.6 Write Status Register Instruction
See Figure 2-7 for the WRSR timing sequence.
(WRSR)
The Write S t atus Regis ter inst ruction (WRSR) all ows the
user to write to the n onvolatile bit s in t he S t atus reg ister
as shown in Table 2-2. The user is able to select one of
four levels of protection for the array by writing to the
appropriate bits in the Status register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bi t for the WP
Write-Protect (WP
(WPEN) bit in the Status register control the
programmable hardware write-protect feature. Hardware write protection is enabled when WP
and the WPEN bit is high. Hardware write protection is
disabled when either the WP
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the Status register are
disabled. See Table 2-4 for a matrix of functionality on
the WPEN bit.
) pin and the Write-Protect Enable
pin is high or the WPEN
pin. The
pin is low
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
TABLE 2-3: ARRAY PROTECTION
BP1 BP0
00
01
10
11
Array Addresses
Write-Protected
none
upper 1/4
(6000h - 7FFFh)
upper 1/2
(4000h - 7FFFh)
all
(0000h - 7FFFh)
CS
8
0 2345671
SCK
instruction data to Status register
SI
SO
Note: An internal write cy cle (T WC) is initiat ed on the rising edge o f CS after a valid write S tatus Registe r sequence.
01000000
high-impedance
9101112131415
7654
210
3
2003 Microchip Technology Inc. Preliminary DS21822C-page 11
25AA256/25LC256
2.7 Data Protection
The following protection has been implemented to
prevent in advertent writes to th e array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or Status register
write, the write enable latch is reset
must be set high after the proper number of
•CS
clock cycles to start an internal write cycle
• Access to the array dur ing an internal write cycle
is ignored and programming is continued
2.8 Power-On State
The 25XX256 powers on in the following state:
• The device is in low-power Standby mode
=1)
(CS
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS
enter active state
TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
0xxProtected Protected Protected
10xProtected Writable Writable
110 (low) Protected Writable Protected
111 (high) Protected Writable Writable
x = don’t care
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks Unprotected Blocks Status Register
is required to
DS21822C-page 12 Preliminary 2003 Microchip Technology Inc.
25AA256/25LC256
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Name Pin Number Function
CS
SO 2 Serial Data Output
WP
SS 4 Ground
V
SI 5 Serial Data Input
SCK 6 Serial Clock Input
HOLD
V
CC 8 Supply Voltage
3.1 Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardle ss of
input signal. If CS is brought high during a
the CS
program cycle, the de vice wil l go into S t andb y mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A lo w-to-high transiti on on CS
sequence initiates an internal write cycle. After powerup, a low level on CS
being initiated.
3.2 Serial Output (SO)
The SO pin is used to transfer data out of the 25XX256.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
1 Chip Select Input
3 Write-Protect Pin
7 Hold Input
after a valid write
is required p r ior to an y sequence
The WP
the St atus regi ster is low. This allo ws the use r to ins t al l
the 25XX256 in a system with WP pin grounded and
still be able to write to the Status register. The WP
functions will be enabled when the WPEN bit is set
high.
pin function is blocked when the WPEN bit in
pin
3.4 Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
3.5 Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX256. Instructions,
addresses or data pres en t on th e SI pin are latched on
the rising edge of t he c lo ck in put, while data on the SO
pin is updated after the falling edge of the clock input.
3.6 Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX256 while in the mid dle of a seri al sequ ence w ithout having to retransmit the entire sequence again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX256 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these p ins will be ignored. To
resume serial communication, HOLD
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
pin may be pulled
must be brought
3.3 Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the no nvolatil e bits in the Status register
is disabled. All other operations function normally.
When WP
nonvolatile bit s i n t he Status register, operate normally .
If the WPEN bit is set, WP low during a Status register
write sequence will disable writing to the Status
register. If an internal write cycle has already begun,
WP
2003 Microchip Technology Inc. Preliminary DS21822C-page 13
is high, all functions, including writes to the
going low will have no effect on the write.
25AA256/25LC256
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
8-Lead DFN
XXXXXXX
T/XXXXX
YYWW
NNN
8-Lead PDIP
XXXXXXXX
T/XXXNNN
YYWW
8-Lead SOIC
XXXXXXXX
T/XXYYWW
NNN
Example
25LC256
I/MF
0328
Example:
25AA256
I/P 1L7
Example:
25LC256
I/SN 0328
:
1L7
0328
1L7
8-Lead TSSOP
XXXX
TYWW
NNN
Legend: XX...X Part number
T Temperature (I, E)
Blank Commercial
YY Year code (last 2 digits of calendar year) except TSSOP
which uses only the last 1 digit
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: Custom marking available.
Example:
5LE
I328
1L7
TSSOP 1st Line Marking Codes
Device
25AA256
25LC256 5LE
std mark
5AE
Pb-free
mark
NAE
NLE
DS21822C-page 14 Preliminary 2003 Microchip Technology Inc.
25AA256/25LC256
8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S)
A1
n
12
TOP VIEW
α
E1
E
B
R
D1 D
EXPOSED
METAL
PADS
BOTTOM VIEW
A2
A3
A
p
L
D2
PIN 1
ID
E2
Units
Dimension Limits
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Base Thickness
Overall Length
Molded Package Length
Exposed Pad Length
Molded Package Width
Exposed Pad Width D2 .085 .091 .097 2.16 2.31 2.46
Lead Width
Lead Length
Tie Bar Width
Mold Draft Angle Top
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: pending
Drawing No. C04-113
n
p
A
A2
A1
A3
E
E1
E2
DOverall Width
D1
B
L
R
α
MIN
INCHES
NOM
.050 BSC
.033
.026
.000
.152 .158 .163 3.85 4.00 4.15
.014
.020
.0004
.008 REF.
.194 BSC
.184 BSC
.236 BSC
.226 BSC
.016
.024
.014
MAX MIN
8
.039
.031
.002
.019
.030
12
MILLIMETERS*
1.27 BSC
0.00
0.20 REF.
4.92 BSC
4.67 BSC
5.99 BSC
5.74 BSC
0.35
0.50
0.85
0.65
0.01
0.40
0.60
.356
MAXNOM
8
1.00
0.80
0.05
0.47
0.75
12
2003 Microchip Technology Inc. Preliminary DS21822C-page 15
25AA256/25LC256
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
E
β
eB
Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
Dimension Limits MIN NOM MAX MIN NOM MAX
1
α
A
c
Units INCHES* MILLIMETERS
n
p
c
α
β
.008 .012 .015 0.20 0.29 0.38
A1
B1
B
88
.100 2.54
51015 51015
51015 51015
A2
L
p
DS21822C-page 16 Preliminary 2003 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
25AA256/25LC256
B
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
n
45°
c
β
n
p
A1
φ
c
α
β
1
h
A
φ
L
048048
A1
MILLIMETERSINCHES*Units
1.27.050
α
A2
MAXNOMMINMAXNOMMINDimension Limits
88
1.751.551.35.069.061.053AOverall Height
1.551.421.32.061.056.052A2Molded Package Thickness
0.250.180.10.010.007.004
6.206.025.79.244.237.228EOverall Width
3.993.913.71.157.154.146E1Molded Package Width
5.004.904.80.197.193.189DOverall Length
0.510.380.25.020.015.010hChamfer Distance
0.760.620.48.030.025.019LFoot Length
0.250.230.20.010.009.008
0.510.420.33.020.017.013BLead Width
1512015120
1512015120
2003 Microchip Technology Inc. Preliminary DS21822C-page 17
25AA256/25LC256
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
n
B
1
A
c
A1
φ
β
A1
n
p
φ
c
α
β
048048
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickne ss
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
L
MILLIMETERS*INCHESUnits
0.65.026
α
A2
MAXNOMMINMAXNOMMINDimension Limits
88
1.10.043AOverall Height
0.950.900.85.037.035.033A2Molded Package Thickness
0.150.100.05.006.004.002
6.506.386.25.256.251.246EOverall Width
4.504.404.30.177.173.169E1Molded Package Width
3.103.002.90.122.118.114DMolded Package Length
0.700.600.50.028.024.020LFoot Length
0.200.150.09.008.006.004
0.300.250.19.012.010.007BLead Width
10501050
10501050
DS21822C-page 18 Preliminary 2003 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision C
Corrections to Section 1.0, Electrical Characteristics.
25AA256/25LC256
2003 Microchip Technology Inc. Preliminary DS21822C-page 19
25AA256/25LC256
NOTES:
DS21822C-page 20 Preliminary 2003 Microchip Technology Inc.
25AA256/25LC256
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used b y Mic rochip as a me ans to m ake
files and information easily available to customers. To
view the site, the use r must have access to the Intern et
and a web browser, such as Netscape
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web Site
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A
variety of Microchip specific business information is
also available, including listings of Microchip sales
offices, distr ibutors an d factory r epresentat ives. Other
data available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchi p Consultant P rogram Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for pr oducts, D evelopment Systems,
technical information and more
• Listing of seminars and events
®
or Microsoft
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
®
Plus, this line provides information on how customers
can receive the most c urrent upgra de kit s.The Hot Lin e
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
042003
2003 Microchip Technology Inc. Preliminary DS21822C-page 21
25AA256/25LC256
READER RESPONSE
It is our intentio n to pro vi de you with the best documentation possible to ens ure suc c es sfu l u se of y ou r M ic roc hip product. If you wish to provid e your c omment s on org anizatio n, clarity, subject matter , and ways in w hich o ur document atio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
RE: Reader Response
From:
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
Technical Publications Manager
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Total Pages Sent ________
FAX: (______) _________ - _________
DS21822C25AA256/25LC256
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21822C-page 22 Preliminary 2003 Microchip Technology Inc.
25AA256/25LC256
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X /XX X
Device
Device 25AA256
Tape & Reel Blank =
Temperature Range I =
Package M F =
25LC256
T=
E=
P=
SN =
ST =
256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM
256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM
Standard packaging (tube)
Tape & Reel
-40°C to+85°C
-40°C to+125°C
Micro Lead Frame (6 x 5 mm body), 8-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
TSSOP, 8-lead
X
–
Te mp Range
Lead PackageTape & Reel
Finish
Examples:
a) 25AA256-I/STG = 256k-bit, 1.8V Serial
EEPROM, Industrial temp., TSSOP package,
Pb-free
b) 25AA256T-I/SN = 256k-bit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel, SOIC
package
c) 25AA256T-I/ST = 256k-bit, 1.8V Serial
EEPROM, Industrial temp., Tape & Reel,
TSSOP package
d) 25LC256-I/STG = 256k-bit, 2.5V Serial
EEPROM, Industrial temp., TSSOP package,
Pb-free
e) 25LC256-I/P = 256k-bit, 2.5V Serial EEPROM,
Industrial temp., P-DIP package
f) 25LC256T-E/ST = 256k-bit, 2.5V Serial
EEPROM, Extended temp., Tape & Reel,
TSSOP package
Lead Finish Blank =
G=
Standard 63% / 37% Sn/Pb
Matte Tin (Pure Sn)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc. Preliminary DS21822C-page 23
25AA256/25LC256
NOTES:
DS21822C-page 24 Preliminary 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• Th ere are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the co de protection fea tures of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EELOQ, MPLAB, PIC, PICmic ro, PI C START,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PI CMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartT el and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
®
8-bit MCUs, KEELOQ
®
code hopping
2003 Microchip Technology Inc. Preliminary DS21822C-page 25
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-72 00
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640- 003 4
Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692- 384 8
Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285- 007 1
Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818- 742 3
Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538- 225 0
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864- 836 0
Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263- 188 8
Fax: 949-263-1338
Phoenix
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-79 66
Fax: 480-792-4338
San Jose
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436- 795 0
Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Cana da
Tel: 905-673- 069 9
Fax: 905-673-6509
ASIA/PACIFIC
Australia
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-986 8-6 73 3
Fax: 61-2-9868-6755
China - Beijing
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85 282 10 0
Fax: 86-10-85282104
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86 766 20 0
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7 503 50 6
Fax: 86-591-7503521
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401 -12 00
Fax: 852-2401-3431
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-62 75- 57 00
Fax: 86-21-6275-5060
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-8 290 13 80
Fax: 86-755-8295-1393
China - Shunde
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
India
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-47 1- 616 6 Fax: 81-4 5-4 71 -6122
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshir e, England RG41 5T U
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
DS21822C-page 26 Preliminary 2003 Microchip Technology Inc.
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