MICROCHIP 25AA160A, 25AA160B, 25LC160A, 25LC160B Technical data

25AA160A/B, 25LC160A/B

16K SPI™ Bus Serial EEPROM

Device Selection Table

Part Number VCC Range Page Size Temp. Ranges Packages

25LC160A 2.5-5.5V 16 Byte I,E P, SN, ST, MS

25AA160A 1.8-5.5V 16 Byte I P, SN, ST, MS

25LC160B 2.5-5.5V 32 Byte I,E P, SN, ST, MS

25AA160B 1.8-5.5V 32 Byte I P, SN, ST, MS

Features

• Max. clock 10 MHz

• Low-power CMOS technology

• 2048 x 8-bit organization

• 16 byte page (‘A’ version devices)

• 32 byte page (‘B’ version devices)

• Write cycle time: 5 ms max.

• Self-timed ERASE and WRITE cycles

• Block write protection

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential read

• High reliability

- Endurance: 1,000,000 erase/write cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• Temperature ranges supported;

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

Pin Function Table

Name Function

Description

The Microchip Technology Inc. 25AA160A/B, 25LC160A/B (25XX160A/B Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS

Communication to the device can be paused via the hold pin (HOLD

). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts.

The 25XX160A/B is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, and 8-lead TSSOP. Pb-free (Pure Matte Sn) finish is also available.

) are 16 Kbit Serial

) input.

Package Types (not to scale)

CS SO

PDIP/SOIC

(P, SN)

HOLD

SCK

TSSOP/MSOP

(ST, MS)

HOLD

SCK

Chip Select Input

SPI is a registered trademark of Motorola Semiconductor.

SO Serial Data Output

SS Ground

Write-Protect

SI Serial Data Input

SCK Serial Clock Input

HOLD

CC Supply Voltage

 2003 Microchip Technology Inc. DS21807B-page 1

Hold Input

*25XX160A/B is used in this document as a generic part number for the 25AA160A/B, 25LC160A/B devices.

25XX160A/B

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-65°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

D001 V

D002 V

D003 V

D004 V

D005 V

D006 V

D007 V

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input

IH2 0.7 VCC VCC +1 V VCC< 2.7V (Note)

IL1 Low-level input

IL2 -0.3 0.2 VCC VVCC < 2.7V (Note)

OL Low-level output

OL —0.2VIOL = 1.0 mA, VCC < 2.5V

OH High-level output

voltage

Industrial (I): T Automotive (E): T

2.0 VCC +1 V VCC ≥ 2.7V (Note)

-0.3 0.8 V VCC ≥ 2.7V (Note)

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH = -400 µA

voltage

D008 I

LI Input leakage current ±1 µACS = VCC, VIN = VSS TO VCC

D009 ILO Output leakage

current

D010 CINT Internal Capacitance

— 7 pF T (all inputs and outputs)

D011 I

CC Read

—

— Operating Current

D012 I

D013 I

CC Write — 3 mA VCC = 5.5V

CCS

Standby Current

—

Note: This parameter is periodically sampled and not 100% tested.

AMB = -40°C to +85°C VCC = 1.8V to 5.5V AMB = -40°C to +125°C VCC = 2.5V to 5.5V

±1 µACS = VCC, VOUT = VSS TO VCC

AMB = 25°C, CLK = 1.0 MHz,

CC = 5.0V (Note)

mAmAVCC = 5.5V; FCLK = 10.0 MHz;

SO = Open

2.5

CC = 2.5V; FCLK = 5.0 MHz;

SO = Open

µAµACS

V CS V

= VCC = 5.5V, Inputs tied to VCC or

SS, TAMB = -40°C TO +125°C

= VCC = 2.5V, Inputs tied to VCC or

SS, TAMB = -40°C TO +85°C

DS21807B-page 2  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

25XX160A/B

AC CHARACTERISTICS

Param.

No.

Sym. Characteristic Min. Max. Units Test Conditions

CLK Clock Frequency —

Industrial (I): T Automotive (E): T

— —

CSS CS Setup Time 50

100 150

CSH CS Hold Time 100

200 250

CSD CS Disable Time 50 — ns —

5 Tsu Data Setup Time 10

20 30

HD Data Hold Time 20

40 50

R CLK Rise Time — 500 ns (Note 1)

F CLK Fall Time — 500 ns (Note 1)

HI Clock High Time 50

100 150

10 T

LO Clock Low Time 50

100 150

11 T

12 T

13 T

CLD Clock Delay Time 50 — ns —

CLE Clock Enable Time 50 — ns —

V Output Valid from Clock

Low

— — —

14 T

15 T

HO Output Hold Time 0 — ns (Note 1)

DIS Output Disable Time —

— —

16 T

HS HOLD Setup Time 20

40 80

AMB = -40°C to +85°C VCC = 1.8V to 5.5V AMB = -40°C to +125°C VCC = 2.5V to 5.5V

5 3

— — —

50 100 160

80 160

—

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.

WC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is

3: T

complete.

MHz MHz MHz

ns ns ns

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

CC ≤ 5.5V CC < 4.5V CC < 2.5V

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

CC ≤ 5.5V CC < 4.5V CC < 2.5V

CC ≤ 5.5V (Note 1) CC ≤ 4.5V (Note 1) CC ≤ 2.5V (Note 1)

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

 2003 Microchip Technology Inc. DS21807B-page 3

25XX160A/B

TABLE 1-2: AC CHARACTERISTICS (CONTINUED)

Industrial (I): T Automotive (E): T

Param.

No.

AC CHARACTERISTICS

Sym. Characteristic Min. Max. Units Test Conditions

17 THH HOLD Hold Time 20

40 80

18 T

HZ HOLD Low to Output

High-Z

30 60

160

19 T

HV HOLD High to Output

Val id

30 60

160

20 T

WC Internal Write Cycle Time — 5 ms (NOTE 3)

AMB = -40°C to +85°C VCC = 1.8V to 5.5V AMB = -40°C to +125°C VCC = 2.5V to 5.5V

— — —

ns ns ns

21 — Endurance 1M — E/W

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com.

WC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is

3: T

complete.

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

4.5V ≤ V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

CC ≤ 5.5V (Note 1) CC < 4.5V (Note 1) CC < 2.5V (Note 1)

4.5V ≤ VCC ≤ 5.5V

2.5V ≤ V

1.8V ≤ V

CC < 4.5V CC < 2.5V

OTE 2)

TABLE 1-3: AC TEST CONDITIONS

AC Waveform:

LO = 0.2V —

HI = VCC - 0.2V (Note 1)

HI = 4.0V (Note 2)

Timing Measurement Reference Level

Input 0.5 V

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V

CC > 4.0V

DS21807B-page 4  2003 Microchip Technology Inc.

FIGURE 1-1: HOLD TIMING

SCK

n+2 n+1 n n-1

high-impedance

25XX160A/B

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

Mode 1,1

Mode 0,0

SCK

MSB in

high-impedance

don’t care

LSB in

n-1

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

 2003 Microchip Technology Inc. DS21807B-page 5

MSB out

don’t care

Mode 1,1

Mode 0,0

ISB out

25XX160A/B

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 25XX160A/B are 2048 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PICmicro microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software.

The 25XX160A/B contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS be low and the HOLD operation.

Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last.

Data (SI) is sampled on the first rising edge of SCK after CS peripheral devices on the SPI bus, the user can assert the HOLD mode. After releasing the HOLD resume from the point when the HOLD

2.2 Read Sequence

The device is selected by pulling CS low. The 8-bit read instruction is transmitted to the 25XX160A/B followed by the 16-bit address, with the five MSBs of the address being don’t care bits. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (07FFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS

microcontrollers. It may also interface with

pin must

pin must be high for the entire

goes low. If the clock line is shared with other

input and place the 25XX160A/B in ‘HOLD’

pin, operation will

was asserted.

pin (Figure 2-1).

2.3 Write Sequence

Prior to any attempt to write data to the 25XX160A/B, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS and then clocking out the proper instruction into the 25XX160A/B. After all eight bits of the instruction are transmitted, the CS write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set.

Once the write enable latch is set, the user may proceed by setting the CS instruction, followed by the 16-bit address, with the five MSBs of the address being don’t care bits, and then the data to be written. Up to 16 bytes (25XX160A) or 32 bytes (25XX160B) of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page.

Note: Page write operations are limited to writing

bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are integer multiples of page size - 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.

For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the n brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status Register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.

data byte has been clocked in. If CS is

must be brought high to set the

low, issuing a WRITE

low

DS21807B-page 6  2003 Microchip Technology Inc.

Block Diagram

25XX160A/B

SCK

HOLD

I/O Control

Status

Logic

Memory

Control

Logic

VCC VSS

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp. R/W Control

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ

WRITE

WRDI WREN RDSR WRSR

0000 0011 0000 0010 0000 0100 0000 0110 0000 0101 0000 0001

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Reset the write enable latch (disable write operations)

Set the write enable latch (enable write operations)

Read Status Register

Write Status Register

FIGURE 2-1: READ SEQUENCE

0 2 3 4 5 6 7 8 910 11 21222324252627282930311

SCK

instruction 16-bit address

 2003 Microchip Technology Inc. DS21807B-page 7

0100000 1 15 14 13 12 210

high-impedance

data out

76543210

25XX160A/B

FIGURE 2-2: BYTE WRITE SEQUENCE

9 1011 2122232425262728293031

SCK

0 2345671

instruction 16-bit address data byte

0000000 1 15 14 13 12

high-impedance

FIGURE 2-3: PAGE WRITE SEQUENCE

SCK

0 2345671

instruction 16-bit address data byte 1

0000000 1 15 14 13 12

Twc

21076543210

9 1011 2122232425262728293031

21076543210

SCK

32 34 35 36 37 38 3933

data byte 2

76543210

41 42 43 46 47

data byte 3

76543210

44 45

data byte n (16/32 max)

76543210

DS21807B-page 8  2003 Microchip Technology Inc.

+ 16 hidden pages