MICROCHIP 25AA1024, 25LC1024 Technical data

25AA1024/25LC1024

1 Mbit SPI™ Bus Serial Flash

Device Selection Table

Part Number VCC Range Page Size Temp. Ranges Packages

25LC1024 2.5-5.5V 256 Byte I,E P, SM, MF

25AA1024 1.8-5.5V 256 Byte I P, SM, MF

Features

• Max. clock 20 MHz

• Flash and byte-level serial EEPROM operation

• Low-power CMOS technology

- Max. Write Current: 5 mA at 5.5V, 20 MHz

- Read Current: 10 mA at 5.5V, 20 MHz

- Standby Current: 1µA at 5.5V (Deep powerdown)

• 131,072 x 8-bit organization

• Byte and Page (256 byte page) Write Operations (5 ms max.)

• Electronic Signature for device ID

• Self-timed ERASE and WRITE cycles

- Sector Erase (1 second/sector typical)

- Bulk Erase (2 seconds typical)

• Sector write protection (32K byte/sector)

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• High reliability

- Endurance: 100,000 erase/write cycles

• Temperature ranges supported;

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°C to +125°C

• Standard and Pb-free packages available

Pin Function Table

Name Function

Description

The Microchip Technology Inc. 25AA1024/25LC1024 (25XX1024 Flash memory with both Flash and byte-level serial EEPROM functions. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled by a Chip Select (CS input.

Communication to the device can be paused via the hold pin (HOLD tions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts.

The 25XX1024 is available in standard packages including 8-lead PDIP and SOIC, and advanced 8-lead DFN package. Pb-free (Pure Sn) finish is also available.

) is a 1024 Kbit serial reprogrammable

). While the device is paused, transi-

Package Types (not to scale)

VSS

DFN

(MF)

25LC1024

VCC

HOLD

SCK

PDIP/SOIC

(P, SM)

1 2

25LC1024

8 7

HOLD

SCK

)

Chip Select Input

SPI is a registered trademark of Motorola Semiconductor.

SO Serial Data Output

SS Ground

Write-Protect

SI Serial Data Input

SCK Serial Clock Input

HOLD

CC Supply Voltage

 2003 Microchip Technology Inc. Preliminary DS21836A-page 1

Hold Input

*25XX1024 is used in this document as a generic part number for the 25AA1024, 25LC1024 devices.

25AA1024/25LC1024

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

D001 V

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input

Industrial (I): T Automotive (E): T

.7 VCC VCC +1 V

voltage

D002 V

D003 V

D004 V

D005 V

D006 V

IL1 Low-level input

IL2 -0.3 0.2 VCC VVCC < 2.7V

OL Low-level output

OL —0.2VIOL = 1.0 mA, VCC < 2.5V

OH High-level output

voltage

-0.3 0.3 VCC VVCC ≥ 2.7V

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH = -400 µA

voltage

D007 I

LI Input leakage current ±1 µACS = VCC, VIN = VSS TO VCC

D008 ILO Output leakage

current

D009 CINT Internal capacitance

— 7 pF TA = 25°C, CLK = 1.0 MHz, (all inputs and outputs)

D010 I

CC Read

—

— Operating current

D011 I

CC Write —

—

D012 I

D13 I

CCS

Standby current

CCSPD Deep power-down

—

—1µACS = VCC = 5.5V, Inputs tied to VCC or current

Note: This parameter is periodically sampled and not 100% tested.

A = -40°C to +85°C VCC = 1.8V to 5.5V A = -40°C to +125°C VCC = 2.5V to 5.5V

±1 µACS = VCC, VOUT = VSS TO VCC

CC = 5.0V (Note)

mAmAVCC = 5.5V; FCLK = 20.0 MHz;

SO = Open

VCC = 2.5V; FCLK = 10.0 MHz; SO = Open

5 3

mAmAVCC = 5.5V

CC = 2.5V

µAµACS

= VCC = 5.5V, Inputs tied to VCC or

SS, 125°C

= VCC = 5.5V, Inputs tied to VCC or

SS, 85°C

DS21836A-page 2 Preliminary  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

25AA1024/25LC1024

Industrial (I): T Automotive (E): T

A = -40°C to +85°C VCC = 1.8V TO 5.5V A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No.

5 Tsu Data setup time 5

10 T

Sym Characteristic Min Max Units Conditions

CLK Clock frequency —

— —

CSS CS setup time 25

250

CSH CS hold time 50

100 500

CSD CS disable time 50 — ns

20 10

— — —

— 10 50

HD Data hold time 10

100

R CLK rise time — 20 ns (Note 1)

F CLK fall time — 20 ns (Note 1)

Clock high time 25

250

LO Clock low time 25

—

250

11 T

12 T

13 T

14 T

15 T

16 T

17 T

CLD Clock delay time 50 — ns

CLE Clock enable time 50 — ns

V Output valid from clock

low

HO Output hold time 0 — ns (Note 1)

DIS Output disable time —

HS HOLD setup time 10

HH HOLD hold time 10

— — —

— —

100

25 50

250

25 50

250

—

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance estimates

in a specific application, please consult the Total Endurance™ Model which can be obtained from our web site.

3: Includes T

HI time.

MHz MHz MHz

ns ns ns

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

1.8 ≤ V

CC < 2.5

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V (Note 3)

CC ≤ 5.5

4.5 ≤ V

2.5 ≤ V

CC < 4.5 CC < 2.5

1.8 ≤ V

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.8 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

CC < 4.5

2.5 ≤ V

1.8 ≤ V

CC < 2.5

(Note 1)

CC ≤ 5.5

4.5 ≤ V

CC < 4.5

2.5 ≤ V

CC < 2.5

1.8 ≤ V

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V

CC < 4.5 CC < 2.5

1.8 ≤ V

 2003 Microchip Technology Inc. Preliminary DS21836A-page 3

25AA1024/25LC1024

TABLE 1-2: (CONTINUED) AC CHARACTERISTICS

AC CHARACTERISTICS

Industrial (I): T Automotive (E): T

A = -40°C to +85°C VCC = 1.8V TO 5.5V A = -40°C to +125°C VCC = 2.5V to 5.5V

Param.

No.

18 Thz HOLD low to output

Sym Characteristic Min Max Units Conditions

High-Z

15 30

150

— — —

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V

1.8 ≤ V

CC < 4.5 CC < 2.5

(Note 1)

19 Thv HOLD

20 Trel CS

21 Tpd CS

High to Standby mode — 1.6 µsVCC = 1.8V to 5.5V

High to Deep power-

high to output valid 15

150

—1.6µsVCC = 1.8V to 5.5V

— — —

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V

1.8 ≤ V

CC < 4.5 CC < 2.5

down

22 Tce Chip erase cycle time — 4 s V

23 Tse Sector erase cycle time — 2 s V

CC = 1.8V to 5.5V

24 Twc Internal write cycle time — 5 ms Byte or Page mode

25 — Endurance 100K — E/W

(Note 2)

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance estimates

in a specific application, please consult the Total Endurance™ Model which can be obtained from our web site.

3: Includes T

HI time.

TABLE 1-3: AC TEST CONDITIONS

AC Waveform:

LO = 0.2V —

HI = VCC - 0.2V (Note 1)

HI = 4.0V (Note 2)

L = 100 pF —

Timing Measurement Reference Level

Input 0.5 V

Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V

CC > 4.0V

DS21836A-page 4 Preliminary  2003 Microchip Technology Inc.

FIGURE 1-1: HOLD TIMING

SCK

n+2 n+1 n n-1

25AA1024/25LC1024

high-impedance

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

Mode 1,1

Mode 0,0

SCK

MSB in

high-impedance

don’t care

LSB in

n-1

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

 2003 Microchip Technology Inc. Preliminary DS21836A-page 5

MSB out

don’t care

Mode 1,1

Mode 0,0

LSB out

25AA1024/25LC1024

2.0 FUNCTIONAL DESCRIPTION

2.1 Principles of Operation

The 25XX1024 is a 131,072 byte Serial Flash designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PICMicro lers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol.

The 25XX1024 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS be low and the HOLD operation.

Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last.

Data (SI) is sampled on the first rising edge of SCK after CS peripheral devices on the SPI bus, the user can assert the HOLD mode. After releasing the HOLD resume from the point when the HOLD

goes low. If the clock line is shared with other

input and place the 25XX1024 in ‘HOLD’

pin must be high for the entire

microcontrol-

pin must

pin, operation will

was asserted.

2.2 Read Sequence

The device is selected by pulling CS low. The 8-bit read instruction is transmitted to the 25XX1024 followed by the 24-bit address, with seven MSBs of the address being don’t care bits. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFFh), the address counter rolls over to address 00000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS

pin (Figure 2-1).

2.3 Write Sequence

Prior to any attempt to write data to the 25XX1024, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX1024. After all eight bits of the instruction are transmitted, the CS write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set.

Once the write enable latch is set, the user may proceed by setting the CS tion, followed by the 24-bit address, with seven MSBs of the address being don’t care bits, and then the data to be written. Up to 256 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page.

Note: Page write operations are limited to writing

bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’), and end at addresses that are integer multiples of page size - 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.

For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the n brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status Register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.

data byte has been clocked in. If CS is

must be brought high to set the

low, issuing a WRITE instruc-

DS21836A-page 6 Preliminary  2003 Microchip Technology Inc.

BLOCK DIAGRAM

25AA1024/25LC1024

SCK

HOLD

Status

I/O Control

Logic

VCC VSS

Memory

Control

Logic

Dec

HV Generator

EEPROM

Array

Page Latches

Y Decoder

Sense Amp. R/W Control

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address

WRITE 0000 0010 Write data to memory array beginning at selected address

WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register

PE 0100 0010 Page Erase - erase one page in memory array SE 1101 1000 Sector Erase - erase one sector in memory array CE 1100 0111 Chip Erase - erase all sectors in memory array

RDID 1010 1011 Release from Deep power-down and read electronic signature

DPD 1011 1001 Deep Power-down mode

FIGURE 2-1: READ SEQUENCE

0 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 391

SCK

instruction 24 Bit Address

 2003 Microchip Technology Inc. Preliminary DS21836A-page 7

0100000 1 23 22 21 20 210

high-impedance

Data Out

76543210

25AA1024/25LC1024

FIGURE 2-2: BYTE WRITE SEQUENCE

9 1011 2930313233343536373839

SCK

0 2345671

instruction 24-bit address data byte

0000000 1 23 22 21 20

high-impedance

FIGURE 2-3: PAGE WRITE SEQUENCE

9 1011 2930313233343536373839

SCK

0 2345671

instruction 24-bit address data byte 1

0000000 1 23 22 21 20

Twc

21076543210

SCK

40 42 43 44 45 46 4741

data byte 2

76543210

49 50 51 54 55

76543210

52 53

data byte 3

data byte n (256 max)

76543210

DS21836A-page 8 Preliminary  2003 Microchip Technology Inc.

25AA1024/25LC1024

2.4 Write Enable (WREN) and Write Disable (WRDI)

The 25XX1024 contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch.

FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN)

0 2345671

SCK

010000 01

high-impedance

The following is a list of conditions under which the write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI)

02345671

SCK

010000 01

high-impedance

 2003 Microchip Technology Inc. Preliminary DS21836A-page 9

+ 19 hidden pages