MICROCHIP 25AA080, 25LC080, 25C080 Technical data

Not recommended for new designs – Please use 25AA080A/B or 25LC080A/B.

25AA080/25LC080/25C080

8K SPI™ Bus Serial EEPROM

Device Selection Table

Part

Number

25AA080 1.8-5.5V 1 MHz I 25LC080 2.5-5.5V 2 MHz I 25C080 4.5-5.5V 3 MHz I,E

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

Features:

• Low-power CMOS technology:

- Write current: 3 mA maximum

- Read current: 500 µA typical

- Standby current: 500 nA typical

• 1024 x 8-bit organization

• 16 byte page

• Write cycle time: 5 ms max.

• Self-timed erase and write cycles

• Block write protection:

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential read

• High reliability:

- Endurance: 1 M cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• 8-pin PDIP and SOIC (150 mil)

• Temperature ranges supported:

- Industrial (I): -40°Cto +85°C

- Automotive (E) (25C080): -40°C to +125°C

Description:

The Microchip Technology Inc. 25AA080/25LC080/ 25C080 (25XX080 Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is co ntrolled throu gh a Chip Select (CS

Communication to the device can be paused via the hold pin (HOLD tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts.

) are 8 Kbit Serial Electrically

) input.

). While the device is paused, transi-

Package Types

PDIP/SOIC

CS SO

VSS

1 2

3 4

8 7

6 5

VCC HOLD

SCK SI

25AA080/

Block Diagram

Status

I/O Control

Logic

Memory

Control

Logic

Dec

HV Generato r

EEPROM

Array

Page Latches

SO CS

SCK

HOLD

*25XX080 is used in th is docum ent as a gen eric part numb er for the 25AA080/25LC080/25C080 devices.

SPI™ is a trademark of Motorola Inc.

 2004 Microchip Technology Inc. DS21230D-page 1

VCC

VSS

Y Decoder

Sense Amp. R/W Control

25AA080/25LC080/25C080

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ........................................................................................................ -0.6V to VCC + 1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

Soldering temperature of leads (10 seconds).......................................................................................................+300°C

ESD protection on all pins.........................................................................................................................................4KV

† NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This is a stress rating only a nd fu nc tional operation of the device at tho se or an y other conditions above those indi cated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of t i me may affect device reliability.

1.1 DC Characteristics

DC CHARACTERISTICS

Param.

No.

D001 V D002 V

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input IH2 0.7 VCC VCC+1 V VCC< 2.7V (Note)

voltage

D003 VIL1 Low-level input D004 VIL2-0.30.3 VCC VVCC < 2.7V (Note) D005 V

OL Low-level output

D006 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V

voltage

D007 VOH High-level output

voltage

D008 I

LI Input leakage current -10 10 µACS = VCC, VIN = VSS TO VCC

D009 ILO Output leakage

current

D010 CINT Internal Capacitance

(all inputs and outputs)

D011 I

CC Read

Operating Current

D012 I

CC Write —

D013 ICCS

Standby Current

Note: This parameter is periodically sampled and not 100% tested.

Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E):T

A = -40°C to +125°C VCC = 4.5V to 5.5V (25C080 onl y)

2.0 VCC+1 V VCC ≥ 2.7V (Note)

-0.3 0.8 V VCC ≥ 2.7V (Note)

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH = -400 µA

-10 10 µACS = VCC, VOUT = VSS TO VCC

—7pFTA = 25°C, CLK = 1.0 MHz,

CC = 5.0V (Note)

— —

500

mAµAVCC = 5.5V; FCLK = 3.0MHz;

SO = Open VCC = 2.5V; FCLK = 2.0 MHz; SO = Open

— —

—

5 3

5 1

mAmAVCC = 5.5V

CC = 2.5V

µAµACS

= VCC = 5.5V, Inputs tied to VCC or

V CS = VCC = 2.5V, Inputs tied to VCC or

DS21230D-page 2  2004 Microchip Technology Inc.

1.2 AC Characteristics

25AA080/25LC080/25C080

AC CHARACTERISTICS

Param.

No.

Sym. Characteristic Min. Max. Units Test Conditions

CLK Clock Frequency —

CSS CS Setup Time 100

CSH CS Hold Time 150

CSD CS Disable Time 500 — ns —

4T 5 Tsu Data Setup Time 30

HD Data Hold Time 50

R CLK Rise Time — 2 µs (Note 1)

F CLK Fall Time — 2 µs (Note 1)

HI Clock High Time 150

10 T

11 T 12 T 13 T

14 T 15 T

16 T

17 T

18 T

19 T

20 T

LO Clock Low Time 150

CLD Clock Delay Time 50 — ns — CLE Clock Enable Time 50 — ns —

V Output Valid from Clock Low —

HO Output Hold Time 0 — ns (Note 1) DIS Output Disable Time —

HS HOLD Setup Time 100

HH HOLD Hold Time 100

HZ HOLD Low to Output High-Z 100

HV HOLD High to Output Valid 100

WC Internal Write Cycle Time — 5 ms —

Industrial (I): T Automotive (E): T

— —

250 500

250 475

50 50

100 100

230 475

— —

100 200

150 200

A = -40°C to +85°C VCC = 1.8V to 5.5V A = -40°C to +125°C VCC = 4.5V to 5.5V (25C080 only)

3 2 1

— — —

150 230 475

200 250 500

— — —

21 — Endurance 1M — E/W

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please

consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.

MHz MHz MHz

ns ns ns

Cycles

VCC = 4.5V to 5.5V V

CC = 2.5V to 4.5V CC = 1.8V to 2.5V

V VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V CC = 1.8V to 2.5V

V VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V CC = 1.8V to 2.5V

CC = 4.5V to 5.5V CC = 2.5V to 4.5V

CC = 1.8V to 2.5V

V VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

CC = 1.8V to 2.5V

VCC = 4.5V to 5.5V V

CC = 2.5V to 4.5V CC = 1.8V to 2.5V

V VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V CC = 1.8V to 2.5V

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V V

CC = 1.8V to 2.5V

VCC = 4.5V to 5.5V (Note 1) V

CC = 2.5V to 4.5V (Note 1) CC = 1.8V to 2.5V (Note 1)

V VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V CC = 1.8V to 2.5V

V VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V CC = 1.8V to 2.5V

V VCC = 4.5V to 5.5V (Note 1)

CC = 2.5V to 4.5V (Note 1) CC = 1.8V to 2.5V (Note 1)

V VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

CC = 1.8V to 2.5V

(Note 2)

 2004 Microchip Technology Inc. DS21230D-page 3

25AA080/25LC080/25C080

FIGURE 1-1: HOLD TIMING

High-impedance

SCK

n+2 n+1 n n-1

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

SCK

2 Mode 1,1 Mode 0,0

MSB in

High-impedance

don’t care

LSB in

n-1

FIGURE 1-3: SERIAL OUTPUT TIMING

SCK

DS21230D-page 4  2004 Microchip Technology Inc.

MSB out

don’t care

Mode 1,1 Mode 0,0

ISB out

25AA080/25LC080/25C080

1.3 AC Test Conditions

AC Waveform:

VLO = 0.2V —

HI = VCC - 0.2V (Note 1)

V VHI = 4.0V (Note 2)

Timing Measurement Reference Lev el

Input 0.5 V Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V

CC > 4.0V

FIGURE 1-4: AC TEST CIRCUIT

VCC

2.25 KΩ

1.8 KΩ

100 pF

 2004 Microchip Technology Inc. DS21230D-page 5

25AA080/25LC080/25C080

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP SOIC Function

CS SO 2 2 Serial Data Output

WP Vss 4 4 Ground

SI 5 5 Serial Data Input

SCK 6 6 Serial Clock Input

HOLD

Vcc 8 8 Supply Voltage

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardle ss of the CS input signal. If CS is brought high during a program cycle, the de vice wil l go into S t andb y mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A lo w-to-high transiti on on CS sequence initiates an internal write cycle. After powerup, a low level on CS is r equ ired p r ior to any sequence being initiated.

1 1 Chip Select Input

3 3 Write-Protect Pin

7 7 Hold Input

after a valid write

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication between a master and the 25XX080. Instructions, addresses or data pres en t on th e SI pin are latched on the rising edge of t he c lo ck input, while data on the SO pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the 25XX080 while in the middle of a serial sequence without having to retra nsmit the e ntire sequ ence agai n. It must be held hi gh an y tim e this f unct ion is not be ing used. Once the device is selected and a serial sequence is underway, the HOLD low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25XX080 must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these p ins will be ignored. To resume serial communication, HOLD high while the SCK p in is lo w, otherwise seria l com munication will not resum e. Lowering the HOLD lin e at any time will tri-state the SO line.

pin may be pulled

must be brought

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX080. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.

2.3 Write-Protec t (WP)

This pin is used in conjunction with the WPEN bit in the Status register to prohibit writes to the nonvolatile bits in the Status register. When WP is low and WPEN is high, writing to the no nvolatil e bits in the Status register is disabled. All other operations function normally. When WP nonvolatile bits in the Status register operate normally. If the WPEN bit is set, WP write sequence will disable writing to the Status register. If an internal write cycle has already begun, WP

The WP the Status register is low. This allows the user to install the 25XX080 in a system with WP still be able to write to the Status register. The WP functions will be enabled when the WPEN bit is set high.

is high, all functions, including writes to the

low during a Status register

going low will have no effect on the write.

pin function is blocked when the WPEN bit in

pin grounded and

DS21230D-page 6  2004 Microchip Technology Inc.

25AA080/25LC080/25C080

3.0 FUNCTIONAL DESCRIPTION

3.1 Principles of Operation

The 25XX080 are 1024 byte Serial EEPROMs designed to interf ace di rec tly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software.

The 25XX080 conta ins an 8-bit instr uction regi ster . The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS be low and the HOLD operation. The WP writing to the memory array.

Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last.

Data is sampled on the fir st rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and pl ace the 25X X080 in ‘HO LD’ mode. After releasing the HOLD from the point when the HOLD

pin must be high fo r the entire

pin must be held high to allow

pin, operation will resume

was asserted.

3.2 Read Sequence

The devic e is selected by pulling CS low. The 8-bit READ instruction is transmitted t o the 25XX080 followed by the 16-bit address, with the six MSBs of the address being "don’t care" bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address i s shifted o ut on the SO pin. The data stored in the memory a t the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address af ter each byte of data is shifted out. When the highest address is reached (03FFh), the address counter rolls over to address 0000h allowing the read cycle t o be continued indefinitely. The read operation is terminated b y raising the

pin (Figure 3-1).

TABLE 3-1: INSTRUCTION SET

pin must

3.3 Write Sequence

Prior to any attempt to write data to the 25XX080, the write enable latch must be set by issuing the WREN instruction (Figure3-4). This is done by setting CS and then clocking out the proper instruction into the 25XX080. After all eight bi ts of the in struction are transmitted, the CS enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set.

Once the write enable latch is set, the user may proceed by setting the C S tion, followed by the 16-bit address, with the six MSBs of the address being “do n’t care” bi ts, and the n the data to be written. Up to 16 bytes of data can be sent to the 25XX080 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A pa ge ad dress b egins with

0000 and ends with xxxx xxxx xxxx 1111.

xxxx

If the internal address counter reaches

xxxx

1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written.

For the data to be actually written to the array, the CS must be brought high after the Leas t Significant bit (D0) of the n brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.

must be brought high to set the write

low, issuing a WRITE instruc-

xxxx xxxx

data byte has been clocked in. If CS is

low

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read Status register WRSR 0000 0001 Write Status register

 2004 Microchip Technology Inc. DS21230D-page 7

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