MICROCHIP 25AA080, 25LC080, 25C080 Technical data

Not recommended for new designs –
Please use 25AA080A/B or 25LC080A/B.

25AA080/25LC080/25C080

8K SPI™ Bus Serial EEPROM

Device Selection Table

Part

Number

25AA080 1.8-5.5V 1 MHz I
25LC080 2.5-5.5V 2 MHz I
25C080 4.5-5.5V 3 MHz I,E

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

Features:

• Low-power CMOS technology:

- Write current: 3 mA maximum

- Read current: 500 µA typical

- Standby current: 500 nA typical

• 1024 x 8-bit organization

• 16 byte page

• Write cycle time: 5 ms max.

• Self-timed erase and write cycles

• Block write protection:

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection:

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

• Sequential read

• High reliability:

- Endurance: 1 M cycles

- Data retention: > 200 years

- ESD protection: > 4000V

• 8-pin PDIP and SOIC (150 mil)

• Temperature ranges supported:

- Industrial (I): -40°Cto +85°C

- Automotive (E) (25C080): -40°C to +125°C

Description:

The Microchip Technology Inc. 25AA080/25LC080/
25C080 (25XX080
Erasable PROMs. The memory is accessed via a
simple Serial Peripheral Interface™ (SPI™) compati­ble serial bus. The bus signals required are a clock
input (SCK) plus separate data in (SI) and data out
(SO) lines. Access to the device is co ntrolled throu gh a
Chip Select (CS

Communication to the device can be paused via the
hold pin (HOLD
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts.

*

) are 8 Kbit Serial Electrically

) input.

). While the device is paused, transi-

Package Types

PDIP/SOIC

CS
SO

WP

VSS

1
2

3
4

8
7

6
5

VCC
HOLD

SCK
SI

25AA080/

Block Diagram

Status

Register

I/O Control

Logic

Memory

Control

Logic

X

Dec

HV Generato r

EEPROM

Array

Page Latches

SI

SO
CS

SCK

HOLD

WP

*25XX080 is used in th is docum ent as a gen eric part numb er for the
25AA080/25LC080/25C080 devices.

SPI™ is a trademark of Motorola Inc.

 2004 Microchip Technology Inc. DS21230D-page 1

VCC

VSS

Y Decoder

Sense Amp.
R/W Control

25AA080/25LC080/25C080

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS ........................................................................................................ -0.6V to VCC + 1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

Soldering temperature of leads (10 seconds).......................................................................................................+300°C

ESD protection on all pins.........................................................................................................................................4KV

† NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This
is a stress rating only a nd fu nc tional operation of the device at tho se or an y other conditions above those indi cated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended
period of t i me may affect device reliability.

1.1 DC Characteristics

DC CHARACTERISTICS

Param.

No.

D001 V
D002 V

Sym. Characteristic Min. Max. Units Test Conditions

IH1 High-level input
IH2 0.7 VCC VCC+1 V VCC< 2.7V (Note)

voltage

D003 VIL1 Low-level input
D004 VIL2-0.30.3 VCC VVCC < 2.7V (Note)
D005 V

OL Low-level output

D006 VOL —0.2VIOL = 1.0 mA, VCC < 2.5V

voltage

voltage

D007 VOH High-level output

voltage

D008 I

LI Input leakage current -10 10 µACS = VCC, VIN = VSS TO VCC

D009 ILO Output leakage

current

D010 CINT Internal Capacitance

(all inputs and
outputs)

D011 I

CC Read

Operating Current

D012 I

CC Write —

D013 ICCS

Standby Current

Note: This parameter is periodically sampled and not 100% tested.

Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V
Automotive (E):T

A = -40°C to +125°C VCC = 4.5V to 5.5V (25C080 onl y)

2.0 VCC+1 V VCC ≥ 2.7V (Note)

-0.3 0.8 V VCC ≥ 2.7V (Note)

—0.4VIOL = 2.1 mA

VCC -0.5 — V IOH = -400 µA

-10 10 µACS = VCC, VOUT = VSS TO VCC

—7pFTA = 25°C, CLK = 1.0 MHz,

CC = 5.0V (Note)

V

—
—

1

500

mAµAVCC = 5.5V; FCLK = 3.0MHz;

SO = Open
VCC = 2.5V; FCLK = 2.0 MHz;
SO = Open

—
—

—

5
3

5
1

mAmAVCC = 5.5V

V

CC = 2.5V

µAµACS

= VCC = 5.5V, Inputs tied to VCC or

SS

V
CS = VCC = 2.5V, Inputs tied to VCC or

SS

V

DS21230D-page 2  2004 Microchip Technology Inc.

1.2 AC Characteristics

25AA080/25LC080/25C080

AC CHARACTERISTICS

Param.

No.

Sym. Characteristic Min. Max. Units Test Conditions

CLK Clock Frequency —

1F

CSS CS Setup Time 100

2T

CSH CS Hold Time 150

3T

CSD CS Disable Time 500 — ns —

4T
5 Tsu Data Setup Time 30

6T

HD Data Hold Time 50

7T

R CLK Rise Time — 2 µs (Note 1)

F CLK Fall Time — 2 µs (Note 1)

8T

HI Clock High Time 150

9T

10 T

11 T
12 T
13 T

14 T
15 T

16 T

17 T

18 T

19 T

20 T

LO Clock Low Time 150

CLD Clock Delay Time 50 — ns —
CLE Clock Enable Time 50 — ns —

V Output Valid from Clock Low —

HO Output Hold Time 0 — ns (Note 1)
DIS Output Disable Time —

HS HOLD Setup Time 100

HH HOLD Hold Time 100

HZ HOLD Low to Output High-Z 100

HV HOLD High to Output Valid 100

WC Internal Write Cycle Time — 5 ms —

Industrial (I): T
Automotive (E): T

—
—

250
500

250
475

50
50

100
100

230
475

230
475

—
—

—
—

100
200

100
200

150
200

150
200

A = -40°C to +85°C VCC = 1.8V to 5.5V
A = -40°C to +125°C VCC = 4.5V to 5.5V (25C080 only)

3
2
1

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

150
230
475

200
250
500

—
—
—

—
—
—

—
—
—

—
—
—

21 — Endurance 1M — E/W

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please

consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.

MHz
MHz
MHz

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

Cycles

VCC = 4.5V to 5.5V
V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V

V

CC = 4.5V to 5.5V
CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V

VCC = 4.5V to 5.5V
V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V

VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V
V

CC = 1.8V to 2.5V

VCC = 4.5V to 5.5V (Note 1)
V

CC = 2.5V to 4.5V (Note 1)
CC = 1.8V to 2.5V (Note 1)

V
VCC = 4.5V to 5.5V

V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V

V

CC = 2.5V to 4.5V
CC = 1.8V to 2.5V

V
VCC = 4.5V to 5.5V (Note 1)

V

CC = 2.5V to 4.5V (Note 1)
CC = 1.8V to 2.5V (Note 1)

V
VCC = 4.5V to 5.5V

CC = 2.5V to 4.5V

V

CC = 1.8V to 2.5V

V

(Note 2)

 2004 Microchip Technology Inc. DS21230D-page 3

25AA080/25LC080/25C080

FIGURE 1-1: HOLD TIMING

CS

17

18

High-impedance

SCK

SO

16

n+2 n+1 n n-1

16

17

19

n

SI

HOLD

n+2 n+1 n

FIGURE 1-2: SERIAL INPUT TIMING

CS

SCK

SI

SO

2
Mode 1,1
Mode 0,0

65

MSB in

High-impedance

7

don’t care

8

LSB in

5

n

3

n-1

4

12

11

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

9

10

SCK

13

SO

SI

DS21230D-page 4  2004 Microchip Technology Inc.

MSB out

don’t care

14

3

Mode 1,1
Mode 0,0

15

ISB out

25AA080/25LC080/25C080

1.3 AC Test Conditions

AC Waveform:

VLO = 0.2V —

HI = VCC - 0.2V (Note 1)

V
VHI = 4.0V (Note 2)

Timing Measurement Reference Lev el

Input 0.5 V
Output 0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V

CC > 4.0V

CC

FIGURE 1-4: AC TEST CIRCUIT

VCC

2.25 KΩ

SO

1.8 KΩ

100 pF

 2004 Microchip Technology Inc. DS21230D-page 5

25AA080/25LC080/25C080

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP SOIC Function

CS
SO 2 2 Serial Data Output

WP
Vss 4 4 Ground

SI 5 5 Serial Data Input

SCK 6 6 Serial Clock Input

HOLD

Vcc 8 8 Supply Voltage

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardle ss of
the CS input signal. If CS is brought high during a
program cycle, the de vice wil l go into S t andb y mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A lo w-to-high transiti on on CS
sequence initiates an internal write cycle. After power­up, a low level on CS is r equ ired p r ior to any sequence
being initiated.

1 1 Chip Select Input

3 3 Write-Protect Pin

7 7 Hold Input

after a valid write

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication
between a master and the 25XX080. Instructions,
addresses or data pres en t on th e SI pin are latched on
the rising edge of t he c lo ck input, while data on the SO
pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the
25XX080 while in the middle of a serial sequence
without having to retra nsmit the e ntire sequ ence agai n.
It must be held hi gh an y tim e this f unct ion is not be ing
used. Once the device is selected and a serial
sequence is underway, the HOLD
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to­low transition. The 25XX080 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these p ins will be ignored. To
resume serial communication, HOLD
high while the SCK p in is lo w, otherwise seria l com mu­nication will not resum e. Lowering the HOLD lin e at any
time will tri-state the SO line.

pin may be pulled

must be brought

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX080.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.

2.3 Write-Protec t (WP)

This pin is used in conjunction with the WPEN bit in the
Status register to prohibit writes to the nonvolatile bits
in the Status register. When WP is low and WPEN is
high, writing to the no nvolatil e bits in the Status register
is disabled. All other operations function normally.
When WP
nonvolatile bits in the Status register operate normally.
If the WPEN bit is set, WP
write sequence will disable writing to the Status
register. If an internal write cycle has already begun,
WP

The WP
the Status register is low. This allows the user to install
the 25XX080 in a system with WP
still be able to write to the Status register. The WP
functions will be enabled when the WPEN bit is set
high.

is high, all functions, including writes to the

low during a Status register

going low will have no effect on the write.

pin function is blocked when the WPEN bit in

pin grounded and

pin

DS21230D-page 6  2004 Microchip Technology Inc.

25AA080/25LC080/25C080

3.0 FUNCTIONAL DESCRIPTION

3.1 Principles of Operation

The 25XX080 are 1024 byte Serial EEPROMs
designed to interf ace di rec tly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro­controller families, including Microchip’s PIC16C6X/7X
microcontrollers. It may also interface with microcon­trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly with the
software.

The 25XX080 conta ins an 8-bit instr uction regi ster . The
device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS
be low and the HOLD
operation. The WP
writing to the memory array.

Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.

Data is sampled on the fir st rising edge of SCK after CS
goes low. If the clock line is shared with other periph­eral devices on the SPI bus, the user can assert the
HOLD input and pl ace the 25X X080 in ‘HO LD’ mode.
After releasing the HOLD
from the point when the HOLD

pin must be high fo r the entire

pin must be held high to allow

pin, operation will resume

was asserted.

3.2 Read Sequence

The devic e is selected by pulling CS low. The 8-bit READ
instruction is transmitted t o the 25XX080 followed by
the 16-bit address, with the six MSBs of the address
being "don’t care" bits. After the correct READ instruction
and address are sent, the data stored in the memory at
the selected address i s shifted o ut on the SO pin. The
data stored in the memory a t the next address can be
read sequentially by continuing to provide clock pulses.
The internal address pointer is automatically incre­mented to the next higher address af ter each byte of
data is shifted out. When the highest address is reached
(03FFh), the address counter rolls over to address
0000h allowing the read cycle t o be continued indefi­nitely. The read operation is terminated b y raising the

pin (Figure 3-1).

CS

TABLE 3-1: INSTRUCTION SET

pin must

3.3 Write Sequence

Prior to any attempt to write data to the 25XX080, the
write enable latch must be set by issuing the WREN
instruction (Figure3-4). This is done by setting CS
and then clocking out the proper instruction into the
25XX080. After all eight bi ts of the in struction are trans­mitted, the CS
enable latch. If the write operation is initiated immedi­ately after the WREN instruction without CS being
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.

Once the write enable latch is set, the user may
proceed by setting the C S
tion, followed by the 16-bit address, with the six MSBs
of the address being “do n’t care” bi ts, and the n the data
to be written. Up to 16 bytes of data can be sent to the
25XX080 before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. A pa ge ad dress b egins with

0000 and ends with xxxx xxxx xxxx 1111.

xxxx

If the internal address counter reaches

xxxx

1111 and the clock continues, the counter will
roll back to the first address of the page and overwrite
any data in the page that may have been written.

For the data to be actually written to the array, the CS
must be brought high after the Leas t Significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.

must be brought high to set the write

low, issuing a WRITE instruc-

xxxx xxxx

xxxx xxxx

th

data byte has been clocked in. If CS is

low

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WRDI 0000 0100 Reset the write enable latch (disable write operations)
WREN 0000 0110 Set the write enable latch (enable write operations)
RDSR 0000 0101 Read Status register
WRSR 0000 0001 Write Status register

 2004 Microchip Technology Inc. DS21230D-page 7

25AA080/25LC080/25C080

FIGURE 3-1: READ SEQUENCE

CS

0 234567891011 21222324252627282930311

SCK

instruction 16-bit address

SI

0100000115 14 13 12 210

High-impedance

SO

FIGURE 3-2: BYTE WRITE SEQUENCE

CS

91011 2122232425262728293031

SCK

SI

SO

0 23456718

instruction 16-bit address data byte

0000000115 14 13 12

High-impedance

FIGURE 3-3: PAGE WRITE SEQUENCE

CS

0 23456718

SCK

9 1011 2122232425262728293031

data out

76543210

Twc

21076543210

instruction 16-bit addres s data byte 1

SI

CS

32 34 35 36 37 38 3933

SCK

data byte 2

SI

DS21230D-page 8  2004 Microchip Technology Inc.

76543210

0000000115 14 13 12

41 42 43 46 47

40

data byte 3

76543210

21076543210

44 45

data byte n (16 max)

76543210

25AA080/25LC080/25C080

3.4 Write Enable (WREN) and Write
Disable (WRDI)

The 25XX080 contains a write enable latch. See
Table 3-3 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation w ill be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.

FIGURE 3-4: WRITE ENABLE SEQUENCE

CS

0 2345671

SCK

SI

SO

010000 01

High-impedance

The following is a list of conditions under which the
write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

FIGURE 3-5: WRITE DISABLE SEQUENCE

CS

0 2345671

SCK

SI

SO

010000 01

High-impedance

0

 2004 Microchip Technology Inc. DS21230D-page 9

25AA080/25LC080/25C080

3.5 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:

7 654 3 2 1 0

WPEN X X X BP1 BP0 WEL WIP

The Write-In-Process (WIP) bit indicates whether the
25XX080 is busy with a write operation. When set to a

1’, a write is in progress, when set to a ‘0’, no write is

‘
in progress. This bit is read-only.

The Wri te Enable Lat ch (WEL) bit indicat es the st atus
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI comma nds
regardless of the state of write protection on the Status
register. This bit is read only.

The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.

See Figure 3-6 for the RDSR timing sequence.

FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE

CS

9101112131415

SCK

SI

0 23456718

instruction

11000000

0’, the latch

SO

High-impedance

data from Status register

7654 210

3

DS21230D-page 10  2004 Microchip Technology Inc.

25AA080/25LC080/25C080

3.6 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows the
user to select one of four levels of protection for the
array by writing to the appropriate bi ts in the S t atus reg­ister. The array is divided up into four segments. The
user has the ability to write-protect none, one, two, or
all four of the segment s of the arra y. The partitioning is
controlled as shown in Table 3-2.

The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bi t for the WP
Write-Protect (WP
(WPEN) bit in the Status register control the program­mable hardware write-protect feature. Hardware write
protection is enabled when WP
WPEN bit is high. Hardw are write protec tion is disa bled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See T ab le 3-3 for a matrix of functionali ty on the WPEN
bit.

See Figure 3-5 for the WRSR timing sequence.

) pin and the Write-Protect Enable

pin is low and the

pin. The

TABLE 3-2: ARRAY PROTECTION

BP1 BP0

00 none
01 upper 1/4

10 upper 1/2

11 all

FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE

Array Addresses

Write-Protected

(0300h - 03FFh)

(0200h - 03FFh)

(0000h - 03FFh)

CS

SCK

SO

SI

0 23456718

instruction data to Status register

0 1000000

High-impedance

9101112131415

7654 210

3

 2004 Microchip Technology Inc. DS21230D-page 11

25AA080/25LC080/25C080

3.7 Data Protection

The following protection has been implemented to
prevent in advertent writes to the array:

• The write enable latch is reset on power-up

•A WRITE ENABLE instruction must be issued to
set the write enable latch

• After a byte write, page write or Status register
write, the write enable latch is reset

must be set high after the proper number of

•CS
clock cycles to start an internal write cycle

• Access to the array during an internal write cycle
is ignored and programming is continued

3.8 Power-On State

The 25XX080 powers on in the following state:

• The device is in low-power Standby mode
=1)

(CS

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low level transition on CS

enter active state

is required to

TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX

WPEN WP WEL Protected Blocks Unprotected Blocks Status Register

XX0Protected Protected Protected
0X1Protected Writable Writable
1 Low 1 Protected Writable Protected
X High 1 Protected Writable Writable

DS21230D-page 12  2004 Microchip Technology Inc.

4.0 PACKAGING INFORMATION

4.1 Package Marking Information

25AA080/25LC080/25C080

8-Lead PDIP (300 mil)

XXXXXXXX
XXXXXNNN

YYWW

8-Lead SOIC (150 mil)

XXXXXXXX
XXXXYYWW

NNN

Example:

25LC080
/PNNN

YYWW

Example:

25LC080
/SNYYWW

NNN

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code

Note: In the event the full Microchi p pa rt numbe r cannot be marke d on o ne line, it will

be carried over to the next line thus lim iti ng the nu mber of available characters
for customer specific information.

* Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.

 2004 Microchip Technology Inc. DS21230D-page 13

25AA080/25LC080/25C080

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

E

β

eB

Number of Pins
Pitch
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

Dimension Limits MIN NOM MAX MIN NOM MAX

1

α

A

c

Units INCHES* MILLIMETERS

n
p

c

α
β

.008 .012 .015 0.20 0.29 0.38

A1

B1

B

88

.100 2.54

51015 51015
51015 51015

A2

L

p

DS21230D-page 14  2004 Microchip Technology Inc.

25AA080/25LC080/25C080

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

Number of Pins
Pitch

Foot Angle
Lead Thickness

Mold Draft Angle Top
Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057

n

45×

c

β

n
p

f

c

α

β

1

h

A

f

L

048048

A1

MILLIMETERSINCHES*Units

1.27.050

α

A2

MAXNOMMINMAXNOMMINDimension Limits

88

1.751.551.35.069.061.053AOverall Height

1.551.421.32.061.056.052A2Molded Package Thickness

0.250.180.10.010.007.004A1Standoff §

6.206.025.79.244.237.228EOverall Width

3.993.913.71.157.154.146E1Molded Package Width

5.004.904.80.197.193.189DOverall Length

0.510.380.25.020.015.010hChamfer Distance

0.760.620.48.030.025.019LFoot Length

0.250.230.20.010.009.008

0.510.420.33.020.017.013BLead Width
1512015120
1512015120

 2004 Microchip Technology Inc. DS21230D-page 15

25AA080/25LC080/25C080

APPENDIX A: REVISION HISTORY

Revision D

Added note to page 1 header (Not recommended for
new designs).

Updated document format.

DS21230D-page 16  2004 Microchip Technology Inc.

25AA080/25LC080/25C080

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip
World Wide Web site.

The web site is used b y Mic rochip as a me ans to m ake
files and information easily available to customers. To
view the site, the use r must have access to the Intern et
and a web browser, such as Netscape
Internet Explorer. Files are also available for FTP
download from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available at the following
URL:

www.microchip.com

The file transfer site is available by using an FTP
service to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari­ety of Micr ochip specific bu siness informatio n is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked
Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to
Microchip Products

• Conferences for p roducts, D evelopment Systems,
technical information and more

• Listing of seminars and events

®

or Microsoft

SYSTEMS INFORMATION AND UPGRADE HOT LINE

The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.

®

Plus, this line provides information on how customers
can receive the most c urrent upgrade kit s. The Hot Line
Numbers are:

1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.

042003

 2004 Microchip Technology Inc. DS21230D-page 17

25AA080/25LC080/25C080

READER RESPONSE

It is our intentio n to pro vi de you with the best documentation possible to ens ure suc c es sfu l u se of y ou r M ic roc hip prod­uct. If you wish to provid e your c omment s on org anizatio n, clarity, subject matter , and ways in w hich o ur document atio n
can better serve you, please FAX your comments to the Technical Publications Manager at [phone].

Please list the following information, and use this outline to provide us with your comments about this document.

To:
RE: Reader Response
From:

Application (optional):
Would you like a reply? Y N

Device: Literature Number:
Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

Technical Publications Manager

Name
Company

Address
City / State / ZIP / Country

Telephone: (_______) _________ - _________

Total Pages Sent ________

FAX: (______) _________ - _________

DS21230D25AA080/25LC080/25C080

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21230D-page 18  2004 Microchip Technology Inc.

25AA080/25LC080/25C080

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X /XX XXX

Device

Device 25AA 080: 8 Kbit 1.8V SPI Serial EEPROM

Temperature
Range

Range

25AA080T: 8 Kbit 1.8V SPI Serial EEPROM
(Tape and Reel)
25LC080: 8 Kbit 2.5V SPI Serial EEPROM
25LC080: 8 Kbit 2.5V SPI Serial EEPROM
(Tape and Reel)
25C080: 8 Kbit 5.0V SPI Serial EEPROM
25C080: 8 Kbit 5.0V SPI Serial EEPROM
(Tape and Reel)

I= -40°C to +85°C
E= -40°C to+125°C

PatternPackageTemperature

Examples:

a) 25AA080-I/SN: Industrial Temp.,

SOIC package

b) 25AA080T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

c) 25LC080-I/SN: Industrial Temp.,

SOIC package

d) 25LC080T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

e) 25C080-I/P: Industrial Temp.,

PDIP package

f) 25C080-I/SN: Industrial Temp.,

SOIC package

g) 25C080T-I/SN: Tape and Reel,

Industrial Temp., SOIC package

h) 25C080-E/SN: Extended Temp.,

SOIC package

Package P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: [phone]

3. Th e Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2004 Microchip Technology Inc. DS21230D-page 19

25AA080/25LC080/25C080

NOTES:

DS21230D-page 20  2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protect ion f eatures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Mill ennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K

EELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

8-bit MCUs, KEELOQ

®

code hopping

 2004 Microchip Technology Inc. DS21230D-page 21

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone]
Fax: [phone]
Technical Support: 480-792-7627
Web Address: www.microchip.com

Atlanta

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Tel: [phone]
Fax: [phone]

Boston

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Chicago

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Dallas

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Detroit

Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: [phone]
Fax: [phone]

Kokomo

2767 S. Albright Road
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Fax: [phone]

Los Angeles

18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: [phone]
Fax: [phone]

San Jose

1300 Terra Bella Avenue
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Fax: [phone]

Toronto

6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Cana da
Tel: [phone]
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ASIA/PACIFIC

Australia

Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
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Fax: [phone]

China - Beijing

Unit 706B
Wan Tai Bei Hai Bldg.
No. 6 Chaoyangmen Bei Str.
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Tel: [phone]
Fax: [phone]

China - Chengdu

Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: [phone]
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China - Fuzhou

Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
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China - Hong Kong SAR

Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
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China - Shanghai

Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
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Tel: [phone]
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China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: [phone]
Fax: [phone]

China - Shunde

Room 401, Hongjian Building, No. 2
Fengxiangnan Road, Ronggui Town, Shunde
District, Foshan City, Guangdong 528303, China
Tel: [phone] Fax: [phone]

China - Qingdao

Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
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Tel: [phone] Fax: [phone]

India

Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: [phone] Fax: [phone]

Japan

Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: [phone] Fax: [phone]

Korea

168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: [phone] Fax: [phone] or
82-2-558-5934

Singapore

200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: [phone] Fax: [phone]

Taiwan

Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
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Fax: [phone]

Taiwan

Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: [phone] Fax: [phone]

EUROPE

Austria

Durisolstrasse 2
A-4600 Wels
Austria
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Fax: [phone]

Denmark

Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: [phone] Fax: [phone]

France

Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: [phone]
Fax: [phone]

Germany

Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: [phone]
Fax: [phone]

Italy

Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: [phone]
Fax: [phone]

Netherlands

Waegenburghtplein 4
NL-5152 JR, Drunen, Netherlands
Tel: [phone]
Fax: [phone]

United Kingdom

505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshir e, England RG41 5T U
Tel: [phone]
Fax: [phone]

05/28/04

DS21230D-page 22  2004 Microchip Technology Inc.