MICROCHIP 25AA040, 25LC040, 25C040 Technical data



M

25AA040/25LC040/25C040

4K SPI

™

Bus Serial EEPROM

DEVICE SELECTION TABLE

Part

Number

25AA040 1.8-5.5V 1 MHz C,I
25LC040 2.5-5.5V 2 MHz C,I

25C040 4.5-5.5V 3 MHz C,I,E

V

CC

Range

Max Clock
Frequency

Temp

Ranges

FEATURES

• Low power CMOS technology

- Write current: 3 mA typical

- Read current: 500 µ A typical

- Standby current: 500 nA typical

• 512 x 8 bit organization

• 16 byte page

• Write cycle time: 5ms max.

• Self-timed ERASE and WRITE cycles

• Block write protection

- Protect none, 1/4, 1/2, or all of array

• Built-in write protection

- Power on/off data protection circuitry

- Write enable latch

- Write protect pin

• Sequential read

• High reliability

- Endurance: 10M cycles (guaranteed)

- Data retention: > 200 years

- ESD protection: > 4000 V

• 8-pin PDIP, SOIC, and TSSOP packages

• Temperature ranges supported:

- Commercial: (C) 0 ° C to +70 ° C

- Industrial: (I) -40 ° C to +85 ° C

- Automotive: (E) (25C040) -40 ° C to +125 ° C

PACKAGE TYPES

PDIP/SOIC

CS
SO

WP

VSS

HOLD

VCC

CS
SO

1
2
3
4

TSSOP

1
2
3
4

BLOCK DIAGRAM

Status

Register

I/O Control

Logic

Memory

Control

25xx040

25xx040

Logic

8

V

CC

7

HOLD

6

SCK

5

SI

SCK

8

SI

7

V

6

SS

5

WP

HV Generator

EEPROM

X

Dec

Array

Page Latches

DESCRIPTION

The Microchip Technology Inc. 25AA040/25LC040/
25C040 (25xx040
able PROM. The memory is accessed via a simple
Serial Peripheral Interface (SPI) compatible serial bus.
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a chip select (CS

Communication to the device can be paused via the
hold pin (HOLD
tions on its inputs will be ignored, with the exception of
chip select, allowing the host to service higher priority
interrupts. Also, write operations to the device can be
disabled via the write protect pin (WP

*25xx040 is used in this document as a generic part number for the 25AA040/25LC040/25C040 devices.
SPI is a trademark of Motorola.

1997 Microchip Technology Inc.

*

) is a 4K bit serial Electrically Eras-

) input.

). While the device is paused, transi-

).

Preliminary

SI

SO
CS

SCK

HOLD

WP

Y Decoder

Sense Amp.
R/W Control

VCC
VSS

DS21204A-page 1



≤

2:

25AA040/25LC040/25C040

µ

µ

µ

µ A µ

1.0 ELECTRICAL

1.1 Maxim

Vcc...................................................................................7.0V

All inputs and outputs w.r.t. Vss.................. -0.6V to Vcc+1.0V

Storage temperature.......................................-65˚C to 150˚C

Ambient temperature under bias..................... -65˚C to 125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins.................................................4kV

*Notice: Stresses above those listed under ‘Maximum ratings’ may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability

TABLE 1-1: PIN FUNCTION TABLE

CHARACTERISTICS

um Ratings*

Name Function

CS
SO Serial Data Output

SI Serial Data Input

SCK Serial Clock Input

WP

SS

V

CC

V

HOLD

Chip Select Input

Write Protect Pin
Ground
Supply Voltage
Hold Input

FIGURE 1-1: AC TEST CIRCUIT

VCC

2.25 K

SO

1.8 K

1.2 A

C Test Conditions

AC Waveform:

= 0.2V

LO

V

HI

CC

V

= V

- 0.2V (Note 1)

= 4.0V (Note 2)

HI

V

Timing Measurement Reference Level

Input 0.5 V
Output 0.5 V

For V

CC

> 4.0V

CC

4.0V

Note 1: For V

100 pF

CC
CC

TABLE 1-2: DC CHARACTERISTICS

All parameters apply over the
specified operating ranges
unless otherwise noted.

Commercial (C): T
Industrial (I): T
Automotive (E): T

Parameter Symbol Min Max Units Test Conditions

V

1 2.0 V

High level input voltage

Low level input voltage

Low level output voltage

High level output voltage V
Input leakage current I
Output leakage current I
Internal Capacitance

IH
IH

V

2 0.7 V

1 -0.3 0.8 V V

IL

V
V

2 -0.3 0.3 V

IL

OL

V

OL

V

OH

LI

LO

C

INT

(all inputs and outputs)

I

CC

Read —

Operating Current

Standby Current I

CC

I

Write —

CCS

Note: This parameter is periodically sampled and not 100% tested.

AMB

= 0 ° C to +70 ° C V

AMB

= -40 ° C to +85 ° C V

AMB

= -40 ° C to +125 ° C V

+1 V V

CC

CC

CC

V

+1 V V

CC

— 0.4 V I
— 0.2 V I

V

-0.5 — V I

CC

-10 10

-10 10
— 7 pF T

1

—

500

5

—
—

—

3
5

2

CC

= 1.8V to 5.5V

CC

= 1.8V to 5.5V

CC

= 4.5V to 5.5V (25C040 only)

≥ 2.7V (Note)

CC
CC

< 2.7V (Note)

≥ 2.7V (Note)

CC

V V

A CS
A CS

mA

A

mAmAV

A

< 2.7V (Note)

CC

OL

= 2.1 mA
= 1.0 mA, V

OL

=-400 µ A

OH

= V

CC

= V

CC

= 25˚C, CLK = 1.0 MHz,

AMB

V

= 5.0V (Note)

CC

V

CC

= 5.5V; F

V

= 2.5V; F

CC
CC

= 5.5V

V

= 2.5V

CC

= Vcc = 5.5V, Inputs tied to V

CS

, V
, V

IN

= V

OUT

CLK
CLK

CC

= V

CS = Vcc = 2.5V, Inputs tied to V

< 2.5V

SS

TO

CC

V

V

SS

TO

CC

=3.0 MHz; SO = Open
=2.0 MHz; SO = Open

CC

or V

CC

or V

SS
SS

DS21204A-page 2

Preliminary

1997 Microchip Technology Inc.

25AA040/25LC040/25C040

TABLE 1-3: AC CHARACTERISTICS

All parameters apply over the
specified operating ranges
unless otherwise noted.

Parameter Symbol Min Max Units Test Conditions

Clock Frequency FCLK —

CS Setup Time TCSS 100

CS Hold Time TCSH 150

CS Disable Time TCSD 500 — ns
Data Setup Time TSU 30

Data Hold Time THD 50

CLK Rise Time TR — 2 µs (Note 1)
CLK Fall Time TF — 2 µs (Note 1)
Clock High Time THI 150

Clock Low Time TLO 150

Clock Delay Time TCLD 50 — ns
Clock Enable Time TCLE 50 — ns
Output Valid from

Clock Low

Output Hold Time THO 0 — ns (Note 1)
Output Disable Time TDIS —

HOLD Setup Time THS 100

HOLD Hold Time THH 100

HOLD Low to Output High-Z THZ 100

HOLD High to Output Valid THV 100

Internal Write Cycle Time TWC — 5 ms
Endurance — 10M — E/W Cycles (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please

consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

Commercial (C): Tamb = 0 ° C to +70 ° C V
Industrial (I): Tamb = -40 ° C to +85 ° C V
Automotive (E): Tamb = -40°C to +125°C VCC = 4.5V to 5.5V (25C040 only)

3
—
—

250
500

250
475

50
50

100
100

250
475

250
475

TV —

—
—

—
—

100
200

100
200

150
200

150
200

2

1

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

150
250
475

200
250
500

—
—
—

—
—
—

—
—
—

—
—
—

CC

= 1.8V to 5.5V

CC = 1.8V to 5.5V

MHz
MHz
MHz

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

ns
ns
ns

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V

CC = 1.8V to 2.5V

V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V

VCC = 4.5V to 5.5V (Note 1)
VCC = 2.5V to 4.5V (Note 1)
VCC = 1.8V to 2.5V (Note 1)

VCC = 4.5V to 5.5V
VCC = 2.5V to 4.5V
VCC = 1.8V to 2.5V



1997 Microchip Technology Inc.

Preliminary

DS21204A-page 3

25AA040/25LC040/25C040

FIGURE 1-2: HOLD TIMING

CS

THH

THS THS THH

SCK

SO

SI

n+2 n+1 n n-1

n+2 n+1 n

HOLD

FIGURE 1-3: SERIAL INPUT TIMING

high impedance

don’t care

THVTHZ

n

TSU

n

n-1

CS

TCSS

THDTsu

MSB in

high impedance

SCK

SI

SO

Mode 1,1
Mode 0,0

FIGURE 1-4: SERIAL OUTPUT TIMING

CS

THI

SCK

TV

TLO

TR

THC

TF

TCSD

TCLE

TCLD

TCSH

LSB in

TCSH

Mode 1,1
Mode 0,0

TDIS

SO

SI

DS21204A-page 4 Preliminary  1997 Microchip Technology Inc.

MSB out

don’t care

ISB out

25AA040/25LC040/25C040

2.0 PIN DESCRIPTIONS

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level
deselects the device and forces it into standby mode.
However, a programming cycle which is already initi­ated or in progress will be completed, regardless of the
CS

input signal. If CS is brought high during a program
cycle, the device will go in standby mode as soon as
the programming cycle is complete. As soon as the
device is deselected, SO goes to the high impedance
state, allowing multiple parts to share the same SPI
bus. A low to high transition on CS
sequence initiates an internal write cycle. After power­up, a low level on CS
being initiated.

is required prior to any sequence

2.2 Serial Input (SI)

The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.

2.3 Serial Output (SO)

The SO pin is used to transfer data out of the 25xx040.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.

2.4 Serial Clock (SCK)

The SCK is used to synchronize the communication
between a master and the 25xx040. Instructions,
addresses, or data present on the SI pin are latched
on the rising edge of the clock input, while data on the
SO pin is updated after the falling edge of the clock
input.

after a valid write

2.5 Write Protect (WP)

This pin is a hardware write protect input pin. When
WP

is low, all writes to the array or status register are
disabled, but any other operation functions normally.
When WP
writes operate normally. WP
reset the write enable latch and inhibit programming,
except when an internal write has already begun. If an
internal write cycle has already begun, WP
will have no effect on the write. See Table 3-2 for Write
Protect Functionality Matrix.

is high, all functions, including non-volatile

going low at any time will

going low

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the
25xx040 while in the middle of a serial sequence with­out having to re-transmit the entire sequence over at a
later time. It must be held high any time this function is
not being used. Once the device is selected and a
serial sequence is underway, the HOLD
pulled low to pause further serial communication with­out resetting the serial sequence. The HOLD
be brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high to
low transition. The 25xx040 must remain selected dur­ing this sequence. The SI, SCK, and SO pins are in a
high impedance state during the time the part is
paused and transitions on these pins will be ignored.
To resume serial communication, HOLD
brought high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.

pin may be

pin must

must be

 1997 Microchip Technology Inc. Preliminary DS21204A-page 5

25AA040/25LC040/25C040

3.0 FUNCTIONAL DESCRIPTION

3.1 PRINCIPLES OF OPERATION

The 25xx040 is a 512 byte Serial EEPROM designed
to interface directly with the Serial Peripheral Interface
(SPI) port of many of today’s popular microcontroller
families, including Microchip’s PIC16C6X/7X micro­controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete
I/O lines programmed properly with the software.

The 25xx040 contains an 8-bit instruction register. The
part is accessed via the SI pin, with data being clocked
in on the rising edge of SCK. The CS
and the HOLD
tion. The WP
the memory array.

Table 3-1 contains a list of the possible instruction
bytes and format for device operation. The most signif­icant address bit (A8) is located in the instruction byte.
All instructions, addresses, and data are transferred
MSB first, LSB last.

Data is sampled on the first rising edge of SCK after
CS

goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD
mode. After releasing the HOLD
resume from the point when the HOLD

pin must be high for the entire opera-

pin must be held high to allow writing to

input and place the 25xx040 in ‘HOLD’

3.2 Read Sequence

The part is selected by pulling CS low. The 8-bit read
instruction with the A8 address bit is transmitted to the
25xx040 followed by the lower 8-bit address (A7
through A0). After the correct read instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin. The data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses. The
internal address pointer is automatically incremented to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(01FFh), the address counter rolls over to address
0000h allowing the read cycle to be continued indefi­nitely. The read operation is terminated by raising the
CS

pin (Figure 3-1).

pin must be low

pin, operation will

was asserted.

3.3 Write Sequence

Prior to any attempt to write data to the 25xx040, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS
and then clocking out the proper instruction into the
25xx040. After all eight bits of the instruction are trans­mitted, the CS
enable latch. If the write operation is initiated immedi­ately after the WREN instruction without CS
brought high, the data will not be written to the array
because the write enable latch will not have been
properly set.

Once the write enable latch is set, the user may pro­ceed by setting the CS
followed by the address, and then the data to be writ­ten. Keep in mind that the most significant address bit
(A8) is included in the instruction byte. Up to 16 bytes
of data can be sent to the 25xx040 before a write cycle
is necessary. The only restriction is that all of the bytes
must reside in the same page. A page address begins
with XXXX 0000 and ends with XXXX 1111. If the
internal address counter reaches XXXX 1111 and the
clock continues, the counter will roll back to the first
address of the page and overwrite any data in the
page that may have been written.

For the data to be actually written to the array, the CS
must be brought high after the least significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the status register may
be read to check the status of the WIP, WEL, BP1, and
BP0 bits (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.

must be brought high to set the write

low, issuing a write instruction,

th

data byte has been clocked in. If CS is

low

being

TABLE 3-1: INSTRUCTION SET

Instruction Name Instruction Format Description

READ 0000 A

WRITE 0000 A

WRDI 0000 0100 Reset the write enable latch (disable write operations)

WREN 0000 0110 Set the write enable latch (enable write operations)

RDSR 0000 0101 Read status register

WRSR 0000 0001 Write status register

Note: A

DS21204A-page 6 Preliminary  1997 Microchip Technology Inc.

is the 9th address bit necessary to fully address 512 bytes.

8

011 Read data from memory array beginning at selected address

8

010 Write data to memory array beginning at selected address

8

FIGURE 3-1: READ SEQUENCE

CS

25AA040/25LC040/25C040

0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 221

SCK

instruction lower address byte

A7 6 5 4

SO

SI

0 1A80000 1

high impedance

FIGURE 3-2: BYTE WRITE SEQUENCE

CS

0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 221

SCK

instruction lower address byte

A7 6 5 4

SO

0 0A80000

SI

1

3 2

3 2

high impedance

1 A0

1 A0

23

don’t care

data out

7 6 5 4 3 2 1 0

twc

23

data byte

7 6 5 4 3 2 1 0

FIGURE 3-3: PAGE WRITE SEQUENCE

CS

8

33

7 6 5 4 3 2 1 0

SCK

SI

CS

SCK

SI

0 2 3 4 5 6 71

instruction lower address byte data byte 1

0 0A80000 1 A7 6 5 4 2 1 0 7 6 5 4 3 2 1 0

25 27 28 29 30 31 3226

data byte 2

7 6 5 4 3 2 1 0

9 10 11 14 15 16 17 18 19 20 21 22 23 24

13

3

34 35 36 39 40

37 38

data byte 3

data byte n (16 max)

7 6 5 4 3 2 1 0

 1997 Microchip Technology Inc. Preliminary DS21204A-page 7

25AA040/25LC040/25C040

3.4 Write Enable (WREN) and Write

Disable (WRDI)

The 25xx040 contains a write enable latch. See
Table 3-3 for the Write Protect Functionality Matrix.
This latch must be set before any write operation will
be completed internally. The WREN instruction will set
the latch, and the WRDI will reset the latch.

FIGURE 3-4: WRITE ENABLE SEQUENCE

CS

0 2 3 4 5 6 71

SCK

SI

SO

0 10 0 0 0 01

The following is a list of conditions under which the
write enable latch will be reset:

• Power-up

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

• WP

high impedance

line is low

FIGURE 3-5: WRITE DISABLE SEQUENCE

CS

0 2 3 4 5 6 71

SCK

SI

SO

0 10 0 0 0 01

0

high impedance

DS21204A-page 8 Preliminary  1997 Microchip Technology Inc.

25AA040/25LC040/25C040

3.5 Read Status Register (RDSR)

The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format­ted as follows:

7 6 5 4 3 2 1 0
X X X X BP1 BP0 WEL WIP

The Write-In-Process (WIP) bit indicates whether the
25xx040 is busy with a write operation. When set to a
‘1’ a write is in progress, when set to a ‘0’ no write is in
progress. This bit is read only.

The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’ the latch
allows writes to the array, when set to a ‘0’ the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the status
register. This bit is read only.

The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write protected. These bits
are set by the user issuing the WRSR instruction.
These bits are non-volatile.

See Figure 3-6 for RDSR timing sequence

3.6 Write Status Register(WRSR)

The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the status register. The array is
divided up into four segments. The user has the ability
to write protect none, one, two, or all four of the seg­ments of the array. The partitioning is controlled as
illustrated in Table 3-2.

See Figure 3-7 for WRSR timing sequence

TABLE 3-2: ARRAY PROTECTION

BP1 BP0

0 0 none
0 1

1 0

1 1

Array Addresses

Write Protected

upper 1/4

(0180h - 01FFh)

upper 1/2

(0100h - 01FFh)

all

(0000h - 01FFh)

FIGURE 3-6: READ STATUS REGISTER SEQUENCE

CS

8

7 6 5 4 2 1 0

SCK

SO

0 2 3 4 5 6 71

instruction

SI

high impedance

1 100000 0

FIGURE 3-7: WRITE STATUS REGISTER SEQUENCE

CS

0 2 3 4 5 6 71

SCK

instruction data to status register

SI

0 100000 0

7 6 5 4

9 10 11 12 13 14 15

data from status register

3

8

9 10 11 12 13 14 15

2 1 0

3

high impedance

SO

 1997 Microchip Technology Inc. Preliminary DS21204A-page 9

25AA040/25LC040/25C040

3.7 Data Protection

The following protection has been implemented to pre­vent inadvertent writes to the array:

• The write enable latch is reset on power-up.

• A write enable instruction must be issued to set

the write enable latch.

• After a byte write, page write, or status register

write, the write enable latch is reset.

• CS

must be set high after the proper number of

clock cycles to start an internal write cycle.

• Access to the array during an internal write cycle

is ignored and programming is continued.

• The write enable latch is reset when the WP

low .

pin is

3.8 Power On State

The 25xx040 powers on in the following state:

• The device is in low power standb y mode (CS

• The write enable latch is reset.

• SO is in high impedance state.

• A low level on CS

.

is required to enter active state.

TABLE 3-3: WRITE PROTECT FUNCTIONALITY MATRIX

WP WEL Protected Blocks Unprotected Blocks Status Register

Low X Protected Protected Protected
High 0 Protected Protected Protected
High 1 Protected Writable Writable

=1).

DS21204A-page 10 Preliminary  1997 Microchip Technology Inc.

25AA040/25LC040/25C040

25AA040/25LC040/25C040 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

25xx040 — /P

P=Plastic DIP (300 mil Body), 8-lead

Package:

SN=Plastic SOIC (150 mil Body), 8-lead

ST=TSSOP, 8-lead

Sales and Support

Temperature
Range:

Devices:

Blank=0°C to +70°C

I=–40°C to +85°C

E=–40°C to +125°C

25AA040 4096 bit 1.8V SPI Serial EEPROM

25AA040T 4096 bit 1.8V SPI Serial EEPROM Tape and Reel

25AA040X 4096 bit 1.8V SPI Serial EEPROM

in alternate pinout (ST only)

25AA040XT 4096 bit 1.8V SPI Serial EEPROM

in alternate pinout Tape and Reel (ST only)

25LC040 4096 bit 2.5V SPI Serial EEPROM
25LC040T 4096 bit 2.5V SPI Serial EEPROM Tape and Reel
25LC040X 4096 bit 2.5V SPI Serial EEPROM

in alternate pinout (ST only)

25LC040XT 4096 bit 2.5V SPI Serial EEPROM

in alternate pinout Tape and Reel (ST only)

25C040 4096 bit 5.0V SPI Serial EEPROM

25C040T 4096 bit 5.0V SPI Serial EEPROM Tape and Reel

25C040X 4096 bit 5.0V SPI Serial EEPROM

in alternate pinout (ST only)

25C040XT 4096 bit 5.0V SPI Serial EEPROM

in alternate pinout Tape and Reel (ST only)

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office.

2. The Microchip Corporate Literature Center U.S. FAX: [phone].

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

 1997 Microchip Technology Inc. Preliminary DS21204A-page 11



W

ORLDWIDE

AMERICAS

Corporate Office

Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: [phone] Fax: [phone]

Technical Support:
Web:

http://www.microchip.com

Atlanta

Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: [phone] Fax: [phone]

Boston

Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: [phone] Fax: [phone]

Chicago

Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: [phone] Fax: [phone]

Dallas

Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: [phone] Fax: [phone]

Dayton

Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: [phone] Fax: [phone]

Los Angeles

Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: [phone] Fax: [phone]

New York

Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: [phone] Fax: [phone]

San Jose

Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: [phone] Fax: [phone]

Toronto

Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: [phone] Fax: [phone]

602 786-7627

S

ALES

& S

ASIA/PACIFIC

Hong Kong

Microchip Asia Pacific
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: [phone] Fax: [phone]

India

Microchip Technology India
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: [phone] Fax: [phone]

Korea

Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: [phone] Fax: [phone]

Shanghai

Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, PRC 200335
Tel: [phone]
Fax: [phone]

Singapore

Microchip Technology Taiwan
Singapore Branch
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: [phone] Fax: [phone]

Taiwan, R.O.C

Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: [phone] Fax: [phone]

ERVICE

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

5/8/97

All rights reserved. © 1997, Microchip Technology Incorporated, USA. 6/97

M

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or
warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other
intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks
of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21204A-page 12

Preliminary

1997 Microchip Technology Inc.

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