MICROCHIP 24LC21A Technical data

24LC21A

1K 2.5V Dual Mode I2C™ Serial EEPROM

Features

• Single supply with operation down to 2.5V

• Completely implements DDC1™/DDC2™ interface for monitor identification, including recovery to DDC1

• Pin and function compatible with 24LC21

• Low-power CMOS technology

- 1 mA typical active current

-10 µA standby current typical at 5.5V

• 2-wire serial interface bus, I

C™ compatible

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to eight bytes

• 1,000,000 erase/write cycles ensured

• Data retention > 200 years

• ESD Protection > 4000V

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges

- Commercial (C): 0°C to +70°C

- Industrial (I): -40°Cto +85°C

Description

The Microchip Technology Inc. 24LC21A is a 128x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control information. Two modes of operation have been implemented: Transmit-only mode and Bidirectional mode. Upon power-up, the device will be in the Transmit-only mode, sending a serial bit stream of the memory array from 00h to 7Fh, clocked by the VCLK pin. A valid high-to-low transition on the SCL pin will cause the device to enter the transition mode, and look for a valid control byte on

C bus. If it detects a valid control byte from the

the I master, it will switch into Bidirectional mode, with byte selectable read/write capability of the memory array using SCL. If no control byte is received, the device will revert to the Transmit-only mode after it receives 128 consecutive VCLK pulses while the SCL pin is idle. The 24LC21A is available in a standard 8-pin PDIP and SOIC package in both commercial and industrial temperature ranges.

DDC is a trademark of the Video Electronics Standards Association.

C is a trademark of Philips Corporation.

Package Types

PDIP

24LC21A

SOIC

24LC21A

Vss

Block Diagram

SDA

V VSS

I/O

Control

Logic

SCL

VCLK

Memory

Control

Logic

XDEC

Pin Function Table

Name Function

SS Ground

V SDA Serial Address/Data I/O SCL Serial Clock (Bidirectional mode)

VCLK Serial Clock (Transmit-only mode)

CC +2.5V to 5.5V Power Supply

NC No Connection

Vcc VCLK

SCL

SDA

Vcc VCLK

SCL

SDA

HV Generator

EEPROM

Array

Page Latches

YDEC

Sense AMP

Control

R/W

 2003 Microchip Technology Inc. DS21160F-page 1

24LC21A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. V

SS.........................................................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indica ted in the opera tional li stings of this sp ecification is not i mplied. Ex posure to maximum rating conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

VCC = +2.5V to 5.5V

DC CHARACTERISTICS

Commercial (C): T Industrial (I): T

Parameter Symbol Min Max Units Conditions

SCL and SDA pins:

High-level input voltage Low-level input voltage

VIH VIL

Input levels on VCLK pin:

High-level input voltage

Low-level input voltage Hysteresis of Schmitt Trigger inputs V Low-level output voltage V Low-level output voltage V Input leakage current I

V VIL

HYS .05 VCC —V(Note) OL1 —0.4VIOL = 3 mA, VCC = 2.5V (Note) OL2 —0.6VIOL = 6 mA, VCC = 2.5V

LI —±1µAVIN = 0.1V to VCC

Output leakage current ILO —±1µAVOUT = 0.1V to VCC Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note)

Operating current I

Standby current I

CC Write CC Read

CCS —

Note: This parameter is periodically sampled and not 100% tested.

A = 0°C to +70°C A =-40°C to +85°C

0.7 VCC —

2.0 —

— —

—

0.3 VCC

—

0.2 V

3 1

100

V V

VCC ≥ 2.7V (Note)

mAmAV

CC < 2.7V (Note)

A = 25°C, FCLK = 1 MHz

CC = 5.5V CC = 5.5V, SCL = 400 kHz

µAµAVCC = 3.0V, SDA = SCL = VCC

VCC = 5.5V, SDA = SCL = VCC VCLK = VSS

DS21160F-page 2  2003 Microchip Technology Inc.

TABLE 1-2: AC CHARACTERISTICS

24LC21A

Parameter Symbol

Vcc= 2.5-5.5V

Standard Mode

Vcc= 4.5 - 5.5V

Fast Mode

Units Remarks

Min Max Min Max

Clock frequency F

CLK —100—400kHz

Clock high time THIGH 4000 — 600 — ns Clock low time TLOW 4700 — 1300 — ns SDA and SCL rise time T

R — 1000 — 300 ns (Note 1)

SDA and SCL fall time TF — 300 — 300 ns (Note 1) Start condition hold time THD:STA 4000 — 600 — ns After this period the first cloc k

pulse is generated

Start condition setup time T

SU:STA 4700 — 600 — ns Only relevant for repeated

Start condition Data input hold time T Data input setup time T

HD:DAT 0—0—ns(Note 2)

SU:DAT 250 — 100 — ns

Stop condition setup time TSU:STO 4000 — 600 — ns Output valid from clock TAA — 3500 — 900 ns (Note 2) Bus free time T

BUF 4700 — 1300 — ns Time the bus must be free

before a new transmission

can start Output fall time from VIH

minimum to V

IL maximum

Input filter spike suppres-

OF — 250 20 + 0.1

SP —50—50ns(Note 3)

250 ns (Note 1), CB ≤ 100 pF

sion (SDA and SCL pins) Write cycle time T

WR — 10 — 10 ms Byte or Page mode

Transmit-Only Mode Parameters

Output valid from VCLK T

VAA — 2000 — 1000 ns

VCLK high time TVHIGH 4000 — 600 — ns VCLK low time T

VLOW 4700 — 1300 — ns

VCLK setup time TVHST 0—0—ns VCLK hold time TSPVL 4000 — 600 — ns Mode transition time T Transmi t-onl y power-up

VHZ — 1000 — 500 ns

TVPU 0—0—ns

time Input filter spike suppres-

SPV — 100 — 100 ns

sion (VCLK pin) Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block

mode (Note 4) Note 1: Not 100% tested. C

B = Total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

spike suppression. This eliminates the need for a T

SP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and

I specification for standard operation.

4: T his parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained from our web site.

 2003 Microchip Technology Inc. DS21160F-page 3

24LC21A

2.0 FUNCTIONAL DESCRIPTION

The 24LC21A is designed to comply to the DDC Standard proposed by VESA (Figure 3-3) with the exception that it is not Access.bus cap ab le. I t operates in two modes, the Transmit-only mode and the Bidirectional mode. T here is a sep ara te 2- wire prot ocol to support each mode, each having a separate clock input but sharing a common data line (SDA). The device enters the Transmit-only mode upon power-up. In this mode, the dev ice t ransm its dat a bit s o n the SD A pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high-to-low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the Bidirectional mode and look for its control byte to be sent by the master. If it detects its control byte, it will stay in the Bidirectional mode. Otherwise, it will revert to the Transmit-only mode after it sees 128 VCLK pulses.

2.1 Transmit-Only Mode

The device will power-up in the Transmit-only mode at address 00H. This mode supports a unidirectional 2-wire protocol for continuous transmission of the contents of th e memory a rray. This d evice requi res that

it be initialized prior to valid data being sent in the Transmit-only mode (Section 2.2 “Initialization Pro- cedure”). In this mod e, data is trans mitted on the SDA pin in 8-bit bytes, with each byte followed by a ninth, null bit (Figure 2-1). The clock source for the Transmitonly mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. Th e eight bit s in each byte are transmitted Most Significant bit first. Each byte within the memory array will be output in sequence. After address 7Fh in the memory array is transmitted, the internal address pointers will wrap around to the first memory loca tion (00h) and conti nue. The Bidirectional mode Clock (SCL) pin must be held high for the device to remain in the Transmit-only mode.

2.2 Initialization Procedure

After VCC has stabilized, the device will be in the Transmit -only mode. Nine clock cy cles on the VCL K pin must be given to the device for it to perform internal sychronization. During this period, the SDA pin will be in a high-impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit in address 00h. (Figure 2-2).

FIGURE 2-1: TRANSMIT-ONLY MODE

SCL

Tvaa Tvaa

SDA

Bit 1 (LSB)

VCLK

TvlowTvhigh

FIGURE 2-2: DEVICE INITIALIZATION

Vcc SCL

SDA

Tvpu

VCLK

12 891011

Null Bit

Bit 1 (MSB) Bit 7

Tvaa Tvaa

Bit 8 Bit 7High-impedance for 9 clock cycles

DS21160F-page 4  2003 Microchip Technology Inc.

24LC21A

3.0 BIDIRECTIONAL MODE

Before the 24LC21A can be switched into the Bidirectional mode (Figure3-1), it must enter the Transition mode, which is done by applying a valid high-to-low transition on the Bidirectional mode Clock (SCL). As soon it enters the Transition mode, it looks for a control byte 1010 000X on the I starts to count pulses on VCLK. Any high-to-low transition on the SCL line will reset the count. If it sees a pulse count of 128 on VCLK while the SCL line is idle, it will revert back to the Transmit-only mode, and transmit its contents starting with the Most Significant bit in address 00h. However, if it detects the control byte on the I in the Bidirectional mode. Once the device has made the transition to the Bidire ctiona l mode , the onl y way to switch the device back to the Transmit-only mode is to remove power from the device. The mode transition process is shown in detail in Figure3-3.

C™ bus, (Figure 3-2) it will switch to the

C™ bus, and

Once the device has switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bidirectional data transmission protocol (I protocol, a devic e that se nds dat a on the bus is define d to be the transmitter, and a device that receives data from the bus is defined to be the rece iver . The bus must be controlled by a master device that generates the Bidirectional mode Clock (SCL), co ntro ls access to th e bus and generates the Sta r t an d Stop co ndi tio ns, while the 24LC21A acts as the slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. In the Bidirectional mode, the 24LC21A only responds to commands for device 1010 000X.

FIGURE 3-1: MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE

MODE

Transmit

Only

Bidirectional

TVHZ

Recovery to Transmit-only mode

C™). In this

SCL

(MSB of data in 00h)

SDA

VCLK count =

VCLK

1 2 3 4 127 128

Bit8

FIGURE 3-2: SUCCESSFUL MODE TRANSITION TO BIDIRECTIONAL MODE

Transmit Only mode

MODE SCL

SDA VCLK count = 1 2 n 0

VCLK

Transition mode with possibility to return to Transmit-only mode

S1 0 1 0 0000 ACK

n < 128

Bidirectional

permanently

 2003 Microchip Technology Inc. DS21160F-page 5

24LC21A

FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA

The 24LC21A was designed to

Display Power-on

DDC Circuit Powered

from +5 volts

Communication

is idle

comply to the portion of flowchart insi de das h box

Is Vsync

present?

Yes

Send EDID continuously

using Vsync as clock

High-to-low

transition on

SCL?

Yes

Stop sending EDID.

Switch to DDC2 mode.

Display has

optional

transition state

Yes

Set Vsync counter = 0

or start timer

Change on

SCL, SDA or

VCLK lines?

Yes

High - low

transition on SCL

Yes

Reset Vsync counter = 0

Valid

DDC2 address

received?

VCLK

cycle?

Yes

Increment VCLK counter

(if appropriate)

Reset counter or timer

Yes

High-to-low

transition on

SCL?

Yes

DDC2 communication

idle. Display waiting for

address byte.

DDC2B address

received?

Is display

Access.bus

Valid Access.bus

See Access.bus

specification to determine

correct procedure.

capable?

Yes

address?

Yes

Respond to DDC2B

Receive DDC2B

command

Counter=128 or

timer expired?

Yes

Switch back to DDC1

mode.

Note 1: The base flowchart is cop yright  199 3, 1994, 1995 V ideo El ectroni c Standard Ass ociation (VESA) from

VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.

2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc. 3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A.

DS21160F-page 6  2003 Microchip Technology Inc.

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