MICROCHIP 24AA04, 24LC04B Technical data

24AA04/24LC04B

4K I2C™ Serial EEPROM

Device Selection Table

Part

Number

24AA04 1.8-5.5 400 kHz

24LC04B 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for VCC <2.5V

Vcc

Range

Max. Clock

Frequency

(1)

Temp.

Ranges

I

Features:

• Single supply with operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current, typical

-1μA standby current, typical (I-temp)

• Organized as 2 blocks of 256 bytes (2 x 256 x 8)

• 2-wire serial interface bus, I

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (24AA04) and 400 kHz (24LC04B)
compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 16 bytes

• Hardware write-protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP
packages

• 5-lead SOT-23 package

• Pb-free finish available

• Available for extended temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

2

C™ compatible

Description:

The Microchip Technology Inc. 24AA04/24LC04B
(24XX04*) is a 4 Kbit Electric all y Era sable PROM. Th e
device is organized as two blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX04 also has a page write
capability fo r up to 16 bytes of data. The 24X X04 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN and MSOP packages and is
also available in the 5-lead SOT-23 package.

Package Types

A0
A1

A2

SS

V

V

SOIC, TSSOP

1
2
3
4

1

A0

2

A1

3

A2

SS

4

DFN

8

V

CC

7

WP

6

SCL

5

SDA

CC

V

8

WP

7

SCL

6
5

SDA

PDIP, MSOP

1

A0

2

A1

3

A2

4

V

SS

SOT-23-5

15

SCL

2

Vss

3

SDA

Note: Pins A0, A1 and A2 are not used by the 24XX04. (No

internal connections).

8

VCC

7

WP

6

SCL

5

SDA

WP

4

Vcc

Block Diagram

HV

Generator

EEPROM

Array

Page

Latches

YDEC

I/O

SDA

I/O

Control

Logic

SCL

WP

Memory

Control

Logic

XDEC

V

CC

VSS

© 2005 Microchip Technology Inc. DS21708E-page 1

Sense Amp.
R/W Control

24AA04/24LC04B

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indica ted in the opera tional li stings of this sp ecification is not i mplied. Ex posure to maximum rating
conditions for extended periods may affect device reliability.

SS ......................................................................................................... -0.3V to VCC +1.0V

(†)

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

D1 V
D2 — High-level input voltage 0.7 V
D3 VIL Low-level input voltage — — 0.3 VCC V—
D4 VHYS Hysteresis of Schmitt

D5 V
D6 ILI Input leakage current ——±1μAVIN = VSS or VCC
D7 ILO Output leakage current ——±1μAVOUT = VSS or VCC
D8 CIN,

D9 I
D10 ICC read — 0.05 1 mA —
D11 ICCS Standby current —

Note: This parameter is periodically sampled and not 100% tested.

Sym. Characteristic Min. Typ. Max. Units Conditions

IH WP, SCL and SDA pins — ————

Trigger inputs

OL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V

Pin capacitance

OUT

C

CC write Operating current —0.13mAVCC = 5.5V, SCL = 400 kHz

(all inputs/outpu t s)

Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V
Automotive (E): T

CC ——V—

0.05 VCC ——V(Note)

——10pFVCC = 5.0V (Note)

—

A = -40°C to +125°C, VCC = +2.5V to +5.5V

A = 25°C, FCLK = 1 MHz

T

0.01
—

1
5

μAμAIndustrial

Automotive
SDA = SCL = VCC
WP = VSS

DS21708E-page 2 © 2005 Microchip Technology Inc.

24AA04/24LC04B

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

Param.

No.

1F

Sym. Characteristic Min. Typ. Max. Units Conditions

CLK Clock frequency —

2 THIGH Clock high time 600

3T

LOW Clock low time 1300

4TR SDA and SCL rise time

(Note 1)

5T

6T

7T

F SDA and SCL fall time — —

HD:STA Start condition hold time 600

SU:STA Start condition setup

time

8THD:DAT Data input hold time 0 —

9T

10 T

SU:DAT Data input setup time 100

SU:STO Stop condition setup

time

11 TAA Output valid from clock

(Note 2)

12 TBUF Bus free time: Time the

bus must be free before
a new transmission can
start

13 TOF Output fall time from VIH

minimum to V

IL

maximum

14 T

SP Input filter spike

suppression
(SDA and SCL pins)

15 TWC Write cycle time

(byte or page)
16 — Endurance 1M — — cycles 25°C, (Note 4)
Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The co mbine d T

SP and VHYS specifications are due to new Schmit t Trigger inputs w h ic h p rov id e i mp rov ed

noise spike suppression. This eliminates the need for a

4: This parameter is not tested but ensured by characterization. For endurance esti mates in a specific

application, please co nsult the Tota l Enduran ce™ Model whic h can be obt ain ed from Mi crochi p’ s web site
at www.microchip.com.

Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V
Automotive (E): T

—

4000

4700

—
—

A = -40°C to +125°C, VCC = +2.5V to +5.5V

—
—

—
—

—
—

—
—

400
100

—
—

—
—

300

1000

kHz 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

ns 2.5V ≤ VCC ≤ 5.5V (Note 1)

1.8V ≤ V

CC < 2.5V (24AA04)

(Note 1)

300 ns (Note 1)

—

4000

600

4700

—
—

—
—

—
—

—
—

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

—ns(Note 2)

—

250
600

4000

—
—

1300
4700

20+0.1C

—

—
—

—
—

—
—

—
—

B

—
—

—
—

—
—

900

3500

—
—

250
250

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

CC < 2.5V (24AA04)

ns 2.5V ≤ VCC ≤ 5.5V

1.8V ≤ V

ns 2.5V ≤ V

1.8V ≤ V

CC < 2.5V (24AA04)

CC ≤ 5.5V
CC < 2.5V (24AA04)

— — 50 ns (Notes 1 and 3)

——5ms—

TI specification for standard operation.

© 2005 Microchip Technology Inc. DS21708E-page 3

24AA04/24LC04B

FIGURE 1-1: BUS TIMING DATA

SCL

SDA

IN

SDA

OUT

5

3

7

6

14

2

FIGURE 1-2: BUS TIMING START/STOP

SCL

7

SDA

6

4

8

9

11

D4

10

12

10

Start Stop

DS21708E-page 4 © 2005 Microchip Technology Inc.

24AA04/24LC04B

2.0 FUNCTIONAL DESCRIPTION

The 24XX04 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus i s defined as t ransmitter, while a de vice
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX04 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable wheneve r the c lock lin e is high . Changes i n
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

3.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The ma ster devi ce m ust gener at e an ex tr a cloc k
pulse which is associated with this Acknowledge bit.

Note: The 24XX04 does not generate any

Acknowledge bits if an internal
programming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the sla ve by no t gene rating a n Ack nowl edge b it
on the last byte that has be en c loc ke d ou t of th e sl av e.
In this case, the sl ave (24 XX04) will leave the data lin e
high to enable the master to generate the Stop
condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

© 2005 Microchip Technology Inc. DS21708E-page 5

(A) (B) (D) (D) (A)(C)

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

24AA04/24LC04B

3.6 Device Addressi ng

A control byte is the first byte received following the
Star t condition from the m aster devi ce. The co ntrol byte
consists of a four-bit control code . For the 24XX04, thi s
is set as ‘
The next two bit s of the control by te are “don’t care s” for
the 24XX04. The last bit, B0, is used by the master
device to select which of the two 256-word blocks of
memory are to be accessed. This bit is, in effect, the
Most Significant bit of the word address.

The last bit of the control byte defines the operation to
be performed. When set to ‘
selected. When set to ‘
Following the Start condition, the 24XX04 monitors the
SDA bus checking the device type identifier being
transmitted and, upon receiving a ‘
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX04 will select a read or write operation.

Operation

1010’ binary for read and write operations.

1’, a read operation is

0’, a write operation is se lecte d.

1010’ code, the

Read
Write

Control

Code

1010

1010

Block Select R/W

Block Address
Block Address

1

0

FIGURE 3-2: CONTROL BYT E

ALLOCATION

Read/Write

Block

Control Code

10 10

S

Start Bit

x = “don’t care”

Slave Address

Select

Bits

xxB0

Acknowledge Bit

R/W

Bit

ACK

DS21708E-page 6 © 2005 Microchip Technology Inc.

24AA04/24LC04B

4.0 WRITE OPERATION

4.1 Byte Write

Following the Start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic low, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow once it has generated an Acknowledge b it during
the ninth clock cycl e. Therefore, th e next byte trans mit­ted by the master is the word address and will be
written into the Address Pointer of the 24XX04. After
receiving another Acknowledge signal from the
24XX04, the master device will transmit the data word
to be written into the addressed memory location. The
24XX04 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24XX04 will not
generate Acknowledge signals (Figure 4-1).

4.2 Page Wri te

The write control byte, word address and the first data
byte are transmitted to the 24 XX04 in th e same w ay a s
in a byte write. But instead of generating a Stop condi­tion the master transmits up to 16 data bytes to the
24XX04, which are temporarily stored in the on-chip
page buffer and will be written into memory once the
master has transmitted a Stop condition. Upon receipt
of each word, the four lowe r-order Add ress Poi nter bit s
are internally incremented by ‘
bits of the word addres s rem ai n con stant. If the master
should transmit m ore th an 16 words prior to ge neratin g
the Stop condition, the address counter will roll over
and the previously rec eived dat a will be overwritt en. As
with the byte wri te operatio n, once the S t op condi tion is
received an internal write cycle will begin (Figure 4-2).

Note: Page w rite operatio ns are limite d to writin g

bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buf fer size (or
‘page size’) an d end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next p age as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

1’. The higher-order 7

FIGURE 4-1: BYTE WRITE

Bus Activity
Master

SDA Line

Bus Activity

S
T
A
R
T

S P

x = “don’t care”

10

Control

Byte

10

x

Block

Select

Bits

Word

Address

x

0

B0

A
C
K

A
C
K

Data

S
T
O
P

A
C
K

FIGURE 4-2: PAGE WRITE

S
T

Bus Activity
Master

SDA Line

Bus Activity

x = “don’t care”

© 2005 Microchip Technology Inc. DS21708E-page 7

Control

A
R
T

S P

1

010

Byte

xx

Block

Select

Bits

B0

0

A
C
K

Word

Address (n)

Data (n) Data (n + 15)

A
C
K

Data (n + 1)

A
C
K

A
C
K

S
T
O
P

A
C
K

24AA04/24LC04B

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issu ed from the mas ter , the device
initiates the int ernally-timed wri te cycle and ACK pol ling
can then be initiated immediately. This involves the
master sending a S tart c ondition fo llowed by the contro l
byte for a Write c ommand (R/W
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 5-1 for a flow diagram of
this operation.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

= 0). If the device is still

6.0 WRITE PROTECTION

The WP pin a llows t he user to wri te-prot ect the entire
array (000-1FF) when the pin is tied to V

SS the write protection is disabled.

V

CC. If tied to

Send Start

Send Control Byte

with R/W

Acknowledge

(ACK = 0)?

= 0

Did Device

Yes

Next

Operation

No

DS21708E-page 8 © 2005 Microchip Technology Inc.