MICROCHIP 24LC01B, 24LC02B Technical data

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24LC01B/02B

1K/2K 2.5V I2C™ Serial EEPROM

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 10 µA standby current typical at 5.5V

- 5 µA standby current typical at 3.0V

• Organized as a single block of 128 bytes (128 x 8 ) -1K or 256 bytes (256 x 8) -2K

• 2-wire serial interface bus, I

C™ compatible

• 100 kHz (2.5V) and 400kHz (5.0V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• ESD protection > 3,000V

• 1,000,000 E/W cycles guaranteed

• Data retention > 200 years

• 8 pin DIP, SOIC, TSSOP* or SOT-23* package

• Available for temperature ranges

- Commercial (C): 0°C to +70°C

- Industrial (I): -40°C to +85°C

DESCRIPTION

The Microchip Technology Inc. 24LC01B and 24LC02B are 1K bit and 2K bit Electrically Er asab le PR OMs. Th e devices are organi zed as a single bloc k of 128 x 8 bit or 256 x 8 bit memory with a two wire serial interface . Low voltage des ign p ermits oper ation d ow n to 2 .5 v olt s with a standby and active currents of only 5 µA and 1 mA respectively. The 24LC01B and 24LC02B also have page-write capability for up to 8 bytes of data. The 24LC01B an d 24LC02B ar e available in the st andard 8-pin DIP and an 8-pin surface mount SOIC package. The SOT-23 and TSSOP packag es are av ailab le f or the 24LC01B.

PAC K AGE TYPES

PDIP, SOIC

Vss

TSSOP*

SOT-23*

SCL

VSS

SDA

* Available for 24LC01B only

BLOCK DIAGRAM

I/O

CONTROL

LOGIC

MEMORY

CONTROL

LOGIC

24LC01B/02B

Vcc

SCL

SDA

8 7 6

24LC01B

2 3

XDEC

Vcc

HV GENERATOR

EEPROM

PAGE LATCHES

ARRAY

Vcc WP SCL SDA

* Available for 24LC01B only

 1999 Microchip Technology Inc. DS20071J-page 1

SDA SCL

VSS

YDEC

SENSE AMP

R/W CONTROL

24LC01B/02B

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*

VCC...................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature.....................................-65°C to +150°C

Ambient temp. with power applied ................ - 65°C to +125°C

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins...................................... .......> 3 kV

*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

SS ............... -0.6V to VCC +1.0V

TABLE 1-1: PIN FUNCTION TABLE

Name Function

V SDA SCL

A0, A1, A2

Ground Serial Address/Data I/O Serial Clock Write Protect Input +2.5V to 5.5V Power Supply

No Internal Connection

TABLE 1-1: DC CHARACTERISTICS

VCC = +2.5V to +5.5V Commercial (C): Tamb = 0°C to +70°C

Industrial (I): Tamb = -40°C to +85°C

Parameter Symbol Min. Max. Units Conditions

WP, SCL and SDA pins:

High level input voltage Low level input voltage V Hysteresis of Schmidt trigger inputs V

Low level output voltage VOL .40 V IOL = 3.0 mA, VCC = 2.5V Input leakage current ILI -10 10 µA VIN = .1V to 5.5V Output leakage current I Pin capacitance (all inputs/outputs) CIN,

Operating current I

Standby current ICCS —30µAVCC = 3.0V, SDA = SCL = VCC

Note: This parameter is periodically sampled and not 100% tested.

IH .7 VCC V

IL .3 VCC V

HYS .05 VCC — V (Note)

LO -10 10 µA VOUT = .1V to 5.5V

—10pFVCC = 5.0V (Note 1)

OUT

CC Write — 3 mA VCC = 5.5V, SCL = 400 kHz

Tamb = 25°C, F

CLK = 1 MHz

ICC Read — 1 mA

100 µA VCC = 5.5V, SDA = SCL = VCC

WP = VSS

FIGURE 1-1: BUS TIMING START/STOP

SCL

SU:STA

SDA

START STOP

DS20071J-page 2  1999 Microchip Technology Inc.

THD:STA

VHYS

TSU:STO

TABLE 1-2: AC CHARACTERISTICS

24LC01B/02B

Parameter Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units Remarks

Min. Max. Min. Max.

Clock frequency F

CLK — 100 — 400 kHz

Clock high time THIGH 4000 — 600 — ns Clock low time T

LOW 4700 — 1300 — ns

SDA and SCL rise time TR — 1000 — 300 ns (Note 1) SDA and SCL fall time TF — 300 — 300 ns (Note 1) START condition hold time T

HD:STA 4000 — 600 — ns After this period the first

clock pulse is generated

START condition setup time T

SU:STA 4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

HD:DAT 0 — 0 — ns (Note 2)

Data input setup time TSU:DAT 250 — 100 — ns STOP condition setup time T

SU:STO 4000 — 600 — ns

Output valid from clock TAA — 3500 — 900 ns (Note 2) Bus free time TBUF 4700 — 1300 — ns Time the bus must be free

before a new transmission can start

Output fall time from VIH minimum to VIL maximum

Input filter spike suppression

OF — 250 20 +0.1

250 ns (Note 1), CB ð 100 pF

SP — 50 — 50 ns (Note 3)

(SDA and SCL pins) Write cycle time T

WR — 10 — 10 ms Byte or Page mode

Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This par am ete r i s no t tested but guaran teed by characterization. For endurance esti ma tes i n a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

FIGURE 1-2: BUS TIMING DATA

TLOW

SCL

TSU:STA

HD:STA

SDA

SDA OUT

 1999 Microchip Technology Inc. DS20071J-page 3

TSP

TAA

THD:STA

THIGH

TSU:STOTSU:DATTHD:DAT

TBUFTAA

24LC01B/02B

2.0 FUNCTIONAL DESCRIPTION

The 24LC01B/02B supports a bi-directional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), co ntrols th e bu s acce ss , and gen erates the START and STOP conditions, while the 24LC01B/02B works as slave. Both ma ster and slave can operate as transmitter or receiver but the master device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock li ne is HIGH will be interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH trans ition of the SDA line while the clock (SCL) is HI GH de termines a STOP con dit i on . A ll operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is det ermined by the master device and is theoreti cally u nlimited , althoug h only the las t sixteen will be store d wh en doi ng a write ope ratio n. Whe n an overwrite doe s occur it will r eplac e data in a fi rst in first out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.

Note: The 24LC01B/02B does not generate any

acknowledge bits if an internal programming cycle is in progress .

The device that acknowledges has to pull down the SDA line du ring the acknowledge cloc k pul se in such a way that the SDA line is stable LOW dur ing the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has be en clocke d out of the slav e. In thi s case, the slave must leave the data line H IGH to e nable the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(

A) (B) (D) (D) (C) (A)

SCL

SDA

START

CONDITION

DS20071J-page 4  1999 Microchip Technology Inc.

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

24LC01B/02B

3.6 Devise Address

The 24LC01B/02B are software-compatible with older devices such as 24C01A, 24C02A, 24LC01, and 24LC02. A single 2 4LC02B c an be us ed in pl ace of tw o 24LC01’s, for example, without any modifications to

software. The “c hip select” p ortion of the control byte becomes a don't care.

After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 24LC01B/02B, followed by three don't care bits.

The eighth bit of sla ve address d etermines if the master device wants to read or write to the 24LC01B/02B (Figure 3-2).

The 24LC01B/02B monitors th e b us f or its correspon ding slave add ress all th e time . It ge ner ates an ac kno wledge bit if the slave address was true and it is not in a programming mode.

Operation

Read Write

Control

Code

1010 1010

Chip

Select

XXX XXX

R/W

1 0

FIGURE 3-2: CONTROL BYTE

ALLOCATION

START

SLAVE ADDRESS

1 010XXX

X = Don’t care

READ/WRITE

R/W A

4.0 WRITE OPERATION

4.1 Byte Write

Following the start signal from the master, the device code (4 bits), the don't care bits (3 bits), and the R/W bit which is a logic low is placed ont o the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock c ycle. There fore t he next byte tran smitted b y the master is the word address and will be written into the address pointer of the 24LC01B/02B. After receiving another ac knowledge si gnal from the 24LC0 1B/02B the master devic e will trans mit the data w ord to be written into the addressed memory location. The 24LC01B/02B acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC01B/02B will not generate acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, word address and the first data byte are transmitted to the 24LC01B/02B in the same way as in a byte write. But instead of generating a stop condition the mast er tr ansmi ts up t o eight dat a b ytes to the 24LC01B/02B which are temporarily stored in the on-chip page b uff e r an d will be written into the me mory after the master has transmitted a stop condition. After the receipt of each w ord, th e three l ow er order a ddres s pointer bits are internally incremented by one. The higher order five bit s o f the word address remains constant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, on ce th e sto p co nd i ti o n is rece ived an in te r nal write cycle will begin (Figure 4-2).

 1999 Microchip Technology Inc. DS20071J-page 5

Note: Page write operations are limited to writing

bytes within a si ngle phys ical page, rega rdless of the number of bytes actually being written. Physical page boundaries start at addresses th at ar e i nte ge r mul t ip l es of t he page buff er siz e (o r ‘page siz e’ ) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beg inning of the curre nt page (overwriting data previously stored there), instead of bein g written t o the ne xt page a s might be expected. It is therefore necessary for the application softw ar e to pre v ent page write operations that would attempt to cross a page boundary.

24LC01B/02B

FIGURE 4-1: BYTE WRITE

BUS ACTIVITY MASTER

S T A R T

CONTROL

BYTE

WORD

ADDRESS

DATA

S T O P

SDA LINE

BUS ACTIVITY

S P

FIGURE 4-2: PAGE WRITE

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

S T

CONTROL

A R T

BYTE

S P

A C K

WORD

ADDRESS (n)

A C K

DA TAn + 1

A C K

DATA n DATAn + 7

A C K

S T O P

A C K

DS20071J-page 6  1999 Microchip Technology Inc.

24LC01B/02B

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated imme diately. This involves t he master sen ding a start condition followed by the control byte for a write command (R/W the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure5-1 for flow diagram.

= 0). If the device is still busy with

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Contr ol Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

Operation

6.0 WRITE PROTECTION

The 24LC01B/02B can be used as a se rial RO M when the WP pin is connected to V inhibited and the enti re memory will be write-p rotected.

CC. Programming will be

7.0 READ OPERATION

Read operations are initiated in the same way as write operations with the exceptio n that the R/W slave addr ess is set to one . There are th ree basic type s of read operatio ns: curren t address rea d, rando m read, and sequential read.

7.1 Current Address Read

The 24LC01B/02B contains an address counter that maintains the addr ess o f t he last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access da ta from address n + 1. Upon recei pt of the slave address with R/W 24LC01B/02B issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC01B/02B discontinues transmission (Figure 7-1).

bit set to one, the

7.2 Random Read

Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is don e by se nding the word address to th e 24LC01B/02B as part of a write operation. After the word address is se nt, the master ge nerates a start condition following t he acknowledge. This ter minates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W 02B will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfe r bu t does g enera te a stop con dition and the 24LC01B/02B discontinues transmission (Figure 7-2).

bit set to a one. The 24LC01B/

7.3 Sequential Read

Sequential reads are initiat ed in th e same w ay as a r andom read e xcep t th at a fter the 24LC01B/02B transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24LC01B/02B to transmit the next sequentially addressed 8-bit word (Figure 7-3).

T o provide sequential reads the 24LC01B/02B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows th e entire memory conten ts to be serially read during one operation.

7.4 Noise Protection

bit of the

 1999 Microchip Technology Inc. DS20071J-page 7

The 24LC01B/02B employs a VCC threshold detector circuit which dis ables the int ernal erase/write l ogic if the VCC is below 1.5 volts at nominal conditions.

The SCL and SD A inputs h av e Schm itt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.

24LC01B/02B

FIGURE 7-1: CURRENT ADDRESS READ

BUS ACTIVITY MASTER

T A R T

CONTROL

BYTE

DATA n

S T O P

SDA LINE

BUS ACTIVITY

FIGURE 7-2: RANDOM READ

S T

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

R T

S P

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n

A C K

S T

WORD

ADDRESS (n)

A R T

CONTROL

BYTE

DA TA n

A C K

DATA n + 1 DATA n + 2 DATA n + X

A C K

N O

A C K

S T O P

N O

A C K

S T O P

N O

A C K

8.0 PIN DESCRIPTIONS

8.1 SDA Serial Address/Data Input/Output

8.2 SCL Serial Clock

This input is used to synchro niz e the data t ra nsf e r from and to the device.

This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to V

CC (typical 10K¾ for 100 kHz, 2 K¾ for

400 kHz) . For normal data tr ansf er SD A is allo wed to c hange onl y

during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.

DS20071J-page 8  1999 Microchip Technology Inc.

8.3 WP

This pin must be connected to either VSS or VCC. If tied to V

(read/write the entire memory). If tied to V

entire memory will be write-pro tected. R ead oper ations are not affected.

SS, normal memory operation is enabled

CC, WRITE operations are inhibited. The

NOTES:

24LC01B/02B

 1999 Microchip Technology Inc. DS20071J-page 9

24LC01B/02B

NOTES:

DS20071J-page 10  1999 Microchip Technology Inc.

24LC01B/02B

24LC01B/02B PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24LC01B/02B — /P

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Package:

Temperature Blank = 0°C to +70°C

Range: I = -40°C to +85°C

Device:

SM = Plastic SOIC (207 mil Body), 8-lead

OT = SOT-23, 5-lead (24LC01B only)

ST = TSSOP, 8-lead (24LC01B only)

24LC01B 1K I2C Serial EEPROM

24LC01BT 1K I

24LC02B 2K I

24LC02BT 2K I

C Serial EEPROM (Tape and Reel)

C Serial EEPROM

C Serial EEPROM (Tape and Reel)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a par ticular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

 1999 Microchip Technology Inc. DS20071J-page 11

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Office

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ASIA/PACIFIC (continued)

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11/15/99

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro

devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 cer tified.

8-bit MCUs, KEELOQ

code hopping

Information contained in this publi c ation regarding device applications and the like is i nte nded for suggestion only and may be superseded by updates . No repr esentation or warranty is given and no liability is assumed by Microchip T echnology Incorpora ted with respect to the accuracy or use of such information, or infringe ment of patents or othe r intellec tual property rights arising from such use or otherwis e. Use of Microchi p’s produc ts as critical components in life s upport systems is not authorized except with expres s w ri t ten approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellect ual property rights. The Microchip logo and name are registered trademarks of Mi crochip Technology Inc. in the U.S. A. and other countries. All rights reserved. All other tradem arks mentioned herein are the property of their respective comp ani es .

 1999 Microchip Technology Inc.

MICROCHIP 24LC01B, 24LC02B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual