MICROCHIP 24AA256, 24LC256, 24FC256 Technical data

24AA256/24LC256/24FC256

256K I2C™ CMOS Serial EEPROM

Device Selection Table

Part

Number

VCC

Range

Max. Clock

Frequency

24AA256 1.8-5.5V 400 kHz
24LC256 2.5-5.5V 400 kHz I, E
24FC256 1.8-5.5V 1 MHz

(2)

Note 1: 100 kHz for VCC < 2.5V.

2: 400 kHz for VCC < 2.5V.

(1)

Temp.

Ranges

I

I

Features:

• Low-power CMOS technology:

- Maximum write current 3mA at 5.5V

- Maximum read current 400 μA at 5.5V

- Standby curren t 100 nA, typical at 5.5V

• 2-wire serial interface bus, I

• Cascadable for up to eight devices

• Self-timed erase/write cycle

• 64-byte Page Write mode available

• 5 ms max. write cycle time

• Hardware write-protect for entire array

• Output slope control to eliminate ground bounce

• Schmitt Trigger inputs for nois e suppression

• 1,000,000 erase/write cycles

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP, SOIC, TSSOP, MSOP and DFN
packages, 14-lead TSSOP package

• Pb-free finishes available

• Temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

2C™

compatible

Description:

The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device al so has a page write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, TSSOP, MSOP and DFN packages.

Block Diagram

A0 A1A2

I/O

SDA

I/O

Control

Logic

V

CC

VSS

SCL

Memory

Control

Logic

WP

XDEC

HV Generator

EEPROM

Array

Page Latches

YDEC

Sense Amp.
R/W Control

Package Types

PDIP/SOIC TSSOP/MSOP*

1

A0

2

A1

3

A2

SS

4

V

Note: * Pins A0 and A1 are no connects for the MSOP package only.

8

VCC
WP

7

SCL

6

24XX256

SDA

5

1

A0

2

A1

3

A2

4

V

SS

24XX256

8

CC

V

7

WP

6

SCL

5

SDA

A0
A1
A2

SS

V

*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.

© 2005 Microchip Technology Inc. DS21203N-page 1

DFN

1
2
3
4

8

VCC

7

WP

6

SCL

24XX256

5

SDA

24AA256/24LC256/24FC256

1.0 ELECTR ICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thes e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

Electrical Characteristics:

DC CHARACTERISTICS

Param.

No.

Sym. Characteristic Min. Max. Units Conditions

D1 — A0, A1, A2, SCL, SDA

and WP pins:
D2 V
D3 V

IH High-level input voltage 0.7 VCC —V—
IL Low-level input voltage — 0.3 VCC

D4 VHYS Hysteresis of Schmitt

Trigger inputs

(SDA, SCL pins)
D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5V

D6 ILI Input leakage current — ±1 μAVIN = VSS or VCC, WP = VSS

D7 ILO Output leakage current — ±1 μAVOUT = VSS or VCC
D8 CIN,

OUT

C

D9 I

CC Read Operating current — 400 μAVCC = 5.5V, SCL = 400 kHz

Pin capacitance

(all inputs/outpu t s)

ICC Write — 3 mA VCC = 5.5V

D10 ICCS Standby current — 1 μATA = -40°C to +85°C

Note: This parameter is periodically sampled and not 100% tested.

Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): V

CC = +2.5V to 5.5V TA = -40°C to +125°C

————

VVVCC ≥ 2.5V

0.2 VCC

CC < 2.5V

V

0.05 VCC —VVCC ≥ 2.5V (Note)

I

OL = 2.1 ma @ VCC = 2.5V

VIN = VSS or VCC, WP = VCC

—10pFVCC = 5.0V (Note)

A = 25°C, FCLK = 1 MHz

T

SCL = SDA = V
A0, A1, A2, WP = V

CC = 5.5V

SS

—5μATA = -40°C to +125°C

SCL = SDA = V
A0, A1, A2, WP = V

CC = 5.5V

SS

DS21203N-page 2 © 2005 Microchip Technology Inc.

24AA256/24LC256/24FC256

TABLE 1-2: AC CHARACTERISTICS

Electrical Characteristics:

AC CHARACTERISTICS

Param.

No.

1F

Sym. Characteristic Min. Max. Units Conditions

CLK Clock frequency —

2THIGH Clock high time 4000

3T

LOW Clock low time 4700

4TR SDA and SCL rise time

(Note 1)

5TF SDA and SCL fall time

(Note 1)

6T

HD:STA Start condition hold time 4000

7TSU:STA Start condition setup time 4700

8THD:DAT Data input hold time 0 — ns (Note 2)
9T

10 T

SU:DAT Data input setup time 250

SU:STO Stop condition setup time 4000

11 TSU:WP WP setup time 4000

12 THD:WP WP hold time 4700

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specificati ons ar e due to n ew Schmitt T rigger inputs , which p rovide im proved

noise spike suppression. This eliminates the need for a T

4: This parameter is not tested bu t ensured by characterization. For endurance estimates in a specific

application, ple ase consu lt the Tot al Endu rance™ M odel, wh ich can be obt ained fro m Microchi p’s web sit e
at www.microchip.com.

Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): V

—
—
—

600
600
500

1300
1300

500

—
—
—

—
—

600
600
250

600
600
250

100
100

600
600
250

600
600

1300
1300

CC = +2.5V to 5.5V TA = -40°C to +125°C

100
400
400

1000

—
—
—
—

—
—
—
—

1000

300
300

300
100

—
—
—
—

—
—
—
—

—
—
—

—
—
—
—

—
—
—

—
—
—

kHz 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC < 2.5V 24FC256
CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC < 2.5V 24FC256
CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC < 2.5V 24FC256
CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V 24FC256

ns All except, 24FC256

1.8V ≤ V

CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC < 2.5V 24FC256
CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

ns 1.8V ≤ V

2.5V ≤ V

1.8V ≤ V

CC ≤ 5.5V
CC < 2.5V 24FC256
CC ≤ 5.5V 24FC256

CC < 2.5V
CC ≤ 5.5V
CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC < 2.5V 24FC256
CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

I specification for standard operation.

CC ≤ 5.5V
CC ≤ 5.5V 24FC256

© 2005 Microchip Technology Inc. DS21203N-page 3

24AA256/24LC256/24FC256

Electrical Characteristics:

AC CHARACTERISTICS (Continued)

Param.

No.

Sym. Characteristic Min. Max. Units Conditions

13 TAA Output valid from clock

(Note 2)

14 TBUF Bus free time: Time the bus

must be free before a new
transmission can start

15 T

OF Output fall time from VIH

minimum to VIL maximum

B ≤ 100 pF

C

16 T

SP Input filt er spi ke su ppre ssion

(SDA and SCL pins)

17 T

WC Write cycle time (byte or

page)
18 — Endurance 1,000,000 — cycles 25°C (Note 4)
Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specific ations ar e due to n ew Schmitt T rigger inputs , which p rovide improved

noise spike suppression. This eliminates the need for a T

4: This parameter i s not tested bu t ensured by characterization. For en durance estimates in a spec ific

application, ple ase consu lt the Tot al Endu rance™ M odel, wh ich can be obt ained fro m Microchi p’s web sit e
at www.microchip.com.

Industrial (I): V
Automotive (E): V

—
—
—
—

4700
1300
1300

500

10 + 0.1CB 250

CC = +1.8V to 5.5V TA = -40°C to +85°C
CC = +2.5V to 5.5V TA = -40°C to +125°C

3500

900
900
400

—
—
—
—

ns 1.8 V ≤ VCC < 2.5V

2.5 V ≤ V

1.8V ≤ V

2.5 V ≤ V

CC ≤ 5.5V

CC < 2.5V 24FC256

CC ≤ 5.5V 24FC256

ns 1.8V ≤ VCC < 2.5V

2.5V ≤ V

1.8V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC < 2.5V 24FC256
CC ≤ 5.5V 24FC256

ns All except, 24FC256 (Note 1)

250

— 50 ns All except, 24FC256 (Notes 1

and 3)

—5ms—

I specification for standard operation.

FIGURE 1-1: BUS TIMING DATA

5

SCL

SDA
IN

SDA
OUT

WP

16

7

6

3

2

89

13

(protected)

(unprotected)

D4

4

10

14

11

12

DS21203N-page 4 © 2005 Microchip Technology Inc.

24AA256/24LC256/24FC256

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name

A0 1 1 1 — 1 User Configurable Chip Select
A1 2 2 2 — 2 User Configurable Chip Select
(NC) — — — 1, 2 — Not Connected
A2 3 3 3 3 3 User Configurable Chip Select

SS 44444Ground

V
SDA 5 5 5 5 5 Serial Data
SCL 6 6 6 6 6 Serial Clock
(NC) — — — — — Not Connected
WP 7 7 7 7 7 Write-Protect Input

CC 8 8 8 8 8 +1.8V to 5.5V (24AA256)

V

8-pin

PDIP

8-pin
SOIC

8-pin

TSSOP

8-pin

MSOP

8-pin

DFN

Function

+2.5V to 5 .5V (24LC256)
+1.8V to 5 .5V (24FC256)

2.1 A0, A1, A2 Chip Address Inputs

The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.

For the MSOP pac kage only, pins A0 and A 1 are not
connected.

Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either V

In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other pro grammabl e device, the chi p
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.

CC or VSS.

2.2 Serial Data (SDA)

This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
400kHz and 1MHz).

For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.

CC (typical 10 kΩ for 100 kHz, 2 kΩ for

2.3 Serial Clock (SCL)

This input is used to synchronize the data transfer to
and from the device.

2.4 Write-Protect (WP)

This pin must be conne cted to eithe r VSS or VCC. If tied

SS, write operations are enabled. If tied to VCC,

to V
write operations are inhibited but read operations are
not affected.

3.0 FUNCT IONAL DESCRIPTION

The 24XX256 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a sla ve. Both master and slave ca n
operate as a transmitter or receiver, but the master
device determines which mode is activated.

© 2005 Microchip Technology Inc. DS21203N-page 5

24AA256/24LC256/24FC256

4.0 BUS CHARAC TERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable wheneve r the c lock lin e is high . Changes i n
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.

4.3 Stop Data Transf er (C)

A low-to-high transition of the SDA li ne, while the cl ock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.

Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.

Note: The 24XX256 does not generate any

Acknowledge bits if an internal
programming cycle is in progress.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is sta ble low d uring the high pe riod of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master m ust s ignal an end of dat a to the sl ave
by NOT generating an Acknow ledge bit on the las t byte
that has been cl ocke d out o f the slave . In th is ca se , the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.

DS21203N-page 6 © 2005 Microchip Technology Inc.

24AA256/24LC256/24FC256

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (C) (A)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

FIGURE 4-2: ACKNOWLEDGE TIMING

SCL

SDA

Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.

Data from transmitter

Data

Allowed

to Change

Stop

Condition

Acknowledge

Bit

987654321 123

Data from transmitter

Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.

© 2005 Microchip Technology Inc. DS21203N-page 7

24AA256/24LC256/24FC256

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consi sts of a 4-bit contro l code. For the
24XX256, this is set as ‘
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1, A0). The Chip Select bits
allow the use of up to eight 24XX256 devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic lev els on the corresp onding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the thre e Most Signi ficant bit s of the word
address.

For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Figures 5-1 and 5-2) should be set to
‘0’. Only two 24XX256 MSOP packages can be
connected to the same bus.

The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bits are a
“don’t care.” The upper address bits are transferred
first, followed by the Less Significant bits.

Following the Start condition, the 24XX256 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘
priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W
write operation.

1010’ binary for read and write

1010’ code and appro-

bit, the 24XX256 will select a read or

FIGURE 5-1: CONTROL BYTE

FORMAT

Bit

Bits

ACKR/W

Acknowledge Bit

S

Start Bi t

Control Code

10

Chip Select

0 A2 A1 A0

1

Slave Address

Read/Write

5.1 Contiguous Addressing Across
Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to
expand the cont iguous addres s space for up to 2 Mbit
by adding up to eight 24XX256 devices on the same
bus. In this ca se, software ca n use A0 of the control
byte as address bit A15; A1 as address bit A16; an d A2
as address bit A17. It is not possible to sequentially
read across device boundaries.

For the MSOP package, up to two 24XX256 devices
can be added for up to 512 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A17. Bits A0 (A15) and A1 (A16) of the
control byte must always be set to a logic ‘0’ for the
MSOP.

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte Address High Byte Address Low Byte

A

A

1 010

Control

Code

DS21203N-page 8 © 2005 Microchip Technology Inc.

A2A1A

Chip

Select

Bits

R/W x

0

14

A

13

12

A11A10A

A

9

8

A

••••••

7

x = “don’t care” bit

A
0