MICROCHIP 24AA128, 24LC128, 24FC128 Technical data
24AA128/24LC128/24FC128
128K I2C™ CMOS Serial EEPROM
Device Selection Table
Part
Number
24AA128 1.8-5.5V 400 kHz
24LC128 2.5-5.5V 400 kHz I, E
24FC128 1.8-5.5V 1 MHz
Note 1: 100 kHz for VCC < 2.5V.
2: 400 kHz for VCC < 2.5V.
VCC
Range
Max. Clock
Frequency
(1)
(2)
Temp.
Ranges
I
I
Features
• Low-power CMOS technology:
- Maximum write current 3mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I
• Cascadable for up to eight devices
• Self-timed erase/write cycle
• 64-byte Page Write mode available
• 5 ms max write c ycle time
• Hardware write-protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt Trigger inputs for nois e suppression
• 1,000,000 erase/write cycles
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC, TSSOP, MSOP and DFN
packages, 14-lead TSSOP package
• Standard and Pb-free finishes available
• Temperature ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
2
C™ compatible
Description
The Microchip Technology Inc. 24AA128/24LC128/
24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial
Electrically Erasable PROM (EEPROM), capable of
operation across a broad voltage range (1.8V to 5.5V).
It has been developed for advanced, low-power
applications such as persona l com mun icati ons o r d at a
acquisition. This device also has a page write capability of up to 64 bytes of data. This device is capable of
both random and sequential reads up to the 128K
boundary. Functional address lines allow up to eight
devices on the same bus, for up to 1 Mbit address
space. This device is available in the standard 8-pin
plastic DIP, SOIC (150 and 208 mil), TSSOP, MSOP,
DFN and 14-lead TSSOP packages.
Block Diagram
I/O
SDA
C
ontrol
Logic
V
VSS
A0 A1 A2
I/O
SCL
CC
Memory
Control
Logic
WP
XDEC
HV Generator
EEPROM
Array
Page Latches
YDEC
Sense Amp.
R/W
Control
Package Types
1
2
3
4
5
6
7
TSSOP
24XX128
DFN
14
V
CC
13
WP
12
NC
11
NC
10
NC
9
SCL
8
SDA
1
A0
2
A1
3
A2
4
V
SS
8
VCC
24XX128
7
WP
6
SCL
5
SDA
PDIP/SOIC TSSOP/MSOP *
1
A0
2
A1
3
A2
SS
4
V
Note: * Pins A0 and A1 are no-connects for the MSOP package only.
24XX128
8
VCC
WP
7
SCL
6
SDA
5
1
A0
2
A1
3
A2
4
V
SS
8
24XX128
7
6
5
CC
V
WP
SCL
SDA
A0
A1
NC
NC
NC
A2
SS
V
*24XX128 is used in this document as a generic part number for the 24AA128/24LC128/24FC128 devices.
2004 Microchip Technology Inc. DS21191M-page 1
24AA128/24LC128/24FC128
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1: DC CHARACTERISTICS
Electrical Characteristics:
DC CHARACTERISTICS
Param.
No.
Sym. Characteristic Min. Max. Units Conditions
D1 — A0, A1, A2, SCL, SDA, and
WP pins:
D2 V
D3 V
IH High-level input voltage 0.7 VCC —V—
IL Low-level input voltage — 0.3 VCC
D4 VHYS Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)
D5 V
D6 I
OL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V
LI Input leakage current — ±1 µAVIN = VSS or VCC, WP = VSS
D7 ILO O utput leakage current — ±1 µAVOUT = VSS or VCC
D8 CIN,
OUT
C
Pin capacitance
(all inputs/outpu t s)
D9 ICC Read Operating current — 400 µAVCC = 5.5V, SCL = 400 kHz
CC Write — 3 mA VCC = 5.5V
I
D10 ICCS Standby current — 1 µATA = -40°C to +85°C
Note 1: This parameter is periodically sampled and not 100% tested.
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): V
CC = +2.5V to 5.5V TA = -40°C to 125°C
————
VVVCC ≥ 2.5V
0.2 VCC
CC < 2.5V
V
0.05 VCC —VVCC ≥ 2.5V (Note 1 )
OL = 2.1 mA @ VCC = 2.5V
I
VIN = VSS or VCC, WP = VCC
—10pFVCC = 5.0V (Note 1)
A = 25°C, fC = 1 MHz
T
SCL = SDA = V
A0, A1, A2, WP = V
CC = 5.5V
SS
—5µATA = -40°C to 125° C
SCL = SDA = V
A0, A1, A2, WP = V
CC = 5.5V
SS
DS21191M-page 2 2004 Microchip Technology Inc.
24AA128/24LC128/24FC128
TABLE 1-2: AC CHARACTERISTICS
Electrica l Characteristics:
AC CHARACTERISTICS
Param.
No.
1F
Sym. Characteristic Min. Max. Units Conditions
CLK Clock frequency —
2THIGH Clock high time 4000
3TLOW Cloc k low time 4700
4T
R SDA and SCL rise time
(Note 1)
5T
F SDA and SCL fall time
(Note 1)
6THD:STAStart condition hold time 4000
SU:ST
7T
A
Start condition setup time 4 700
8THD:DATData input hold time 0 — ns (Note 2)
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): V
—
—
—
600
600
500
1300
1300
500
—
—
—
—
—
600
600
250
600
600
250
CC = +2.5V to 5.5V TA = -40°C to 125°C
100
400
400
1000
—
—
—
—
—
—
—
—
1000
300
300
300
100
—
—
—
—
—
—
—
—
kHz 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
2.5V ≤ V
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
2.5V ≤ V
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
2.5V ≤ V
ns 1.8V ≤ V
2.5V ≤ V
1.8V ≤ V
ns All except, 24FC128
1.8V ≤ V
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
2.5V ≤ V
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
2.5V ≤ V
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
CC < 2.5V
CC ≤ 5.5V
CC ≤ 5.5V 24FC128
CC ≤ 5.5V 24FC128
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
9T
10 T
11 TSU:WP WP setup time 4000
SU:DA
T
SU:ST
O
Data input setup time 250
100
100
Stop condition setup time 4000
600
600
250
600
600
—
—
—
—
—
—
—
—
—
—
ns 1.8V ≤ V
2.5V ≤ V
1.8V ≤ V
CC < 2.5V
CC ≤ 5.5V
CC ≤ 5.5V 24FC128
ns 1.8 V ≤ VCC < 2.5V
2.5 V ≤ V
1.8V ≤ V
2.5 V ≤ V
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
CC ≤ 5.5V
CC ≤ 5.5V 24FC128
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
noise spike suppression. This eliminates the need for a T
SP and VHYS specifications are due t o new Schmitt Trigger inputs, whi ch prov ide im proved
I specification for standa rd opera tio n.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, pl ease consu lt the Total En durance™ Model, w hich c an be o btaine d from M icrochip ’s we b site:
www.microchip.com.
2004 Microchip Technology Inc. DS21191M-page 3
24AA128/24LC128/24FC128
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
Electrica l Characteristics:
AC CHARACTERISTICS
Param.
No.
Sym. Characteristic Min. Max. Units Conditions
12 THD:WP WP hold time 4700
13 T
AA Output valid from clock
(Note 2)
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
15 TOF Output fall time from VIH
minimum to VIL maximum
B ≤ 100 pF
C
16 TSP Input filter spike suppression
(SDA and SCL pins)
17 T
WC Write cycle time (byte or
page)
18 — Endurance 1,000,000 — cycles 25°C (Note 4)
Note 1: Not 100% tested. C
B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt Trigger inputs, whi ch prov ide im proved
noise spike suppression. This eliminates the need for a T
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, pl ease consu lt the Total En durance™ Model, w hich c an be o btaine d from M icrochip ’s we b site:
www.microchip.com.
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Automotive (E): V
1300
1300
—
—
—
—
4700
1300
1300
500
10 + 0.1CB 250
CC = +2.5V to 5.5V TA = -40°C to 125°C
—
—
—
3500
900
900
400
—
—
—
—
ns 1.8V ≤ V
2.5V ≤ V
1.8V ≤ V
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
2.5V ≤ V
ns 1.8V ≤ VCC < 2.5V
2.5V ≤ V
1.8V ≤ V
2.5V ≤ V
CC < 2.5V
CC ≤ 5.5V
CC ≤ 5.5V 24FC128
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
CC ≤ 5.5V
CC < 2.5V 24FC128
CC ≤ 5.5V 24FC128
ns All except, 24FC128 (Note 1)
250
24FC128 (Note 1)
— 50 ns All except, 24FC128 (Notes 1
and 3)
—5ms—
I specification for standard operation.
FIGURE 1-1: BUS TIMING DATA
5
SCL
SDA
IN
SDA
OUT
WP
DS21191M-page 4 2004 Microchip Technology Inc.
16
7
6
3
2
89
13
(protected)
(unprotected)
D4
4
10
14
11
12
24AA128/24LC128/24FC128
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name
A0 1 1 1 1 — 1 User Configurable Chip Select
A1 2 2 2 2 — 2 User Configurable Chip Select
(NC) — — — 3, 4, 5 1, 2 — Not Connected
A2 3 3 3 6 3 3 User Configurable Chip Select
SS 4 4 4 7 4 4 Ground
V
SDA 5 5 5 8 5 5 Serial Data
SCL 6 6 6 9 6 6 Serial Clock
(NC) — — — 10, 11,12 — — Not Connected
WP 7 7 7 13 7 7 Write-Protect Input
CC 8 8 8 14 8 8 +1.8V to 5.5V (24AA128)
V
8-pin
PDIP
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP pac kage only, pins A0 and A 1 are not
connected.
Up to eight devices (two fo r the MS OP packag e) may
be connected to the same bus by using different Chip
Select bit combi nations. If these p ins are left unconnected, the inputs will be pulled down internally to
SS. If they are tied to VCC or driven high, the internal
V
pull-down circuitr y is disab le d.
In most applications, the chip address inputs A0, A1,
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other pro grammabl e device, the chi p
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
400kHz and 1MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
CC (typical 10 kΩ for 100 kHz, 2 kΩ for
8-pin
SOIC
8-pin
TSSOP
14-pin
TSSOP
8-pin
MSOP
8-pin
DFN
Function
+2.5V to 5.5V (24LC128)
+1.8V to 5.5V (24FC128)
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4 Write-Protect (WP)
This pin can be connected to either VSS, VCC or left
floating. Internal pull-down circuitry on this pin will keep
the device in the un prot ected state if left floa tin g. If tie d
SS or left floating, normal memory operation is
to V
enabled (read/write the entire memory
If tied to V
operations are not affec ted.
CC, write operations are inhibited. Read
0000-3FFF).
3.0 FUNCTIONAL DESCRIPTION
The 24XX128 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
serial clock (SCL), controls the bus access and
generates the Start and Stop conditions while the
24XX128 works as a sla ve. Both master and slave ca n
operate as a transmitter or receiver, but the master
device determines which mode is activated.
2004 Microchip Technology Inc. DS21191M-page 5
24AA128/24LC128/24FC128
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable wheneve r the c lock lin e is high . Changes i n
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1 ).
4.1 Bus not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA li ne, while the cl ock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse, wh ich i s ass ociat ed with this A cknow ledg e
bit.
Note: The 24XX128 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is sta ble low d uring the high pe riod of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master m ust s ignal an end of dat a to the sl ave
by NOT generating an Acknow ledge bit on the las t byte
that has been cl ocke d out o f the slave . In th is ca se , the
slave (24XX128) will leave the data line high to enable
the master to generate the Stop condition.
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (C) (A)
SCL
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
FIGURE 4-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
SDA
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
987654321123
Data from transmitter
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Stop
Condition
DS21191M-page 6 2004 Microchip Technology Inc.
24AA128/24LC128/24FC128
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consi sts of a 4-bit contro l code. For the
24XX128, this is set as ‘
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1, A0). The Chip Select bits
allow the use of up to eight 24XX128 devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic lev els on the corresp onding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the thre e Most Signi ficant bit s of the word
address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Fig ures 5-1 and 5-2) should be set to
‘0’. Only two 24XX128 MSOP packages can be
connected to the same bus.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A13…A0 are used, t he upper two addres s bit s a re
“don’t care” bits . The upper addre ss bits ar e transferred
first, followed by the less significant bits.
Following the Start condition, the 24XX128 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘
appropriate devic e select b it s, th e slave d evice out put s
an Acknowledge si gnal on the SD A line. Dependi ng on
the state of the R/W
or write operation.
1010’ binary for read and write
1010’ code and
bit, the 24XX128 will select a read
FIGURE 5-1: CONTROL BYTE
FORMAT
Read/Write
Chip Select
Control Code
1 0 1 0 A2 A1 A0SACKR/W
Slave Address
Start Bit
Bit
Bits
Acknowledge Bit
5.1 Contiguous Addressing Across Multiple Devices
The Chip Select bits A2, A1,and A0 can be used to
expand the cont iguous addres s space for up to 1 Mbi t
by adding up to eight 24XX128s on the same bus. In
this case, software can use A0 of the control byte as
address bit A14; A1 as address bit A15; and A2 as
address bit A16. It is not possible to sequentially read
across device boundaries.
For the MSOP package, up to two 24XX128 devices
can be added for up to 256 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A16. Bits A0 (A14) and A1 (A15) of the
control byte must always be set to logic ‘0’ for the
MSOP.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte Address High Byte Address Low Byte
A
1010
Control
Code
2004 Microchip Technology Inc. DS21191M-page 7
A2A1A
Chip
Select
Bits
R/W XX
0
13
A
12
A11A10A
A
8
9
A
••••••
7
A
0
X = don’t care bit
24AA128/24LC128/24FC128
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits ), the Chi p Selec t (three b its) an d
the R/W bit (which i s a lo gic low) are cloc ked ont o the
bus by the master transmitter. This indicates to the
addressed slave rec eiver that the a ddress high byt e will
follow after it has generated an Acknowled ge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24XX128. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX128, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX128 acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX128 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the arra y with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2 Page Write
The write control byte, w ord add res s, and th e firs t da ta
byte are transmitted to th e 2 4XX1 28 in mu ch th e s am e
way as in a byte write. The exception is that instead of
generating a S t op cond ition, the maste r transm its up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower address
pointer bits are internally incremented by ‘
1’. If the
master should transmit more than 64 bytes prior to
generating the Stop condition, the address counter will
roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop
condition is received, an internal write cycle will begin
(Figure 6-2). If an attempt is made to write to the array
with the WP pin held high, the device w ill acknow ledg e
the command, but no write cy cle w ill occ ur, no data will
be written and the device will immed iately acc ept a new
command.
6.3 Write-Protection
The WP pin a llows t he user to wri te-prot ect the entire
array (0000-3FFF) when the pi n is tied to V
V
SS or left floating, the wri te protect ion i s disabl ed. Th e
WP pin is sampled at the Stop bit for every Write
command (Figure 1-1). Toggling the WP pin after the
Stop bi t wil l hav e no e ffe ct on t he ex ecutio n of th e wri te
cycle.
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer mu lti ple s of
[page size - 1]. If a Page Write
command attempts to write across a
physical page boundary, the result is
that the data wraps around to the
beginning of the current page (overwriting data previously stored there),
instead of being written to the next
page, as might be expected. It is,
therefore, necessary for the application software to prevent page write
operations that would attempt to cross
a page boundary.
CC. If tied to
FIGURE 6-1: BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
X = don’t care bit
S
T
Control
A
Byte
R
T
S1010 0
A1A
A
0
2
A
C
K
High Byte
XX
Address
A
C
K
Address
Low Byte
S
Data
A
C
K
T
O
P
P
A
C
K
FIGURE 6-2: PAGE WRITE
S
T
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
X = don’t care bit
DS21191M-page 8 2004 Microchip Technology Inc.
Control
A
Byte
R
T
S1010 0
A2A1A
0
A
C
K
XX
Address
High Byte
A
C
K
Address
Low Byte
Data Byte 0
A
C
K
A
C
K
Data Byte 63
S
T
O
P
P
A
C
K
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