MICROCHIP 24C02C Technical data



查询24C02C供应商

M

2K 5.0V I

FEATURES

• Single supply with operation from 4.5 to 5.5V

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

• Organized as a single block of 256 b ytes (256 x 8)

• Hardware write protection for upper half of array

• 2-wire serial interface bus, I

• 100 kHz and 400 kHz compatibility

• Page-write buffer for up to 16 bytes

• Self-timed write cycle (including auto-erase)

• Fast 1 mS write cycle time for byte or page mode

• Address lines allow up to eight devices on bus

• 1,000,000 erase/write cycles guaranteed

• ESD protection > 4,000V

• Data retention > 200 years

• 8-pin PDIP, SOIC or TSSOP packages

• Available for extended temperature ranges

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

- Automotive (E): -40 ° C to +125 ° C

2

C compatible

2

C

™

Serial EEPROM

PACKA GE TYPES

PDIP/SOIC

A0

A1

A2

Vss

TSSOP

A0
A1
A2

V

SS

24C02C

Vcc

24C02C

8

WP

7

SCL

6

SDA

5

8

VCC

7

WP

6

SCL

5

SDA

1

24C02C

2

3

4

1
2
3

4

DESCRIPTION

The Microchip Technology Inc. 24C02C is a 2K bit
Serial Electrically Erasable PROM with a voltage range
of 4.5V to 5.5V. The device is organized as a single
block of 256 x 8-bit memory with a 2-wire serial inter­face. Low current design permits operation with typical
standby and active currents of only 10 µ A and 1 mA
respectively. The device has a page-write capability for
up to 16 bytes of data and has fast write cycle times of
only 1 mS for both byte and page writes. Functional
address lines allow the connection of up to eight
24C02C devices on the same bus for up to 16K bits of
contiguous EEPROM memory. The device is available
in the standard 8-pin PDIP, 8-pin SOIC (150 mil), and
TSSOP packages.

BLOCK DIAGRAM

A0 A1 A2

I/O
Control
Logic

SDA

Vcc

Vss

SCL

WP

Memory
Control

Logic

XDEC

HV Generator

EEPROM
Array

Write Protect
Circuitry

YDEC

SENSE AMP
R/W CONTROL

2

I

C is a trademark of Philips Corporation.

1997 Microchip Technology Inc.

Preliminary

DS21202A-page 1

24C02C



µ

µ

µ

1.0 ELECTRICAL
CHARACTERISTICS

1.1 Maxim

V

........................................................................7.0V

CC

All inputs and outputs w.r.t. V

Storage temperature...........................-65˚C to +150˚C

Ambient temp. with power applied.......-65˚C to +125˚C

Soldering temperature of leads (10 seconds)...+300˚C

ESD protection on all pins ......................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

All parameters apply across the speci­fied operating ranges unless otherwise
noted.

SCL and SDA pins:

High level input voltage V
Low level input voltage V
Hysteresis of Schmitt trigger inputs V

Low level output voltage V
Input leakage current I
Output leakage current I

Pin capacitance (all inputs/outputs)

Operating current
Standby current I

Note : This parameter is periodically sampled and not 100% tested.

um Ratings*

......-0.6V to V

SS

Parameter Symbol Min. Max. Units Conditions

+1.0V

CC

V

= +4.5V to +5.5V

CC

Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

IH
IL

HYS

OL
LI

LO

IN

OUT

C

, C

I

CC

Read — 1 mA V
Write — 3 mA V

CC

I

CCS

CC

0.7 V
— 0.3 V

CC

0.05 V
— 0.40 V I

-10 10

-10 10
— 10 pF V

— 50

TABLE 1-1: PIN FUNCTION TABLE

Name Function

V

SS

SDA
SCL

CC

V

A0, A1, A2

WP

— V

CC

— V (Note)

Ground
Serial Data
Serial Clock
+4.5V to 5.5V Power Supply
Chip Selects
Hardware Write Protect

V

= 3.0 mA, Vcc = 4.5V

OL

IN

A V
A V

= 0.1V to 5.5V, WP = Vss

= 0.1V to 5.5V

OUT
CC

= 5.0V (Note)

Tamb = 25 ° C, f = 1 MHz

CC

= 5.5V, SCL = 400 kHz
= 5.5V

CC
CC

A V

= 5.5V, SDA = SCL = V

CC

DS21202A-page 2

Preliminary

1997 Microchip Technology Inc.



24C02C

TABLE 1-3: AC CHARACTERISTICS

All parameters apply across the specified oper­ating ranges unless otherwise noted.

Tamb > +85 ° C -40 ° C

Parameter Symbol

Min. Max. Min. Max.

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T

Output fall time from V
minimum to V

IL

IH

maximum

Input filter spike suppression

HIGH

LOW

HD

SU

HD
SU
SU

T

T

CLK

R

F

:

STA

STA

:

:

DAT
DAT

:
:

STO

AA

BUF

OF

SP

4000 — 600 — ns
4700 — 1300 — ns

4000 — 600 — ns After this period the first

4700 — 600 — ns Only relevant for repeated

4000 — 600 — ns

4700 — 1300 — ns Time the bus must be free

(SDA and SCL pins)
Write cycle time T

WR

Endurance 1M — 1M — cycles 25 ° C, V

Note 1: Not 100% tested. C

= total capacitance of one bus line in pF.

B

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined T

SP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

Vcc = 4.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C
Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

≤

Tamb

≤

+85 ° C

Units Remarks

— 100 — 400 kHz

— 1000 — 300 ns (Note 1)
— 300 — 300 ns (Note 1)

clock pulse is generated

START condition

0 — 0 — ns (Note 2)

250 — 100 — ns

— 3500 — 900 ns (Note 2)

before a new transmission
can start

— 250 20 + 0.1 C

250 ns (Note 1), C

B

B

— 50 — 50 ns (Note 3)

— 1.5 — 1 ms Byte or Page mode

CC

= 5.0V, Block

Mode (Note 4)

100 pF

≤

2:

3:

FIGURE 1-1: BUS TIMING DATA

TF

SCL

SDA
IN

SDA
OUT

1997 Microchip Technology Inc.

TSU:STA

TSP

TLOW

THD:STA

THIGH

THD:DAT TSU:DAT TSU:STO

TAA

TR

Preliminary

TBUF

DS21202A-page 3

24C02C

2.0 PIN DESCRIPTIONS

2.1 SDA Serial Data

This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
400 kHz).

For normal data transfer SD A is allow ed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.

2.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

2.3 A0, A1, A2

The levels on these inputs are compared with the cor­responding bits in the slave address. The chip is
selected if the compare is true.

Up to eight 24C02C devices may be connected to the
same bus by using different chip select bit combina­tions. These inputs must be connected to either V
V

SS.

CC (typical 10 kΩ for 100 kHz, 2 kΩ for

CC or

3.0 FUNCTIONAL DESCRIPTION

The 24C02C supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver . The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24C02C works
as slave. Both master and slave can operate as trans­mitter or receiver but the master device determines
which mode is activated.

2.4 WP

This is the hardware write protect pin. It must be tied to
V

CC or VSS. If tied to Vcc, the hardware write protection

is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled.

2.5 Noise Protection

The 24C02C employs a VCC threshold detector circuit
which disables the internal erase/write logic if the V
is below 3.8 volts at nominal conditions.

The SCL and SDA inputs hav e Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

CC

DS21202A-page 4 Preliminary  1997 Microchip Technology Inc.