MICROCHIP 24C01A, 24C02A Technical data



C 

24C01A/02A/04A

2

1K/2K/4K 5.0V I



C

Serial EEPROMs

FEATURES

• Low power CMOS technology

• Hardware write protect

• Two wire serial interface bus, I

• 5.0V only operation

• Self-timed write cycle (including auto-erase)

• Page-write buffer

• 1ms write cycle time for single byte

• 1,000,000 Erase/Write cycles guaranteed

• Data retention >200 years

• 8-pin DIP/SOIC packages

• Available for extended temperature ranges

- Commercial (C): 0˚C to +70˚C

- Industrial (I): -40˚C to +85˚C

- Automotive (E): -40˚C to +125˚C

2

compatible

DESCRIPTION

The Microchip Technology Inc. 24C01A/02A/04A is a
1K/2K/4K bit Electrically Erasable PROM. The device
is organized as shown, with a standard two wire serial
interface. Advanced CMOS technology allows a signif­icant reduction in power over NMOS serial devices. A
special feature in the 24C02A and 24C04A provides
hardware write protection for the upper half of the block.
The 24C01A and 24C02A have a page write capability
of two bytes and the 24C04A has a page length of eight
bytes. Up to eight 24C01A or 24C02A devices and up
to four 24C04A devices may be connected to the same
two wire bus.

This device offers fast (1ms) byte write and
extended (-40 ° C to 125 ° C) temperature operation. It
is recommended that all other applications use
Microchip’s 24LCXXB.

PACKA GE TYPES

DIP

8-lead
SOIC

14-lead
SOIC

* “TEST” pin in 24C01A

A0

1

A1

2

A2

3

V

4

SS

NC

A0
A1

NC

A2

NC

1
2

3

4

1
2
3
4

5
6

SS

7

A0
A1

A2

V

SS

V

BLOCK DIAGRAM

24C01A

24C02A

24C04A

24C01A

24C02A

24C04A

24C01A

24C02A

24C04A

14
13

11

12

10

V

8

CC

7

WP*

6

SCL

5

SDA

8

V

CC

7

WP*

6

SCL

5

SDA

NC

CC

V

WP
NC
SCL

9

SDA

8

NC

24C01A 24C02A 24C04A

Organization 128 x 8 258 x 8 2 x 256 x 8
Write Protect None 080-0FF 100-1FF
Page Write

Buffer

2

I

C is a trademark of Philips Corporation.

1996 Microchip Technology Inc. DS11183D-page 1

2 Bytes 2 Bytes 8 Bytes

Vcc
Vss

SDA

SCL

Data
Buffer
(FIFO)

Data Reg.

Slave Addr.

Control

Logic

A0 A1 A2 WP

Vpp R/W

A

P

d

o

d

i

r

n

A0 to

e

t

A7

s

e

s

r
Increment

Amp

Memory

Array

A8



24C01A/02A/04A

µ

µ

1.0 ELECTRICAL CHARA CTERISTICS

1.1 Maxim

CC

V

...................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

um Ratings*

SS

............... -0.6V to V

CC

+1.0V

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A0, A1, A2 Chip Address Inputs

V

SDA Serial Address/Data I/O

SCL Serial Clock

TEST (24C01A only) V

WP Write Protect Input

V

TABLE 1-2: DC CHARACTERISTICS

V

= +5V ( ± 10%) Commercial (C): Tamb = 0 ° C to +70 ° C

CC

Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol Min. Max. Units Conditions

V

CC

detector threshold V

SCL and SDA pins:

High level input voltage
Low level input voltage
Low level output voltage

A1 & A2 pins:

High level input voltage

Low level input voltage
Input leakage current I
Output leakage current I
Pin capacitance

(all inputs/outputs)
Operating current I

Standby current I
Note: This parameter is periodically sampled and not 100% tested

TH

V

IH

IL

V

V

OL

V

IH

IL

V

LI

LO

C

,

IN

C

OUT

CC

Write — 3.5 mA F

I

CC

Write — 4.25 mA F

I

CC

2.8 4.5 V

CC

V

x 0.7

-0.3

CC

V

+ 1

CC

V

x 0.3

0.4

CC

V

- 0.5

-0.3

CC

V

+ 0.5

0.5
—10
—10
— 7.0 pF V

— 750

Read

CCS

— 100

V
V
VI

V
V

µ

AV

µ

AV

AV

A SDA=SCL=V

A0 No Function for 24C04A only, Must

be connected to V

SS

CC

Ground

+5V Power Supply

OL

= 3.2 mA (SDA only)

= 0V to V

IN
OUT

= 0V to V

/V

IN

= 0V (Note)

OUT

CC

CC

CC

CC

or V

or V

SS

SS

Tamb = +25˚C, f = 1 MHz

CLK

= 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = 0˚C to +70˚C

CLK

= 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = (I) and (E)

= 5V, Tamb= (C), (I) and (E)

CC

CC

=5V (no PROGRAM active)

FIGURE 1-1: BUS TIMING START/STOP

SCL

TSU:STA

SDA

START STOP

DS11183D-page 2

THD:STA

VHYS

TSU:STO

1996 Microchip Technology Inc.



24C01A/02A/04A

TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Min. Typ Max. Units Remarks

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T
Data output delay time T
STOP condition setup time T
Bus free time T

Input filter time constant

HD

SU

HD

SU

SU

CLK
HIGH
LOW

R
F

:S

:S

:D
:D

AA

:S

BUF

T

I

TA

TA

AT
AT

TO

(SDA and SCL pins)
Program cycle time T

WC

Endurance — 1M — — cycles 25 ° C, Vcc = 5.0V, Block

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

— — 100 kHz
4000 — — ns
4700 — — ns

— — 1000 ns

— — 300 ns
4000 — — ns After this period the first

clock pulse is generated

4700 — — ns Only relevant for repeated

START condition

0—— ns
250 — — ns
300 — 3500

(Note 1)
4700 — — ns
4700 — — ns Time the bus must be free

before a new transmission

can start

— — 100 ns

— .4 1 ms Byte mode

.4N N ms Page mode, N=# of bytes

Mode (Note 2)

FIGURE 1-2: BUS TIMING DATA

TF

TLOW

SCL

TSU:STA

THD:STA

SDA

IN

SDA
OUT

TSP

TAA

THD:STA

THIGH

THD:DAT TSU:DAT

TAA

TR

TSU:STO

TBUF

1996 Microchip Technology Inc. DS11183D-page 3

24C01A/02A/04A

2.0 FUNCTIONAL DESCRIPTION

The 24C01A/02A/04A supports a bidirectional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener­ates the START and STOP conditions, while the
24C01A/02A/04A works as slave. Both master and
slave can operate as transmitter or receiver but the
master device determines which mode is activated.

Up to eight 24C01/24c02s can be connected to the bus,
selected by the A0, A1 and A2 chip address inputs. Up
to four 24C04As can be connected to the bus, selected
by A1 and A2 chip address inputs. A0 must be tied to
V

CC or VSS for the 24C04A. Other devices can be con-

nected to the bus but require different device codes
than the 24C01A/02A/04A (refer to section Slave
Address).

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24C01A/02A/04A does not generate

any acknowledge bits if an internal pro­gramming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (A)(C)

SCL

SDA

START

CONDITION

DS11183D-page 4  1996 Microchip Technology Inc.

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

24C01A/02A/04A

4.0 SLAVE ADDRESS

The chip address inputs A0, A1 and A2 of each 24C01A/
02A/04A must be externally connected to either V
ground (V
unique address. A0 is not used on the 24C04A and
must be connected to either V
24C01A or 24C02A devices and up to four 24C04A
devices may be connected to the bus. Chip selection is
then accomplished through software by setting the bits
A0, A1 and A2 of the slave address to the corresponding
hard-wired logic levels of the selected 24C01A/02A/04A.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24C01A/02A/04A, followed by the
chip address bits A0, A1 and A2. In the 24C04A, the
seventh bit of that byte (A0) is used to select the upper
block (addresses 100—1FF) or the lower block
(addresses 000—0FF) of the array.

The eighth bit of slave address determines if the master
device wants to read or write to the 24C01A/02A/04A
(Figure 4-1).

The 24C01A/02A/04A monitors the bus for its corre­sponding slave address all the time. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.

SS), assigning to each 24C01A/02A/04A a

CC or VSS. Up to eight

CC or

FIGURE 4-1: SLAVE ADDRESS

ALLOCATION

STAR T READ/WRITE

SLAVE ADDRESS

1010A2A1A0

R/W A

5.0 BYTE PROGRAM MODE

In this mode, the master sends addresses and one data
byte to the 24C01A/02A/04A.

Following the STAR T signal from the master , the device
code (4-bits), the slave address (3-bits), and the R/W
bit, which is logic LOW, are placed onto the bus by the
master. This indicates to the addressed 24C01A/02A/
04A that a byte with a word address will follow after it
has generated an acknowledge bit. Therefore the next
byte transmitted by the master is the word address and
will be written into the address pointer of the 24C01A/
02A/04A. After receiving the acknowledge of the
24C01A/02A/04A, the master device transmits the data
word to be written into the addressed memory location.
The 24C01A/02A/04A acknowledges again and the
master generates a STOP condition. This initiates the
internal programming cycle of the 24C01A/02A/04A
(Figure 6-1).

6.0 PAGE PROGRAM MODE

To program the 24C01A/02A/04A, the master sends
addresses and data to the 24C01A/02A/04A which is
the slave (Figure 6-1 and Figure 6-2). This is done by
supplying a START condition followed by the 4-bit
device code, the 3-bit slave address, and the R/W
which is defined as a logic LOW for a write. This indi­cates to the addressed slave that a word address will
follow so the slave outputs the acknowledge pulse to
the master during the ninth clock pulse. When the word
address is received by the 24C01A/02A/04A, it places
it in the lower 8 bits of the address pointer defining
which memory location is to be written. (The A0 bit
transmitted with the slave address is the ninth bit of the
address pointer for the 24C04A). The 24C01A/02A/04A
will generate an acknowledge after every 8-bits
received and store them consecutively in a RAM buffer
until a STOP condition is detected. This STOP condi­tion initiates the internal programming cycle. The RAM
buffer is 2 bytes for the 24C01A/02A and 8 bytes for the
24C04A. If more than 2 bytes are transmitted by the
master to the 24C01A/02A, the device will not acknowl­edge the data transfer and the sequence will be
aborted. If more than 8 bytes are transmitted by the
master to the 24C04A, it will roll over and overwrite the
data beginning with the first received byte. This does
not affect erase/write cycles of the EEPROM array and
is accomplished as a result of only allowing the address
registers bottom 3 bits to increment while the upper 5
bits remain unchanged.

If the master generates a STOP condition after trans­mitting the first data word (Point ‘P’ on Figure 6-1), byte
programming mode is entered.

The internal, completely self-timed PROGRAM cycle
starts after the STOP condition has been generated by
the master and all received data bytes in the page
buffer will be written in a serial manner.

The PROGRAM cycle takes N milliseconds, whereby N
is the number of received data bytes (N max = 8 for
24C04A, 2 for 24C01A/02A).

bit

 1996 Microchip Technology Inc. DS11183D-page 5

24C01A/02A/04A

FIGURE 6-1: BYTE WRITE

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T
A
R
T

S P

CONTROL

BYTE

A
C
K

FIGURE 6-2: PAGE WRITE

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

S P

A
C
K

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send­ing a start condition followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 7-1 for flow diagram.

= 0). If the device is still busy with

WORD

ADDRESS

A
C
K

DATA n DATA n + 7

A
C
K

A
C
K

DATA n + 1

DATA

A
C
K

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

S
T
O
P

A
C
K

S
T
O
P

A
C
K

Send Control Byte

with R/W = 0

Did Device

Acknowledge

NO

(ACK = 0)?

YES

Next

Operation

DS11183D-page 6  1996 Microchip Technology Inc.

24C01A/02A/04A

8.0 WRITE PROTECTION

Programming of the upper half of the memory will not
take place if the WP pin of the 24C02A or 24C04A is
connected to V

CC (+5.0V). The device will accept slave

and word addresses but if the memory accessed is
write protected by the WP pin, the 24C02A/04A will not
generate an acknowledge after the first byte of data has
been received, and thus the program cycle will not be
started when the STOP condition is asserted. Polarity
of the WP pin has no effect on the 24C01A.

9.0 READ MODE

This mode illustrates master device reading data from
the 24C01A/02A/04A.

As can be seen from Figure 9-2 and Figure 9-3, the
master first sets up the slave and word addresses by
doing a write. (Note: Although this is a read mode, the
address pointer must be written to). During this period
the 24C01A/02A/04A generates the necessary
acknowledge bits as defined in the appropriate section.

FIGURE 9-1: CURRENT ADDRESS READ

S

BUS ACTIVITY
MASTER

T
A
R
T

CONTROL

BYTE

The master now generates another START condition
and transmits the slave address again, except this time
the read/write bit is set into the read mode. After the
slave generates the acknowledge bit, it then outputs
the data from the addressed location on to the SDA pin,
increments the address pointer and, if it receives an
acknowledge from the master, will transmit the next
consecutive byte. This auto-increment sequence is
only aborted when the master sends a STOP condition
instead of an acknowledge.

Note 1: If the master knows where the address

pointer is, it can begin the read sequence
at the current address (Figure 9-1) and
save time transmitting the slave and word
addresses.

Note 2: In all modes, the address pointer will not

increment through a block (256 byte)
boundary, but will rotate back to the first
location in that block.

S

DATA n

T
O
P

SDA LINE

BUS ACTIVITY

FIGURE 9-2: RANDOM READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T

CONTROL

A

BYTE

R
T

S P

SP

WORD

ADDRESS (n)

A
C
K

S
T
A
R
T

CONTROL

BYTE

DATA (n)

N
O

A
C
K

S
T
O
P

S

A
C
K

A
C
K

A
C
K

N
O

A
C
K

 1996 Microchip Technology Inc. DS11183D-page 7

24C01A/02A/04A

FIGURE 9-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

S
T
O
P

SDA LINE

BUS ACTIVITY

A
C
K

A
C
K

10.0 PIN DESCRIPTION

10.1 A0, A1, A2 Chip Address Inputs

The levels on these inputs are compared with the cor­responding bits in the slave address. The chip is
selected if the compare is true. For 24C04 A0 is no
function.

Up to eight 24C01A/02A's or up to four 24C04A's can
be connected to the bus.

These inputs must be connected to either V

10.2 SDA Serial Address/Data Input/Output

This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

For normal data transfer, SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi­tions.

CC (typical 10KΩ).

SS or VCC.

P

A
C
K

A
C
K

N
O

A
C
K

This feature allows the user to assign the upper half of
the memory as ROM which can be protected against
accidental programming. When write is disabled, slave
address and word address will be acknowledged but
data will not be acknowledged.

Note 1: A “page” is defined as the maximum num-

ber of bytes that can be programmed in a
single write cycle. The 24C04A page is 8
bytes long; the 24C01A/02A page is 2
bytes long.

Note 2: A “block” is defined as a continuous area

of memory with distinct boundaries. The
address pointer can not cross the bound­ary from one block to another. It will how­ever, wrap around from the end of a block
to the first location in the same block. The
24C04A has two blocks, 256 bytes each.
The 24C01A and 24C02A each have only
one block.

10.3 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

10.4 WP Write Protection

This pin must be connected to either VCC or VSS for
24C02A or 24C04A. It has no effect on 24C01A.

If tied to V
memory block will not be executed. Read operations
are possible.

If tied to V
(read/write the entire memory).

DS11183D-page 8  1996 Microchip Technology Inc.

CC, PROGRAM operations onto the upper

SS, normal memory operation is enabled

NOTES:

24C01A/02A/04A

 1996 Microchip Technology Inc. DS11183D-page 9

24C01A/02A/04A

NOTES:

DS11183D-page 10  1996 Microchip Technology Inc.

24C01A/02A/04A

24C01A/02A/04A Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24C01A/02A/04A - /P

Package: P = Plastic DIP

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead, 24C04A only

Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C

E = -40°C to +125°C

2

Device: 24C01A 1K I

24C01AT 1K I

24C02A 2K I

24C02AT 2K I

24C04A 4K I

24C04AT 4K I

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

2

C Serial EEPROM

2

C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. DS11183D-page 11

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Singapore 188980
Tel: [phone] Fax: [phone]

Taiwan, R.O.C

Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: [phone] Fax: [phone]

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Y okohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

9/3/96

All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS11183D-page 12  1996 Microchip Technology Inc.