MICROCHIP 24C01A, 24C02A Technical data



C 

24C01A/02A/04A

2

1K/2K/4K 5.0V I



C

Serial EEPROMs

FEATURES

• Low power CMOS technology

• Hardware write protect

• Two wire serial interface bus, I

• 5.0V only operation

• Self-timed write cycle (including auto-erase)

• Page-write buffer

• 1ms write cycle time for single byte

• 1,000,000 Erase/Write cycles guaranteed

• Data retention >200 years

• 8-pin DIP/SOIC packages

• Available for extended temperature ranges

- Commercial (C): 0˚C to +70˚C

- Industrial (I): -40˚C to +85˚C

- Automotive (E): -40˚C to +125˚C

2

compatible

DESCRIPTION

The Microchip Technology Inc. 24C01A/02A/04A is a
1K/2K/4K bit Electrically Erasable PROM. The device
is organized as shown, with a standard two wire serial
interface. Advanced CMOS technology allows a signif­icant reduction in power over NMOS serial devices. A
special feature in the 24C02A and 24C04A provides
hardware write protection for the upper half of the block.
The 24C01A and 24C02A have a page write capability
of two bytes and the 24C04A has a page length of eight
bytes. Up to eight 24C01A or 24C02A devices and up
to four 24C04A devices may be connected to the same
two wire bus.

This device offers fast (1ms) byte write and
extended (-40 ° C to 125 ° C) temperature operation. It
is recommended that all other applications use
Microchip’s 24LCXXB.

PACKA GE TYPES

DIP

8-lead
SOIC

14-lead
SOIC

* “TEST” pin in 24C01A

A0

1

A1

2

A2

3

V

4

SS

NC

A0
A1

NC

A2

NC

1
2

3

4

1
2
3
4

5
6

SS

7

A0
A1

A2

V

SS

V

BLOCK DIAGRAM

24C01A

24C02A

24C04A

24C01A

24C02A

24C04A

24C01A

24C02A

24C04A

14
13

11

12

10

V

8

CC

7

WP*

6

SCL

5

SDA

8

V

CC

7

WP*

6

SCL

5

SDA

NC

CC

V

WP
NC
SCL

9

SDA

8

NC

24C01A 24C02A 24C04A

Organization 128 x 8 258 x 8 2 x 256 x 8
Write Protect None 080-0FF 100-1FF
Page Write

Buffer

2

I

C is a trademark of Philips Corporation.

1996 Microchip Technology Inc. DS11183D-page 1

2 Bytes 2 Bytes 8 Bytes

Vcc
Vss

SDA

SCL

Data
Buffer
(FIFO)

Data Reg.

Slave Addr.

Control

Logic

A0 A1 A2 WP

Vpp R/W

A

P

d

o

d

i

r

n

A0 to

e

t

A7

s

e

s

r
Increment

Amp

Memory

Array

A8



24C01A/02A/04A

µ

µ

1.0 ELECTRICAL CHARA CTERISTICS

1.1 Maxim

CC

V

...................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

um Ratings*

SS

............... -0.6V to V

CC

+1.0V

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A0, A1, A2 Chip Address Inputs

V

SDA Serial Address/Data I/O

SCL Serial Clock

TEST (24C01A only) V

WP Write Protect Input

V

TABLE 1-2: DC CHARACTERISTICS

V

= +5V ( ± 10%) Commercial (C): Tamb = 0 ° C to +70 ° C

CC

Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol Min. Max. Units Conditions

V

CC

detector threshold V

SCL and SDA pins:

High level input voltage
Low level input voltage
Low level output voltage

A1 & A2 pins:

High level input voltage

Low level input voltage
Input leakage current I
Output leakage current I
Pin capacitance

(all inputs/outputs)
Operating current I

Standby current I
Note: This parameter is periodically sampled and not 100% tested

TH

V

IH

IL

V

V

OL

V

IH

IL

V

LI

LO

C

,

IN

C

OUT

CC

Write — 3.5 mA F

I

CC

Write — 4.25 mA F

I

CC

2.8 4.5 V

CC

V

x 0.7

-0.3

CC

V

+ 1

CC

V

x 0.3

0.4

CC

V

- 0.5

-0.3

CC

V

+ 0.5

0.5
—10
—10
— 7.0 pF V

— 750

Read

CCS

— 100

V
V
VI

V
V

µ

AV

µ

AV

AV

A SDA=SCL=V

A0 No Function for 24C04A only, Must

be connected to V

SS

CC

Ground

+5V Power Supply

OL

= 3.2 mA (SDA only)

= 0V to V

IN
OUT

= 0V to V

/V

IN

= 0V (Note)

OUT

CC

CC

CC

CC

or V

or V

SS

SS

Tamb = +25˚C, f = 1 MHz

CLK

= 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = 0˚C to +70˚C

CLK

= 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = (I) and (E)

= 5V, Tamb= (C), (I) and (E)

CC

CC

=5V (no PROGRAM active)

FIGURE 1-1: BUS TIMING START/STOP

SCL

TSU:STA

SDA

START STOP

DS11183D-page 2

THD:STA

VHYS

TSU:STO

1996 Microchip Technology Inc.



24C01A/02A/04A

TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Min. Typ Max. Units Remarks

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T
Data output delay time T
STOP condition setup time T
Bus free time T

Input filter time constant

HD

SU

HD

SU

SU

CLK
HIGH
LOW

R
F

:S

:S

:D
:D

AA

:S

BUF

T

I

TA

TA

AT
AT

TO

(SDA and SCL pins)
Program cycle time T

WC

Endurance — 1M — — cycles 25 ° C, Vcc = 5.0V, Block

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

— — 100 kHz
4000 — — ns
4700 — — ns

— — 1000 ns

— — 300 ns
4000 — — ns After this period the first

clock pulse is generated

4700 — — ns Only relevant for repeated

START condition

0—— ns
250 — — ns
300 — 3500

(Note 1)
4700 — — ns
4700 — — ns Time the bus must be free

before a new transmission

can start

— — 100 ns

— .4 1 ms Byte mode

.4N N ms Page mode, N=# of bytes

Mode (Note 2)

FIGURE 1-2: BUS TIMING DATA

TF

TLOW

SCL

TSU:STA

THD:STA

SDA

IN

SDA
OUT

TSP

TAA

THD:STA

THIGH

THD:DAT TSU:DAT

TAA

TR

TSU:STO

TBUF

1996 Microchip Technology Inc. DS11183D-page 3

24C01A/02A/04A

2.0 FUNCTIONAL DESCRIPTION

The 24C01A/02A/04A supports a bidirectional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener­ates the START and STOP conditions, while the
24C01A/02A/04A works as slave. Both master and
slave can operate as transmitter or receiver but the
master device determines which mode is activated.

Up to eight 24C01/24c02s can be connected to the bus,
selected by the A0, A1 and A2 chip address inputs. Up
to four 24C04As can be connected to the bus, selected
by A1 and A2 chip address inputs. A0 must be tied to
V

CC or VSS for the 24C04A. Other devices can be con-

nected to the bus but require different device codes
than the 24C01A/02A/04A (refer to section Slave
Address).

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24C01A/02A/04A does not generate

any acknowledge bits if an internal pro­gramming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (A)(C)

SCL

SDA

START

CONDITION

DS11183D-page 4  1996 Microchip Technology Inc.

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION