MICROCHIP 24AA32A, 24LC32A Technical data

24AA32A/24LC32A

)

32K I2C™ Serial EEPROM

Device Selection Table

Part

Number

24AA32A 1.8-5.5 400kHz
24LC32A 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for VCC <2.5V

VCC

Range

Max Clock
Frequency

(1)

Temp

Ranges

I

Features

• Single supply with operation down to 1.8V

• Low-power CMOS technology

- 1 mA active current typical

-1µA standby current (max.) (I-temp)

• Organized as 4 blocks of 8K bits (32K bit)

• 2-wire serial interface bus, I

• Cascadable for up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (<2.5V) and 400 kHz (≥2.5V)
compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 32 bytes

• 2 ms typical write cycle time for page write

• Hardware write-protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP and MSOP packages

• Standard and Pb-free finishes available

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

2

C™ compatible

Description

The Microchip Technology Inc. 24AA32A/24LC32A
(24XX32A*) is a 32 Kbit Electrically Erasable PROM.
The device is organized as four blocks of 8K x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby
and active currents of only 1 µA and 1 mA,
respectively. It has been developed for advanced, low­power applications such as personal communications
or data acquisit ion. The 24XX32A also has a page wri te
capability for up to 32 bytes of dat a. Function al address
lines allow up to eight devices on the same bus, for up
to 256 Kbits address space. The 24XX32A is available
in the standard 8-pin PDIP, surface mount SOIC,
TSSOP and MSOP packages.

Package Types

PDIP/SOIC/TSSOP/MSOP

A0
A1
A2

Vss

1
2
3
4

24XX32

8

Vcc

7

WP

6

SCL

5

SDA

ROTATED TSSOP

(24AA32AX/24LC32AX

24XX32X

WP
Vcc

A0
A1

1
2
3
4

8
7
6
5

SCL
SDA
Vss
A2

Block Diagram

A0

Control

Logic

I/O

SDA

I/O

A1WPA2

Memory
Control

Logic

SCL

XDEC

HV Generator

EEPROM

Array

Page Latches

YDEC

Vcc

SS

V

*24XX32A is used in this document as a generic part number for the 24AA32A/24LC32A devices.

 2003 Microchip Technology Inc. DS21713D-page 1

Sense Amp.

R/W Control

24AA32A/24LC32A

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indica ted in the opera tional li stings of this sp ecification is not i mplied. Ex posure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

CC = +1.8V to +5.5V

V

DC CHARACTERISTICS

Param.

No.

D1 V

Symbol Characteristic Min Typ Max Units Conditions

IH WP, SCL and SDA pins — ————

D2 — High-level input voltage 0.7 VCC ——V—
D3 VIL Low-level input voltage — — 0.3 VCC V—
D4 V

HYS Hysteresis of Schmitt

Trigger inputs
D5 V
D6 I

OL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V

LI Input leakage current ——±1µAVIN =.1V to VCC

D7 ILO Output leakage current ——±1µAVOUT =.1V to VCC
D8 CIN,

C

OUT

Pin capacitance

(all inputs/outpu t s)
D9 ICC write Operating current —0.13mAVCC = 5.5V, SCL = 400 kHz
D10 ICC read — 0.05 1 mA —
D11 I

CCS Standby current —

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical measurements taken at room temperature.

Industrial (I): T
Automotive (E): T

A = -40°C to +85°C
A = -40°C to +125°C

0.05 VCC ——V(Note 1)

——10pFVCC = 5.0V (Note 1)

T

A = 25°C, FCLK = 1 MHz

—

0.01
—

1
5

µAµAIndustrial

Automotive
SDA = SCL = V
WP = VSS

CC

DS21713D-page 2  2003 Microchip Technology Inc.

24AA32A/24LC32A

TABLE 1-2: AC CHARACTERISTICS

CC = +1.8V to +5.5V

V

AC CHARACTERISTICS

Param.

No.

1F

Symbol Characteristic Min Max Units Conditions

CLK Clock frequency —

2 THIGH Clock high time 600

3TLOW Clock low time 1300

4T

R SDA and SCL rise time

(Note 1)

5TF SDA and SCL fall time — 300 ns (Note 1)
6T

HD:STA Start condition hold time 600

7TSU:STA Start condition setup time 600

8THD:DAT Data input hold time 0 — ns (Note 2)
9TSU:DAT Data input setup time 100

10 TSU:STO Stop condition setup time 600

11 T

AA Output valid from clock

(Note 2)

12 TBUF Bus free time: Time the bus

must be free before a new
transmissi on can start

13 T

OF Output fall time from VIH

minimum to V

IL maximum

14 TSP Input filter spike suppression

(SDA and SCL pins)

15 T

WC Write cycle time (byte or

page)
16 — Endurance 1M — cycles 25°C, (Note 4)
Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specificat io ns are due to new Schm it t Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a

4: This parameter is not tested but ensured by character ization. For enduranc e estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site:
www.microchip.com.

Industrial (I): T
Automotive (E): T

—

4000

4700

—
—

4000

4700

250

4000

—
—

1300
4700

20+0.1C

B

—

A = -40°C to +85°C
A = -40°C to +125°C

400

kHz 2.5V ≤ VCC ≤ 5.5V

100

—

ns 2.5V ≤ VCC ≤ 5.5V

—
—

ns 2.5V ≤ VCC ≤ 5.5V

—

300

ns 2.5V ≤ VCC ≤ 5.5V

1000

—

ns 2.5V ≤ VCC ≤ 5.5V

—
—

ns 2.5V ≤ VCC ≤ 5.5V

—

—

ns 2.5V ≤ VCC ≤ 5.5V

—
—

ns 2.5V ≤ VCC ≤ 5.5V

—

900

ns 2.5V ≤ VCC ≤ 5.5V

3500

—

ns 2.5V ≤ VCC ≤ 5.5V

—

250

ns 2.5V ≤ V

250

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

1.8V ≤ V

—50ns(Notes 1 and 3)

—5ms—

TI specification for standard operation.

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC < 2.5V (24AA32A)

CC ≤ 5.5V
CC < 2.5V (24AA32A)

 2003 Microchip Technology Inc. DS21713D-page 3

24AA32A/24LC32A

FIGURE 1-1: BUS TIMING DATA

SCL

SDA

IN

SDA

OUT

5

3

7

6

14

2

FIGURE 1-2: BUS TIMING START/STOP

SCL

7

SDA

6

4

8

9

11

D4

10

12

10

Start Stop

DS21713D-page 4  2003 Microchip Technology Inc.

24AA32A/24LC32A

)

2.0 FUNCTIONAL DESCRIPTION

The 24XX32A supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus i s defined as t ransmitter, while a de vice
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
serial clock (SCL), controls the bus access and gener­ates the Start and Stop conditions, while the 24XX32A
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device deter­mines which mode is activ ated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable wheneve r the c lock lin e is high . Changes i n
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All com­mands must be preceded by a Start condition.

3.3 Stop Data Transf er (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera­tions must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically
unlimited, (althoug h only the la st thirty two by tes will be
stored when doing a write operation). When an over­write does occur it will replace data in a first-in first-out
(FIFO) fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The ma ster devi ce m ust gener at e an ex tr a cloc k
pulse which is associated with this Acknowledge bit.

Note: The 24XX32A does not generate any

Acknowledge bits if an internal
programming cycle is in progress.

The device that acknowledges, has to pull down the
SDA line during the Acknowl edge cloc k pulse in s uch a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the sla ve by no t gene rating a n Ack nowl edge b it
on the last byte that has be en c loc ke d ou t of th e sl av e.
In this case, the slave (24XX32A) will leave the data
line high to enable the master to generate the Stop
condition.

FIGURE 3-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

 2003 Microchip Technology Inc. DS21713D-page 5

(A) (B) (D) (D) (A

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

(C)

STOP

CONDITION

24AA32A/24LC32A

it

3.6 Device Addressing

A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte co nsi sts of a four-bit control cod e. For
the 24XX32A, this is set as ‘1010’ binary for read and
write operations. The ne xt th ree bits of the control byte
are the Chi p Sel ect bits ( A2, A 1, A 0). T he Chip Sele ct
bits allow the use of up to eight 24XX32A devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic lev els on the corresp onding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three Most Significant bits of the word
address.

The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read op eration is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 3-3). Because
only A1 1 to A0 are use d, the upper four ad dress bits are
don’t care bits. The upper address bits are transferred
first, followed by the less significant bits.

Following the Start condition, the 24XX32A monitors
the SDA bus checking the device type identifier being
transmitted and, upon receiving a ‘1010’ code and
appropriate device s elect b its , the s lave d evice outputs
an Acknowledge si gnal on the SD A line. Dependi ng on
the state of the R/W
or write operation.

bit, the 24XX32A will selec t a read

FIGURE 3-2: CONTROL BYTE FORMAT

Read/Write Bit

Control Code

1 0 1 0 A2 A1 A0SACK

Slave Address

Start Bi t

Chip Select

Bits

R/W

Acknowledge Bit

3.7 Contiguous Addressing Across
Multiple Devices

The Chip Select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 256K bits by
adding up to eight 24XX32A's on the same bus. In this
case, software can use A0 of the control byte
address bit A12, A1 as address bit A13, and A2 as
address bit A14. It is not possible to sequentially read
across device boundaries.

as

FIGURE 3-3: ADDRES S SEQUENCE BI T ASSIGN MENTS

CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE

1010

CONTROL

CODE

A2A1A

CHIP

SELECT

BITS

R/W XXXX

0

A11A10A

9

A

8

A

••••••

7

X = Don’t Care B

A
0

DS21713D-page 6  2003 Microchip Technology Inc.

24AA32A/24LC32A

4.0 WRITE OPERATIONS

4.1 Byte Write

Following the Start condition from the master, the
control code (4 bits), the Chip Select (3 bits), and the
R/W bit (which is a lo gic low) ar e clo cke d on to t he b us
by the master transmitter. This indicates to the
addressed slave r eceiver that the add ress high byte
will follow once it has ge nerated an Acknowle dge bit
during the ni nth cloc k cycle. Therefor e, the n ext byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24XX32A. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX32A, the master
device will transmit the data word to be written into the
addressed memory loc ation. The 24XX3 2A acknowl­edges again and the master generates a Stop
condition. This init iates the internal write cycle and,
during this time, the 24XX32A will not generate
Acknowledge signals (Figure 4-1). If an attempt is
made to write to the array with the WP pin held high,
the device will acknowledge the command but no
write cycle will occur. No data will be writte n and the
device will immediately accept a new command. After
a byte Write command, the internal address counter
will point to the address location following the one that
was just written.

4.2 Page Write

The write control byte, word address and the first data
byte are transmitted to the 24XX32A in the same way
as in a byte write. However, instead of generating a
Stop co ndition, th e master tra nsmits up to 31 add itional
bytes whic h are tempor arily stored in the on-chip page
buffer and will be written into memory once the master
has transmitted a Stop condition. Upon receipt of each
word, the five lower-address pointer bits are internally
increment ed by ‘ 1’. If the master should transmit more
than 32 bytes prior to gene rating the S top condition, th e
address counter will roll over and the previously
received data will be overwri tten. As w ith the by te writ e
operation, once the Stop condition is received, an
internal write cycle w ill begin (Figure4-2). If an attempt
is made to write to th e array with the WP pin held hig h,
the device will ac knowledge the command but no w ri te
cycle will occur, no data will be written and the device
will immediately accept a new command.

Note: Page write operatio ns are lim ited to wri ting

bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buf fer size (or
‘page size’) and, end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next p age as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.

4.3 Write-Protection

The WP pin a llows t he user to wri te-prot ect the entire
array (0000-0FFFF) when the pin is tied to V
to V

SS or left floating, the write protection is disabled.

The WP pin is sampled at the Stop bit for every write
command (Figure 3-1) Toggling the WP pin after the
Stop bi t wil l hav e no ef fe ct on t he ex ecutio n o f the wr ite
cycle.

 2003 Microchip Technology Inc. DS21713D-page 7

CC. If tied

24AA32A/24LC32A

FIGURE 4-1: BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY
X = don’t care bit

FIGURE 4-2: PAGE WRITE

S

T
BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY
X = don’t care bit

CONTROL

A

R

T

S10 10 0

S
T

CONTROL

A
R
T

S1010 0

BYTE

A2A1A

0

A
C
K

BYTE

A

A1A

2

0

ADDRESS

HIGH BYTE

XXX

X

ADDRESS

HIGH BYTE

XXX

A
C
K

A
C
K

ADDRESS
LOW BYTE

X

A
C
K

ADDRESS
LOW BYTE DATA BYTE 0

A
C
K

S

DATA

A
C
K

DA TA BYTE 31

A
C
K

T
O
P

P

A
C
K

S
T
O
P

P

A
C
K

DS21713D-page 8  2003 Microchip Technology Inc.