MICROCHIP 24AA32 Technical data



C 

查询24AA32供应商

24AA32

2

32K 1.8V I



C

Smart Serial EEPROM

FEATURES

• Voltage operating range: 1.8V to 6.0V

- Peak write current 3 mA at 6.0V

- Maximum read current 150 µ A at 6.0V

- Standby current 1 µ A typical

• Industry standard two-wire bus protocol, I
compatible

- Including 100 kHz (1.8V) and 400 kHz (5V)

modes

• Self-timed ERASE and WRITE cycles

• Power on/off data protection circuitry

• Endurance:

- 10,000,000 Erase/Write (E/W) cycles guaran-

teed for High Endurance Block

- 1,000,000 E/W cycles guaranteed for Stan-

dard Endurance Block

• 8 byte page, or byte modes available

• 1 page x 8 line input cache (64 bytes) for fast write
loads

• Schmitt trigger, filtered inputs for noise suppression

• Output slope control to eliminate ground bounce

• 2 ms typical write cycle time, byte or page

• Factory programming (QTP) available

• Up to 8 devices may be connected to the same
bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP/SOIC packages

• Temperature ranges

- Commercial (C): 0 ° C to +70 ° C

2

DESCRIPTION

P ACKA GE TYPES

PDIP

A0

1

A1

2

A2

3

V

4

SS

SOIC

A0
A1

A2

V

SS

1
2

3

4

BLOCK DIAGRAM

A0..A2

24AA32

24AA32

8

VCC

7

NC

6

SCL

5

SDA

8

V

CC

7

NC

6

SCL

5

SDA

HV GENERATOR

The Microchip T echnology Inc. 24AA32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM capable of oper­ation across a broad voltage range (1.8V to 6.0V). This
device has been developed for advanced, low power
applications such as personal communications or data
acquisition. The 24AA32 features an input cache for
fast write loads with a capacity of eight 8-byte pages, or
64 bytes. It also features a fixed 4K-bit block of ultra­high endurance memory for data that changes fre­quently. The 24AA32 is capable of both random and
sequential reads up to the 32K boundary. Functional
address lines allow up to 8 - 24AA32 devices on the
same bus, for up to 256K bits address space. Advanced
CMOS technology and broad voltage range make this
device ideal for low-power/low voltage, nonvolatile code

2

I

C is a trademark of Philips Corporation.

1996 Microchip Technology Inc. DS21124C-page 1

I/O

CONTROL

LOGIC

I/O

SCL

SDA

CC

V

VSS

and data applications. The 24AA32 is available in the
standard 8-pin plastic DIP and 8-pin surface mount
SOIC package.

MEMORY

CONTROL

LOGIC

XDEC

EEPROM ARRAY

PAGE LATCHES

Cache

YDEC

SENSE AMP

R/W CONTROL



24AA32

µ

µ

µ

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

V

CC

..................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature..................................... -65˚C to +150˚C

Ambient temp. with power applied................ -65˚C to +125˚C

Soldering temperature of leads (10 seconds)............. +300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-2: DC CHARACTERISTICS

A0, A1, A2, SCL and SDA pins:

um Ratings*

SS

...............-0.6V to V

Parameter Symbol Min Max Units Conditions

CC

+1.0V

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A0..A2 User Configurable Chip Selects

V

SS

SDA Serial Address/Data I/O
SCL Serial Clock

V

CC

NC

CC

V

= +1.8V to 6.0V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Ground

+1.8V to 6.0V Power Supply

No Internal Connection

High level input voltage V
Low level input voltage V
Hysteresis of Schmitt Trigger inputs V

Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance

(all inputs/outputs)
Operating current I

Standby current I

Note: This parameter is periodically sampled and not 100% tested.

I

CC

CC

IH
IL

HYS

OL
LI

LO

C

IN

C

OUT

Write
Read

CCS

.7 V

CC

— .3 Vcc V

CC

.05 V

— .40 V I

-10 10

-10 10

,

—10pFV

—
—

—5

FIGURE 1-1: BUS TIMING START/STOP

SCL

TSU:STA

THD:STA

—V

— V (Note)

OL

IN

AV

OUT

AV

CC

Tamb = 25˚C, Fclk = 1 MHz

3

150

mA

µ

CC

V

CC

A

V

CC

A

V
(Note)

2

µ

A

V

CC

(Note)

VHYS

TSU:STO

= 3.0 mA

= .1V to V

= .1V to V

CC

CC

= 5.0V Note 1

= 6.0V, SCL = 400 kHz
= 6.0V, SCL = 400 kHz

= 5.0V, SCL = SDA = V
= 1.8V, SCL = SDA = V

CC

CC

SDA

DS21124C-page 2

START STOP

1996 Microchip Technology Inc.



24AA32

TABLE 1-3: AC CHARACTERISTICS

V

CC

= 1.8V-6.0V

Parameter Symbol

STD. MODE

Min Max Min Max

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T

Output fall time from V

IL

max

V

IH

min to

Input filter spike suppression

HIGH

HD

SU

HD
SU
SU

T

T

CLK

LOW

R
F

:

STA

:

STA

:

DAT

:

DAT

:

STO

AA

BUF

OF

SP

— 100 — 400 kHz
4000 — 600 — ns
4700 — 1300 — ns

— 1000 — 300 ns (Note 1)

— 300 — 300 ns (Note1)
4000 — 600 — ns After this period the first

4700 — 600 — ns Only relevant for repeated

0—0—ns

250 — 100 — ns

4000 — 600 — ns

— 3500 — 900 ns (Note 2)
4700 — 1300 — ns Time the bus must be free

— 250 20 +0.1

— 50 — 50 ns (Note 3)

(SDA and SCL pins)
Write cycle time T

WR

— 5 — 5 ms/page (Note 4)

Endurance

High Endurance Block
Rest of Array

Note 1: Not 100% tested. C

—
—

B

= total capacitance of one bus line in pF.

10M

1M

—
—

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

SP

specifications are due to new Schmitt trigger inputs which provide improved

HYS

noise and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

CC

V

= 4.5 - 6.0V

FAST MODE

B

C

10M

1M

Units Remarks

clock pulse is generated

START condition

before a new transmission
can start

250 ns (Note 1), C

—

cycles 25

—

C, Vcc = 5.0V, Block

Cycle Mode (Note 5)

B

≤

100 pF

°

FIGURE 1-2: BUS TIMING DATA

TF

TLOW

SCL

TSU:STA

THD:STA

SDA
IN

SDA
OUT

1996 Microchip Technology Inc. DS21124C-page 3

TSP

TAA

THIGH

THD:DAT

TAA

TSU:DAT

TSU:STO

TR

TBUF

24AA32

2.0 FUNCTIONAL DESCRIPTION

The 24AA32 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24AA32 works
as slave. Both master and slave can operate as trans­mitter or receiver but the master device determines
which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is
not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.

Note: The 24AA32 does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur­ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave (24AA32) will leave the data line HIGH
to enable the master to generate the STOP condition.

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (A)(C)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

DS21124C-page 4

 1996 Microchip Technology Inc.