查询24FC256供应商
M
256K Bit I
24AA256/24LC256/24FC256
2
™
C
CMOS Serial EEPROM
DEVICE SELECTION TABLE
Part
Number
24AA256 1.8-5.5V 400 kHz
24LC256 2.5-5.5V 400 kHz
24FC256 2.5-5.5V 1 MHz I
†
100 kHz for V
‡
100 kHz for E temperature range.
V
CC
Range
CC
< 2.5V.
Max Clock
Frequency
Temp
Ranges
†
‡
I
I, E
FEATURES
• Low power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µA at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 64-byte page-write mode available
• 5 ms max write-cycle time
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 100,000 erase/write cycles guaranteed
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC (208 mil) packages
• Temperature ranges:
- Industrial (I): -40 ° C to +85 ° C
- Automotive (E): -40 ° C to +125 ° C
2
C compatible
DESCRIPTION
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This device also has a page-write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary. Functional address lines allow up to eight devices on the
same bus, for up to 2M bit address space. This device
is available in the standard 8-pin plastic DIP and 8-pin
SOIC (208 mil) packages.
P ACKA GE TYPE
PDIP
A0
1
A1
2
A2
3
Vss
4
SOIC
1
A0
2
A1
3
A2
SS
V
4
BLOCK DIAGRAM
A0 A1 A2
WP
SCL
MEMORY
CONTROL
LOGIC
CONTROL
LOGIC
I/O
SDA
VCC
VSS
I/O
24XX256
8
24XX256
7
6
5
XDEC
Vcc
8
WP
7
SCL
6
SDA
5
VCC
WP
SCL
SDA
HV GENERATOR
PAGE LATCHES
SENSE AMP
R/W CONTROL
EEPROM
ARRAY
YDEC
2
I
C is a trademark of Philips Corporation.
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
1998 Microchip Technology Inc.
Preliminary
DS21203D-page 1
µ
µ
24AA256/24LC256/24FC256
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maxim
V
.................................................................................................7.0V
CC
All inputs and outputs w.r.t. V
Storage temperature...................................................-65°C to +150°C
Ambient temp. with power applied...............................-65°C to +125°C
Soldering temperature of leads (10 seconds)...........................+300°C
ESD protection on all pins........................................................... ≥ 4 kV
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2 DC CHARACTERISTICS
All parameters apply across the
specified operating ranges, unless
otherwise noted.
SCL, SDA, and WP pins:
High level input voltage V
Low level input voltage V
Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)
Low level output voltage V
Output leakage current I
Note: This parameter is periodically sampled and not 100% tested.
um Ratings*
SS
............................. -0.6V to V
Industrial (I): V
Automotive (E): V
Parameter Symbol Min Max Units Conditions
A0, A1, A2,
Input leakage current I
Pin capacitance
C
(all inputs/outputs)
Operating current I
Standby current I
CC
+1.0V
= +1.8V to 5.5V Tamb = -40°C to +85°C
CC
= +4.5V to 5.5V Tamb = -40°C to 125°C
CC
0.7 V
IH
IL
CC
— 0.3 V
0.2 V
V
IN
CC
I
CC
0.05 V
HYS
LO
, C
OL
LI
OUT
CC
— 0.40 V I
-10 10
-10 10
—10pFV
Read — 400 µA V
Write — 3 mA V
CCS
—1 µ A SCL = SDA = V
TABLE 1-1 PIN FUNCTION TABLE
Name Function
A0, A1, A2 User Configurable Chip Selects
Ground
SS
V
SDA Serial Data
SCL Serial Clock
WP Write Protect Input
V
+1.8 to 5.5V (24AA256)
CC
+2.5 to 5.5V (24LC256,24FC256)
—V
CC
CC
V
V
—VV
AV
AV
CC
V
2.5V
V
CC
< 2.5V
2.5V (Note)
CC
OL
= 3.0 mA @ V
I
= 2.1 mA @ V
OL
= V
or V
IN
SS
IN
V
= V
OUT
= V
= 5.0V (Note)
CC
Tamb = 25°C, f
CC
= 5.5V, SCL = 400 kHz
= 5.5V
CC
CC
SS
CC
or V
SS
or V
CC
= 1 MHz
c
CC
A0, A1, A2, WP = V
CC
CC
, WP = V
, WP = V
= 5.5V
= 4.5V
= 2.5V
SS
CC
SS
FIGURE 1-1: BUS TIMING DATA
TF
SCL
SDA
IN
SDA
OUT
WP
DS21203D-page 2
TSU:STA
TSP
TLOW
THD:STA
THIGH
THD:DAT TSU:DAT TSU:STO
TAA
(protected)
(unprotected)
VHYS
TR
TSU:WP
Preliminary
TBUF
THD:WP
1998 Microchip Technology Inc.
24AA256/24LC256/24FC256
TABLE 1-3 AC CHARACTERISTICS
All parameters apply across the specified operating ranges unless otherwise noted.
Parameter Symbol Min Max Units Conditions
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
(Note 1)
START condition hold time THD:STA 4000
START condition setup time TSU:STA 4700
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 250
STOP condition setup time TSU:STO 4000
WP setup time TSU:WP 4000
WP hold time THD:WP 4700
Output valid from clock
(Note 2)
Bus free time: Time the bus must be
free before a new transmission can
start
Output fall time from VIH
minimum to VIL maximum
CB ≤ 100 pF
Industrial (I): V
Automotive (E): V
CLK
HIGH
LOW
R
T
TF —
TAA —
TBUF 4700
TOF 10 + 0.1CB250
—
—
—
—
4000
4000
600
500
4700
4700
1300
500
—
—
—
—
—
4000
600
250
4700
600
250
250
100
100
4000
600
250
4000
600
600
4700
1300
1300
—
—
—
4700
1300
500
= +1.8V to 5.5V Tamb = -40°C to +85°C
CC
= +4.5V to 5.5V Tamb = -40°C to 125°C
CC
100
kHz 4.5V ≤ V
100
400
1000
—
—
—
—
—
—
—
—
1000
1000
300
300
300
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
3500
900
400
—
—
—
—
1.8V ≤ V
2.5V ≤ V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ V
1.8V ≤ V
2.5V ≤ V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ V
1.8V ≤ V
2.5V ≤ V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ V
1.8V ≤ V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns All except 24FC256
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ V
1.8V ≤ V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
24FC256 (2.5 V ≤ Vcc ≤ 5.5 V)
ns All except 24FC256 (Note 1)
250
24FC256 (Note 1)
CC
5.5V (E Temp range)
CC
2.5V
CC
5.5V
CC
5.5V (E Temp range)
CC
2.5V
CC
5.5V
CC
5.5V (E Temp range)
CC
2.5V
CC
5.5V
CC
≤ 5.5V (E Temp range)
CC ≤ 2.5V
CC ≤ 5.5V (E Temp range)
CC ≤ 2.5V
≤
≤
≤
≤
≤
≤
≤
≤
≤
1998 Microchip Technology Inc.
Preliminary
DS21203D-page 3
24AA256/24LC256/24FC256
TABLE 1-3 AC CHARACTERISTICS
All parameters apply across the specified operating ranges unless otherwise noted.
Parameter Symbol Min Max Units Conditions
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page) TWC —5
Endurance 100K — cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application,
please consult the Total Endurance Model which can be obtained on Microchip’s website @www.microchip.com.
Industrial (I): VCC = +1.8V to 5.5V Tamb = -40°C to +85°C
Automotive (E): V
T
SP — 50 ns All except 24FC256 (Notes 1 and 3)
CC = +4.5V to 5.5V Tamb = -40°C to 125°C
ms
DS21203D-page 4 Preliminary 1998 Microchip Technology Inc.
24AA256/24LC256/24FC256
2.0 PIN DESCRIPTIONS
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1, A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different chip select bit combinations. If left
unconnected, these inputs will be pulled down internally to V
SS.
2.2 SDA Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup
resistor to V
kHz and 1 MHz).
For normal data transfer SDA is allo wed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
CC (typical 10 kΩ for 100 kHz, 2 kΩ for 400
2.3 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.4 WP
This pin can be connected to either VSS, VCC or left
floating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to V
is enabled (read/write the entire memory 0000-7FFF).
If tied to V
operations are not affected.
SS or left floating, normal memory operation
CC, WRITE operations are inhibited. Read
3.0 FUNCTIONAL DESCRIPTION
The 24XX256 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be controlled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24XX256
works as a slave. Both master and slav e can operate as
a transmitter or receiver, but the master device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the cloc k line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condition.
4.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge bit.
Note: The 24XX256 does not generate any
acknowledge bits if an internal programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. During reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24XX256) will leav e the data line HIGH
to enable the master to generate the STOP condition.
1998 Microchip Technology Inc. Preliminary DS21203D-page 5
24AA256/24LC256/24FC256
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D) (C) (A)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
FIGURE 4-2: ACKNOWLEDGE TIMING
SCL
SDA
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
DATA
ALLOWED
TO CHANGE
Acknowledge
Bit
987654321 123
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
STOP
CONDITION
DS21203D-page 6 Preliminary 1998 Microchip Technology Inc.
24AA256/24LC256/24FC256
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code; for the
24XX256 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24XX256 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bits is a
don’t care. The upper address bits are transferred first,
followed by the less significant bits.
Following the start condition, the 24XX256 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W
write operation.
bit, the 24XX256 will select a read or
FIGURE 5-1: CONTROL BYTE FORMAT
ite Bit
Read/Wr
Control Code
1 0 1 0 A2 A1 A0SACKR/W
Slave Address
Start Bit
5.1 Contiguous Ad
Chip Select
Bits
Acknowledge Bit
dressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 2 Mbit by adding up to eight 24XX256's on the same bus. In this
case, software can use A0 of the control b
address bit A15; A1, as address bit A16; and A2, as
address bit A17. It is not possible to sequentially read
across device boundaries.
yte as
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE
A
1010
CONTROL
CODE
1998 Microchip Technology Inc. Preliminary DS21203D-page 7
A2A1A
CHIP
SELECT
BITS
R/W X
0
A13A
A11A10A
12
14
A
9
A
••••••
7
8
X = Don’t Care Bit
A
0
24AA256/24LC256/24FC256
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the start condition from the master, the
control code (four bits), the chip select (three bits), and
the R/W
bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24XX256. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24XX256, the master device will
transmit the data word to be written into the addressed
memory location. The 24XX256 acknowledges again
and the master generates a stop condition. This initiates the internal write cycle, and, during this time, the
24XX256 will not generate acknowledge signals
(Figure 6-1). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command but no write cycle will occur, no data will
be written, and the device will immediately accept a
new command. After a byte write command, the internal address counter will point to the address location
following the one that was just written.
FIGURE 6-1: BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
X = don’t care bit
S
T
CONTROL
A
BYTE
R
T
S1010 0
A1A
A
0
2
X
A
C
K
ADDRESS
HIGH BYTE
6.2 Page Write
The write control byte, word address, and the first data
byte are transmitted to the 24XX256 in the same way
as in a byte write. But instead of generating a stop condition, the master transmits up to 63 additional bytes,
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a stop condition. After receipt of each word,
the six lower address pointer bits are internally
incremented by one. If the master should transmit more
than 64 bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to V
V
SS or left floating, the write protection is disabled. The
WP pin is sampled at the STOP bit for every write
command (Figure 1-1) Toggling the WP pin after the
STOP bit will have no effect on the execution of the
write cycle.
ADDRESS
A
C
K
LOW BYTE
DATA
A
C
K
CC. If tied to
S
T
O
P
P
A
C
K
FIGURE 6-2: PAGE WRITE
S
T
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
X = don’t care bit
DS21203D-page 8 Preliminary 1998 Microchip Technology Inc.
CONTROL
A
BYTE
R
T
S1010 0
A2A1A
ADDRESS
HIGH BYTE
X
0
A
C
K
A
C
K
ADDRESS
LOW BYTE
DATA BYTE 0
A
C
K
A
C
K
DATA BYTE 63
S
T
O
P
P
A
C
K
24AA256/24LC256/24FC256
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition, followed by the control byte
for a write command (R/W
with the write cycle, then no ACK will be returned. If no
ACK is returned, then the start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
= 0). If the device is still b usy
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
YES
Next
Operation
NO
1998 Microchip Technology Inc. Preliminary DS21203D-page 9
24AA256/24LC256/24FC256
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
8.1 Current Address Read
The 24XX256 contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W
the 24XX256 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24XX256 discontinues transmission (Figure 8-1).
FIGURE 8-1: CURRENT ADDRESS READ
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
T
A
R
T
S
1100
CONTROL
BYTE
AAA
210
1
A
C
K
bit of the
bit set to one,
DATA
BYTE
N
O
A
C
K
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done b y sending the word address to the
24XX256 as part of a write operation (R/W
bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This terminates the write operation, but not before the internal
address pointer is set. Then, the master issues the
control byte again but with the R/W
bit set to a one. The
24XX256 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24XX256 to discontinue transmission
(Figure 8-2). After a random read command, the internal address counter will point to the address location
following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a random read except that after the 24XX256 transmits the
S
T
O
P
P
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24XX256 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge b ut will generate a stop condition. To pro vide sequential reads , the
24XX256 contains an internal address pointer which is
incremented by one at the completion of each operation. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer will automatically roll over from
address 7FFF to address 0000 if the master acknowledges the byte received from the array address 7FFF.
FIGURE 8-2: RANDOM READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
X = Don’t Care Bit
S
T
CONTROL
A
R
BYTE
T
S1010
AAA
210
0
X
A
C
K
ADDRESS
HIGH BYTE
A
C
K
ADDRESS
LOW BYTE
S
T
A
R
T
S1010
A
C
K
CONTROL
BYTE
AAA
210
DATA
BYTE
1
A
C
K
S
T
O
P
P
N
O
A
C
K
FIGURE 8-3: SEQUENTIAL READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
DS21203D-page 10 Preliminary 1998 Microchip Technology Inc.
CONTROL
BYTE
DATA n DATA n + 1 DATA n + 2 DATA n + X
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
N
O
A
C
K
24AA256/24LC256/24FC256
24XX256 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
24XX256 — /P
Package:
P = Plastic DIP (300 mil Body), 8-lead
SM = Plastic SOIC (208 mil Body, EIAJ standard), 8-lead
Temperature
Range:
Device:
24AA256T 256K bit 1.8V I
24LC256T 256K bit 2.5V I
24FC256T 256K bit 1MHz I
I = -40°C to +85°C
E = -40°C to +125°C
24AA256 256K bit 1.8V I
24LC256 256K bit 2.5V I
24FC256 256K bit 1MHz I
2
C Serial EEPROM
2
C Serial EEPROM (Tape and Reel)
2
C Serial EEPROM
2
C Serial EEPROM (Tape and Reel)
2
C Serial EEPROM
2
C Serial EEPROM (Tape and Reel)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Web Site at www.microchip.com
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using
1998 Microchip Technology Inc. Preliminary DS21203D-page 11
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
Microchip T echnology Inc.
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Chandler, AZ 85224-6199
Tel: 602-786-7200 Fax: 602-786-7277
Technical Support:
Web:
http://www.microchip.com
Atlanta
Microchip T echnology Inc.
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Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip T echnology Inc.
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Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Chicago
Microchip T echnology Inc.
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Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip T echnology Inc.
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Tel: 972-991-7177 Fax: 972-991-8588
Dayton
Microchip T echnology Inc.
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Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip T echnology Inc.
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Tel: 248-374-1888 Fax: 248-374-2874
Los Angeles
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Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip T echnology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
602 786-7627
AMERICAS (continued)
Toronto
Microchip T echnology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
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Tel: 852-2-401-1200 Fax: 852-2-401-3431
India
Microchip T echnology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
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Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microchip T echnology Korea
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Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
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Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan, R.O.C
Microchip T echnology Taiwan
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Tung Hua North Road
T aipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh T riangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
France
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
7/7/98
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January , 1997.
Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
related specialty memory products
and development systems conform
to the stringent quality standards of
the International Standard
Organization (ISO).
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 10/98 Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS21203D-page 12 1998 Microchip Technology Inc.
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