• Organized as 8 blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (≥2.5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 16 bytes
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP
packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available temperature ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
2
C™ compatible
Description:
The Microchip Technology Inc. 24AA16/24LC16B
(24XX16*) is a 16 Kbit Electrically Erasable PROM.
The device is organized as eight blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX16 also has a page write
capability fo r up to 16 bytes of data. The 24X X16 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN and MSOP packages, and is
also available in the 5-lead SOT-23 package.
Package Types
A0
A1
A2
SS
V
V
SOIC, TSSOP
1
2
3
4
1
A0
2
A1
3
A2
SS
4
DFN
8
V
CC
7
WP
6
SCL
5
SDA
CC
V
8
WP
7
SCL
6
5
SDA
PDIP, MSOP
1
A0
2
A1
3
A2
4
V
SS
SOT-23-5
15
SCL
2
Vss
3
SDA
Note:Pins A0, A1 and A2 are not used by the 24XX16 (no
internal connections).
8
VCC
7
WP
6
SCL
5
SDA
WP
4
Vcc
Block Diagram
WP
HV
Generator
I/O
Control
Logic
I/O
SCL
SDA
V
CC
*24XX16 is used in this document as a generic part
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indica ted in the opera tional li stings of this sp ecification is not i mplied. Ex posure to maximum rating
conditions for extended periods may affect device reliability.
SS ......................................................................................................... -0.3V to VCC +1.0V
(†)
TABLE 1-1:DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
D1V
D2—High-level input voltage0.7 V
D3VILLow-level input voltage——0.3 VCCV—
D4VHYSHysteresis of Schmitt
D5V
D6ILIInput leakage current——±1μAVIN = VSS or VCC
D7ILOOutput leakage current——±1μAVOUT = VSS or VCC
D8CIN,
D9I
D10ICC read—0.011mA—
D11ICCSStandby current—
Note 1:This parameter is periodically sampled and not 100% tested.
The 24XX16 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX16 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable when ever the c lock lin e is high. Cha nges i n
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1Bus Not Busy (A)
Both data and clock lines remain high.
3.2Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3Stop Data Transfer (C)
A low-to-h i gh t ran si t io n of t h e SD A l in e whi l e t h e c lo ck
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a S tart conditi on and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically
unlimited, (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur it will replace data in a first-in first-out (FIFO)
fashion.
3.5Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The ma ster devi ce m ust gener at e an ex tr a cloc k
pulse which is associated with this Acknowledge bit.
Note:The 24XX16 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the sla ve by no t gene rating a n Ack nowl edge b it
on the last byte that has be en c loc ke d ou t of th e sl av e.
In this case, the sl ave (24 XX16) will leave the data lin e
high to enable the master to generate the Stop
condition.
FIGURE 3-1:DAT A TRANSFER SEQUENCE ON THE SERIAL BUS
A control byte is th e first byte received following the
Start condition from the master device (Figure 3-2).
The control byte consists of a four-bit control code.
For the 24XX16, this is set as ‘
and write operations. The next three bits of the control
byte are the block-sel ect bits (B2, B1, B0). T hey are
used by the master device to select which of the eight
256 word-blocks of memory are to be accessed.
These bits are in effect the thr ee Mo st S ignif ica nt bits
of the word address. It should be noted that the
protocol limits the si ze of the me mory to eight block s
of 256 wor ds , th er efore, the protocol can support only
one 24XX16 per system .
The last bit of the control byte defines the operation to
be performed. When set to ‘
selected. When set to ‘
Following the Start condition, the 24XX16 monitors the
SDA bus, checking the device type identifier being
transmitted and, upon receiving a ‘
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX16 will select a read or write operation.
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a lo gic-low, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow once it has generated an Ac knowledge b it during
the ninth clock cycl e. Therefore, th e next byte trans mitted by the master is the word address and will be
written into the Address Pointer of the 24XX16. After
receiving another Acknowledge signal from the
24XX16, the master device will transmit the data word
to be written into the addressed memory location. The
24XX16 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24XX16 will not
generate Acknowledge signals (Figure 4-1).
4.2Page Wri te
The write control byte, word address and the first data
byte are transmitted to the 24 XX16 in th e same w ay a s
in a byte write. However, instead of generating a Stop
condition, the master transmits up to 16 data bytes to
the 24XX16, which are temporarily stored in the onchip page buffer and will be written into memory once
the master has transmitted a Stop condition. Upon
receipt of each word, the four lower-order Address
Pointer bits are internally incremented by ‘
higher-order 7 bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwri tten. As w ith the by te writ e
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-2).
Note:Page write operatio ns are lim ited to wri ting
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buf fer size (or
‘page-size’) and end a t ad dresses that a re
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might b e
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issu ed from the mas ter , the device
initiates the int ernally-timed wri te cycle and ACK pol ling
can then be initiated immediately. This involves the
master sending a S tart c ondition fo llowed by the contro l
byte for a Write c ommand (R/W
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 5-1 for a flow diagram of
this operation.
FIGURE 5-1:ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
= 0). If the device is still
6.0WRITE-PROTECTION
The 24XX16 can be used as a serial ROM when the
WP pin is connected to V
inhibited and the entire memory will b e writ e-protected.
Read operations are initiated in the same way as write
operations, with the exception that the R/W
slave address is set to ‘
1’. There are three basic types
of read operations: current addr ess read , rand om rea d
and sequential read.
7.1Current Address Read
The 24XX16 contains an address counter that maintains the address of the last word accessed, internally
incremented by ‘
1’. Therefore, if the previous access
(either a read or write opera tio n) w as to address
next current address read operati on would access da ta
from address
with R/W
n + 1. Upon receipt of the sl ave add res s
bit set to ‘1’, the 24XX16 issues an acknowledge and transmits the 8-b it data w ord. The master will
not acknowledge the tra nsfer , but does generate a S top
condition and the 24XX16 discontinues transmission
(Figure 7-1).
7.2Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operatio n, th e w ord add ress m us t firs t
be set. This is accomplished by sending the word
address to the 24XX16 as part of a write operation.
Once the word address is sent , the master ge nerates a
Start condition following the acknowledge. This
terminates the write operation, but not before the internal Address Pointer is set. The master then issues the
control byte agai n, but wi th the R /W
24XX16 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer , but does generate a S top con dition and the
24XX16 will discontinue transmission (Figure 7-2).
bit set to a ‘1’. The
bit of the
n, the
7.3Sequential Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX16 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX16 to transmit the next sequentiallyaddressed 8-bit word (Figure 7-3).
To provide se quential read s, the 24XX16 co ntains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4Noise Protection
The 24XX16 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the V
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
V
SDA555553Serial Address/Data I/O
SCL666661Serial Clock
WP777775Write-Protect Input
CC888884+1.8V to 5.5V Power Supply
V
8.1Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the de vice . Sinc e it i s an opendrain terminal, the SDA bus requires a pull-up resistor
CC (typical 10 kΩ for 100 k Hz, 2 kΩ for 400 kHz).
to V
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
8.2Serial Clock (SCL)
The SCL input is used to sync hro ni ze th e da t a tra ns fer
to and from the device.
8.3Write-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to V
(read/write the entire memory
If tied to V
memory will be write-protected. Read operations are
not affected.
This feature allows the user to use the 24XX16 as a
serial ROM when WP is enabled (tied to V
SS, normal memory operation is enabled
00-07FFH).
CC, write operations are inhibited. The entire
CC).
8.4A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX16.
They may be left floating or tied to either V
Note:For very small packages with no room for the Pb-free JEDEC designator
Note:In the event the full Microchip part num ber can not be ma rked on one line , it wil
TSSOPMSOP
TTemperature (I, E)
YYear code (last digit of calendar year)
YYYear code (last 2 digits of calendar year)
WWWeek code (week of January 1 is week ‘01’)
NNNAlphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
3
e
, the marking will only appear on the outer carton or reel label.
3
e
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
I Temp.E Temp.I Temp.E Temp.
SOT-23DFN
Note:Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
Number of Pins
Pitch
Top to Seating PlaneA.140.155.1703.563.944.32
Molded Package ThicknessA2.115.130.1452.923.303.68
Base to Seating PlaneA1.0150.38
Shoulder to Shoulder WidthE.300.313.3257.627.948.26
Molded Package WidthE1.240.250.2606.106.356.60
Overall LengthD.360.373.3859.149.469.78
Tip to Seating PlaneL.125.130.1353.183.303.43
Lead Thickness
Upper Lead WidthB1.045.058.0701.141.461.78
Lower Lead WidthB.014.018.0220.360.460.56
Overall Row Spacing§eB.310.370.4307.879.4010.92
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
24AA16/24LC16B
B
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickness
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
n
B
1
A
c
A1
φ
β
Units
A1
n
p
φ
c
α
β
048048
Number of Pins
Pitch
Standoff §
Foot Angle
Lead Thickne ss
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E
E1
p
B
p1
D
24AA16/24LC16B
n
c
β
Number of Pins
Pitch
Outside lead pitch (basic)
Foot Angle
Lead Thickne ss
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-178
Drawing No. C04-091
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Device: Literature Number:
Questions:
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DS21703E24AA16/24LC16B
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PART NO.X/XX
Device
PackageTemperature
Range
24AA16:= 1. 8V, 16 Kbit I2C Serial EEPROM
24AA16T: = 1.8V, 16 Kbit I
24LC16B: = 2.5V, 16 Kbit I
24LC16BT: = 2.5V, 16 Kbit I
Temperature
Range:
Package:MC=2x3 DFN, 8-lead
Lead Finish Blank =Pb-free – Matte Tin (see Note 1)
I=-40°C to +85°C
E= -40°C to +125°C
P=Plastic DIP (300 mil body), 8-lead
SN=Plastic SOIC (150 mil body), 8-lead
ST=Plastic TSSOP (4.4 mm), 8-lead
MS=Plastic Micro Small Outline (MSOP), 8-lead
OT=SOT-23, 5-lead (Tape and Reel only)
G=Pb-free – Matte Tin only
(Tape and Reel)
(Tape and Reel)
2
C Serial EEPROM
2
C Serial EEPROM
2
C Serial EEPROM
X
Lead Finish
Examples:
a)24AA16-I/P: Industrial Temperature,1.8V,
PDIP package
b)24AA16-I/SN : Industrial Temperature,1.8V,
SOIC package
c)24AA16T-I/OT: Industrial Temperature,
1.8V, SOT-23 package, Tape and Reel
d)24LC16B-I/P: Industrial T emperature, 2.5V,
PDIP package
e)24LC16B-E/SN: Automotive Temp.,2.5V
SOIC package
f)24LC16BT-I/OT: Industrial Temperature,
2.5V, SOT-23 package, Tape and Reel
Note 1: Most products manufactured after January 2005 will have a M atte Tin (Pb-free) finish. Most products manufactured
before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).
Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.
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Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.Your local Microchip sales office
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Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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Note the following details of the code protection feature on Microchip devices:
•Microchip products meet the specification contained in their particular Microchip Data Sheet.
•Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•Microchip is willing to work with the customer who is concerned about the integrity of their code.
•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are com mitted to continuously improving the code protect ion f eatures of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Mill ennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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