MICROCHIP 24AA128, 24LC128, 24FC128 Technical data

24AA128/24LC128/24FC128

128K I2C™CMOS Serial EEPROM

DEVICE SELECTION TABLE

Part

Number

24AA128 1.8-5.5V 400 kHz

24LC128 2.5-5.5V 400 kHz
24FC128 2.5-5.5V 1 MHz I

†

100 kHz for VCC < 2.5V.

‡

100 kHz for E temperature range .

VCC

Range

Max Clock
Frequency

†
‡

Temp

Ranges

C

I, E

FEATURES

• Low power CMOS technology

- Maximum write current 3 mA at 5.5V

- Maximum read current 400 µA at 5.5V

- Standby current 100 nA typical at 5.5V

• 2-wire serial interface bus , I2C compatible

• Cascadable for up to eight devices

• Self-timed ERASE/WRITE cycle

• 64-byte page-write mode available

• 5 ms max write-cycle time

• Hardware write protect for entire array

• Output slope control to eliminate ground bounce

• Schmitt trigger inputs for noise suppression

• 100,000 erase/write cycles guaranteed

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP and SOIC (150 a nd 20 8 m il) p ackages

• 14-pin TSSOP package

• Temperature ranges:

- Commercial (C) 0° to +70°C

- Industrial (I): -40°Cto +85°C

- Automotive (E): -40°Cto+125°C

PACKAGE TYPE

PDIP

A0

1

A1

2

A2

3

Vss

4

SOIC

V

TSSOP

A0
A1
A2

SS

A0
A1

NC
NC
NC

A2

Vss

1
2

3
4

1
2
3
4
5
6
7

BLOCK DIAGRAM

A0 A1 A2

WP

24XX128

24XX128

24XX128

8

7
6

5

8
7

6
5

14
13
12
11
10
9
8

Vcc

WP
SCL

SDA

VCC
WP
SCL
SDA

Vcc
WP
NC

NC
NC

SCL
SDA

HV GENERATOR

DESCRIPTION

The Microchip Technology Inc. 24AA128/24LC128/
24FC128 (24XX128*) is a 16K x 8 (128K bit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.8V to 5.5V). It has
been developed for advanced, low power applications
such as personal communications or data acquisition.
This devi ce also ha s a page-write ca pa bility of u p to 64

CONTROL

LOGIC

I/O

SDA

I/O

SCL

MEMORY

CONTROL

LOGIC

XDEC

EEPROM

ARRAY

PAGE LATCHES

YDEC

bytes of data. This device is capable of both random
and sequential reads up to the 128K boundary. Func­tional address lines allow up to eight devices on the
same bus, for up to 1M bit address space. This device
is avail able in th e standard 8-pin p lastic DIP, 8-pin SOIC

VCC
VSS

SENSE AMP

R/W CONTROL

(150 and 208 mil), and 14-pin TSSOP pa ckages.

I2C is a trademark of Philips Corporation.
*24XX128 is used in this document as a generic part number for the 24AA128/24LC128/24FC128 devices.

 1999 Microchip Technology Inc. Preliminary DS21191F-page 1

24AA128/24LC128/24FC128

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*

VCC........................................................................6.5V

All inputs and outputs w.r.t. V

Storage temperature..........................-65°C to +150°C

Ambient temp. with power applied......-65°C to +125°C

Soldering temperature of leads (10 seconds)..+300°C

ESD protection on all pins ..................................... ≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listin gs of this spe cificat ion is
not implied. Exposure to maximum rating conditions for extended peri­ods may affect device reliability.

SS .....-0.6V to VCC +1.0V

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A0, A1, A2 User Configurable Chip Selects

V

SS Ground

SDA Serial Data
SCL Serial Clock

WP Write Protect Input

CC +1.8 to 5.5V (24AA128)

V

+2.5 to 5.5V (24LC128)

TABLE 1-2: DC CHARACTERISTICS

All parameters apply across the
specified operating ranges, unless
otherwise noted.

Parameter Symbol Min Max Units Conditions

A0, A1, A2, SCL, SDA, and WP
pins:

High level input voltage V
Low level input voltage V

Hysteresis of Schmitt Trigger
inputs (SDA, SCL pins)
Low level output voltage VOL —0.40VIOL = 3.0 mA @ VCC = 4.5V

Input leakage current I
Output leakage current ILO -10 10 µAVOUT = VSS or VCC

Pin capacitance
(all inputs/outputs)

Operating current

Standby current I

Note: This parameter is periodically sampled and not 100% tested.

Commercial (C): VCC = +1.8V to 5.5V Tamb = 0°C to +70°C
Industrial (I): V
Automotive (E): V

IH 0.7 VCC —V
IL — 0.3 VCC

V

HYS 0.05 VCC —VVCC ≥ 2.5V (Note)

LI -10 10 µA

CC = +2.5V to 5.5V Tamb = -40°C to +85°C
CC = +4.5V to 5.5V Tamb = -40°C to 125°C

V

VCC ≥ 2.5V

0.2 VCC

V

CC < 2.5V

V

I

OL = 2.1 mA @ VCC = 2.5V

IN = VSS or VCC, WP = VSS

V
VIN = VSS or VCC, WP = VCC

CIN, COUT —10pFVCC = 5.0V (Note)

Tamb = 25°C, f

I

CC Read — 400 µA VCC = 5.5V, SCL = 400 kHz

I

CC Write — 3 mA VCC = 5.5V

CCS —1 µA

SCL = SDA = V
A0, A1, A2, WP = V

c

= 1 MHz

CC = 5.5V

SS

FIGURE 1-1: BUS TIMING DATA

SCL

SDA
IN

SDA
OUT

WP

DS21191F-page 2 Preliminary  1999 Microchip Technology Inc.

TSU:STA

THD:STA

TLOW

(protected)

(unprotected)

TSU:WP

THD:WP

24AA128/24LC128/24FC128

TABLE 1-3: AC CHARACTERISTICS

All parameters apply across the spec­ified operating ranges unless other­wise noted.

Parameter Symbol Min Max Units Conditions

Clock frequency F

Clock high time T

Clock low time T

SDA and SCL rise time
(Note 1)

SDA and SCL fall time
(Note 1)

START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T

STOP condition setup time T

WP setup time T

WP hold time T

Note 1: Not 100% tested. C

B

2: As a transmitt er, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

4: T his parameter is not tested b ut guaranteed b y characterization. F or endurance estimates in a specific application, please

consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

Commercial (C): VCC = +1.8V to 5.5V Tamb = 0°C to +70°C
Industrial (I): V
Automotive (E): V

CLK —

HIGH 4000

LOW 4700

R —

T

F —

T

HD:STA 4000

SU:STA 4700

HD:DAT 0 — ns (Note 2)
SU:DAT 250

SU:STO 4000

SU:WP 4000

HD:WP 4700

= total capacitance of one bus line in pF.

CC = +2.5V to 5.5V Tamb = -40°C to +85°C

CC = +4.5V to 5.5V Tamb = -40°C to 125°C

CC
CC
CC

CC
CC
CC

CC
CC
CC

CC
CC
CC

CC
CC
CC

CC
CC
CC

CC
CC
CC

CC
CC
CC

CC
CC

CC
CC
CC

—
—
—

4000

600
500

4700
1300

500

—
—
—

—

4000

600
250

4700

600
250

250
100
100

4000

600
250

4000

600
600

4700
1300
1300

100
100
400

1000

—
—
—
—

—
—
—
—

1000
1000

300
300

300
100

—
—
—
—

—
—
—
—

—
—
—
—

—
—
—
—

—
—
—
—

—
—
—
—

kHz 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns All except 24FC128

24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

 1999 Microchip Technology Inc. Preliminary DS21191F-page 3

24AA128/24LC128/24FC128

TABLE 1-3: AC CHARACTERISTICS (CONTINUED)

All parameters apply across the spec­ified operating ranges unless other­wise noted.

Parameter Symbol Min Max Units Conditions

Output valid from clock
(Note 2)

Bus free time: Time the bus must be
free before a new transmission can
start

Output fall time from V
minimum to VIL maximum

≤ 100 pF

C

B

Input filter spike suppression
(SDA and SCL pins)

Write cycle time (byte or page) T
Endurance 100K — cycles 25°C, V

Note 1: Not 100% tested. C

2: As a transmitt er, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

suppression. This eliminates the need for a TI specification for standard operation.

4: T his parameter is not tested b ut guaranteed b y characterization. F or endurance estimates in a specific application, please

consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.

IH

B

SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike

Commercial (C): VCC = +1.8V to 5.5V Tamb = 0°C to +70°C

Industrial (I): V
Automotive (E): V

TAA —

BUF 4700

T

T

OF 10 + 0.1C

SP — 50 ns All except 24FC128 (Notes 1 and 3)

T

WC —5ms

= total capacitance of one bus line in pF.

CC = +2.5V to 5.5V Tamb = -40°C to +85°C

CC = +4.5V to 5.5V Tamb = -40°C to 125°C

CC
CC
CC

CC
CC
CC

CC = 5.0V, Block Mode (Note 4)

—
—
—

4700
1300

500

3500
3500

900
400

—
—
—
—

250

B

250

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns 4.5V ≤ V

1.8V ≤ V

2.5V ≤ V
24FC128 (2.5 V ≤ Vcc ≤ 5.5 V)

ns All except 24FC128 (Note 1)

24FC128 (Note 1)

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

5.5V (E Temp range)

≤

2.5V

≤

5.5V

≤

2.0 PIN DESCRIPTIONS

2.1 A0, A1, A2 Chip Address Inputs

The A0, A1, A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the cor respondi ng bits in t he slave
address. The chip is select ed if the compare is tr ue.

Up to eight devices may be connected to the same bus by
using different chip select bit combinati ons. If left uncon­nected, these inputs will be pulled down internally to V

2.2 SDA Serial Data

This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open­drain terminal, therefore , the SDA b us requires a pullup
resistor to V

CC (typical 10 kΩ for 100 kHz, 2 kΩ for 400

kHz and 1 MHz).
For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.

2.3 SCL Serial Clock

This input is us ed to synch roniz e th e dat a tr ansfer from
and to the device.

SS.

2.4 WP

This pin can be connected to either VSS, VCC or left
floating. A n internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to V

SS or left floating, normal memory operation

is enabled (read/write the entire memory 0000-3FFF).
If tied to V

CC, WRITE operations are inhibited. Read

operations are not affected.

3.0 FUNCTIONAL DESCRIPTION

The 24XX128 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be con­trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24XX128
works as a slav e. Both m aster and sla ve can o perate as
a transmitter or receiver, but the master device deter­mines which mode is activated.

DS21191F-page 4 Preliminary  1999 Microchip Technology Inc.

24AA128/24LC128/24FC128

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable whenever the clock line is H IG H. C han ge s
in the data line while the clock line is H IG H will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 4-1).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW trans ition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

4.3 Stop Data Transfer (C)

A LOW to HIGH trans ition of the SDA line while the
clock (SCL) is HI GH de termines a STOP con dit i on . A ll
operations must end with a STOP cona810(Glaq1.008 T]TJı˝T*ı˝0.003 Tcı˝-0.001 Twı˝[(o)12(per)16(at)14(9))]T(Glaq1.-a-22(t) V)52t S i7laq11(4)-(C)sfate o5(a t(g b)213(sf)15(ei)13(n)3(e da)13rep11 Tw-18es)13(e)0( tin)13()0(e) lod5(er)57(, (ab)27(l)13(e)0( ,ll)14( b)14(e)1( )]TJı˝03 570.TJı39˝0.003 12(d fis)1(n)-2( a (by45)11(-5(he ST)4)13(c)-8( c)-c)11((o)12(per,.016 T15(er)27(, l3( c)c)2i(s)-45iner)27o)16(l)13(y)3(an)-13( o)er)-337(e)0( bee)13(n)]TJı˝0*ı˝0.003 (O)8(on)12001 Twn c STo13( 515(t0(GH)-111(t))0(s)2 Tcı˝- c)-c Tcı˝-f.016 T12(d we ST)lsiksdg2(peral(ona81028 33(n)]T3 T3(s2[(i)142Twn)12)12(d w12(per6 T12(d wl3( c)c)2 li)1)13on)12(s)-4( m)2bt0(GH)-11we ST 12(d ngeu)-1(s(O)8(on)1200t)sper oe been

 1999 Microchip Technology Inc. Preliminary DS21191F-page 5

24AA128/24LC128/24FC128

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the
start condition from t he master de vice (Figu re 5-1). The
control byte consists of a 4-bit control code; for the
24XX128 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24XX128 devices on the
same bus and are used to select which device is
accessed. Th e c hip se le ct b it s i n th e co n tr ol byte must
correspond to the logi c le v els on the c orrespondi ng A2,
A1, and A0 pi ns for th e device to r espond. These b its
are in effect the three most signific ant bits of the word
address.

The last bit of the control byte defines the operation to
be performed. When set -13lor oTJ07(7e-1(s0)-1(9T86[()12( te)27(s)10(e)-1(l)12(e)-1()1( )]T812(e)--247(7e-2(s)-4(s)l)12(, 0.0n12(r(l)-12(sn (e)--247(tus)11(e de)120.0 ze)--2413(ce)12(r(lr8(o)1t)15( e1( oT307(7e-1(s03-1(9T86312(e)-1(c)10(t)1( bit))12(ng )13(A20 12)]T812(e( T)-lee)-12(ct)6)15(he r)-9( r)-9e)0(s)-3(r)4s)-16( f)-11(n)0(r)-9( txct)6)150(s)-te)17(o(th)4-10(r6)150(s)(e)0( t)-1(c)-16(e)0(e d)-13(e11(h)-ve)--2-9(1)0(de r)-9fa)12(d)0(d)-e r)-9(ns)-16( 0)12(d w)5(r)-11s)]TJ0 2 )]TJ0 rd)]TJ0 -1.2267 TD(t)14((Th)1)-1( )13strs2(ifi)d0.066 a86 Tw[(c)10(de)66 Tviy117(F2(-2gu)13(3(Bc)10(hau(d)12(.16(V)-45 Tc0 Te)27(s)10(e)-)12(28)12(t)1(e)]T9(e)-l2(010)A13i)12(205A013(3(arits)10us )-13(re)1,)12(n)-1( )13up oTJ0t )13(( o)12(f) ape)12d ths(ifi)12((l)12(2(e)l b)26(y)-4(te)12( )-12(s)23(.)1( )]TJ0 ds0)-1()10(ts)0(d)ha39(x)1( )-13[(s)0(d)(ion)12(up oTJ0tde)120]TJ0 -1.2267 TD(t)1de se7e-nTD(t)fe-0.041d2(d w)5(r)-11s

DS21191F-page 6 Preliminary  1999 Microchip Technology Inc.

24AA128/24LC128/24FC128

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start condition from the master, the
control code (fou r b its), the chip select (three bits), and
the R/W
bus by the master transmitter. This indicates to the
addressed sla ve rec eiver that the address high b yte will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitte d by the mas ter is t he hig h-orde r byte of the
word address and will be written into the address
pointer of the 24XX128. The next byte is the least sig­nificant address byte. After receiving another acknowl­edge signal fr om the 24XX128 , the master device w ill
transmit the data word to be written into the addressed
memory location. The 24XX128 acknowledges again
and the master generates a stop condition. This ini­tiates the in ternal write cycle, and, during this time, the
24XX128 will not generate acknowledge signals
(Figure 6-1). If an at t em p t i s ma de to write to the ar ray
with the WP pin held high, the devic e will acknowledge
the command but no write cycle will occur, no data will
be written, and the device will immediately accept a
new command. After a byte write command, the inter­nal address counter will point to the address location
following the one that was just written.

6.2 Page Write

The write control byte , wo rd address, and the first data
byte are transmitted to the 24XX128 in the same way
as in a byte write. But inste ad of gener ating a stop co n­dition, the master transmits up to 63 additional bytes,
which are temp or arily s tored in the on-chip page buffer
and will be wr itten into memor y after the mast er has
transmitted a st op condition. After receipt of each word,
the six lower address pointer bits are internally

bit (which is a logi c low) are clocked onto the

incremented by one. If the master should transmit more
than 64 bytes prior to g eneratin g the s top conditi on, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the s top condi tion i s rece iv ed, an int er­nal write cycle will begin (Figure 6-2). If an attempt is
made to write to the arr ay with t he WP pin held h igh, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command.

6.3 Write Protection

The WP pin allows the user to write-protect the entire
array (000 0-3FFF) whe n the pi n is tie d to V

SS or left floating, the write protection is disabled. The

V
WP pin is sampled at the STOP bit for every write
command (Figure 1-1) Toggling the WP pin after the
STOP bit will have no effect on the execution of the
write cycle.

Note: Page write operations are limited to wri tin g

bytes within a single physical page, regard­less of the number of bytes actually being
written. Physical page bound aries start at
addresses that are integ er multiples of the

page buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page writ e command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored ther e),
instead of being written to the next page as
might be expected. It is therefore neces­sary for the app lica tion soft ware to pr event
page write operations that would attempt to
cross a page boundary .

CC. If tied to

FIGURE 6-1: BYTE WRITE

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = don’t care bit

S
T

CONTROL

A

BYTE

R
T

A1A

S1010 0

A

0

2

XX

A
C
K

ADDRESS

HIGH BYTE

A
C
K

ADDRESS
LOW BYTE

S

DATA

A
C
K

T
O
P

P11

A
C
K

FIGURE 6-2: PAGE WRITE

 1999 Microchip Technology Inc. Preliminary DS21191F-page 7

24AA128/24LC128/24FC128

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master
sending a start condition, followed by the control byte
for a write command (R/W
with the write cycle, then n o ACK will be returned. If no
ACK is returned, then the start bit and control b yte must
be resent. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.

= 0). If the de vice is still b usy

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

NO

Next

Operation

DS21191F-page 8 Preliminary  1999 Microchip Technology Inc.

24AA128/24LC128/24FC128

8.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.

8.1 Current Address Read

The 24XX128 contains an address counter that main­tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next curren t address re ad opera tion w ould acce ss data
from address n + 1.

Upon receipt of the cont rol byte w ith R/W
the 24XX128 issues an ack nowl edge and tr ansmit s the
8-bit data wo rd. The master wi ll not acknowledge the
transfer but does generate a stop condition and the
24XX128 discontinues trans m ission (Figure 8-1).

FIGURE 8-1: CURRENT ADDRESS READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T

CONTROL

A
R
T

S

1100

BYTE

AAA
210

1

A
C
K

FIGURE 8-2: RANDOM READ

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

X = Don’t Care Bit

S
T

CONTROL

A
R

BYTE

T
S1010

AAA
210

0

bit of the

bit set to one,

DAT A

BYTE

ADDRESS

HIGH BYTE

XX

A
C
K

S
T
O
P

P

N
O

A
C
K

A
C
K

8.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is don e by se nding the word address to th e
24XX128 as part of a write operati on (R/W

bit set to 0).
After the word addres s is sent, the master generates a
start condition following the acknowledge. This termi­nates the write operation, but not before the internal
address pointer is set. Then, the master issues the
control byte again b ut with the R/W

bit set to a one. The
24XX128 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24XX128 to discontinue transmission
(Figure 8-2). After a random read command, the inter­nal address counter will point to the address location
following the one that was just read.

8.3 Sequential Read

Sequential reads are initiat ed in th e same w ay as a r an­dom read except that after the 24XX128 transmits the
first data byte, the master issues an acknowledge as
opposed to the st op co nditi on us ed in a rando m read .
This acknowledge directs the 24XX128 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
Following the final byte transmitted to the master, the
master will NO T gen erate an ac knowl edge b ut will gen­erate a stop con dition . To provide sequential reads , th e
24XX128 contains an i nternal add res s po int er w hic h i s
increment ed by one at th e completi on of eac h opera­tion. This address pointer allows the entire memory
contents to be serially read during one operation. The
internal address pointer wil l automa tically rol l ov er from
address 3FFF to address 0000 if the master acknowl­edges the byte received from the array address 3FFF.

S

ADDRESS

LOW BYTE

T
A
R
T

S1010

A
C
K

CONTROL

BYTE

AAA
210

DAT A

BYTE

1

A
C
K

S
T
O
P

P

N
O

A
C
K

FIGURE 8-3: SEQUENTIAL READ

 1999 Microchip Technology Inc. Preliminary DS21191F-page 9

24AA128/24LC128/24FC128

NOTES:

DS21191F-page 10 Preliminary  1999 Microchip Technology Inc.

24AA128/24LC128/24FC128

24XX128 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24XX128 — /P

P = Plastic DIP (300 mil Body), 8-lead

Package:

SN = Plastic SOIC (150 mil Body)

ST = TSSOP, 8-lead

OT = SOT-23, 5-lead

Temperature
Range:

Device:

Blank = 0°C to +70°C

I = –40°C to +85°C

E = –40°C to +125°C

2

24AA128 128 bit 1.8V I

24AA128T 128 bit 1.8V K I2C Serial EEPROM (Tape and Reel)

24LC128 128 bit 2.5V I2C Serial EEPROM

24LC128T 128 bit 2.5V K I2C Serial EEPROM (Tape and Reel)

24FC128 128 bit 1MHz I2C Serial EEPROM

24FC128T 128 bit 1MHz I2C Serial EEPROM (Tape and Reel)

C Serial EEPROM

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: [phone]. After September 1, 1999, [phone]

3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 1999 Microchip Technology Inc. Preliminary DS21191F-page 11

WORLDWIDE SALES AND SERVICE

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ASIA/PACIFIC (continued)

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11/15/99

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro

devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 cer tified.

®

8-bit MCUs, KEELOQ

®

code hopping

All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.

Information contained in this publi c ation regarding device applic at i ons and the like is intended for sugge st i on onl y and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip T echnology Incorpora ted with respect to the accuracy or use of such information, or infringe ment of patents or othe r intellec tual property rights arising from such use or otherwis e. Use of Microchi p’s produc ts
as critical components in life s upport systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicit ly or otherwise, under any inte lle ct ual property rights. The Microchip
logo and name are registered trademarks of Mi crochip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective com panies.

 1999 Microchip Technology Inc.