MICROCHIP 24AA1025, 24LC1025, 24FC1025 Technical data

24AA1025/24LC1025/24FC1025

1024K I2C™ CMOS Serial EEPROM

Device Selection Table:

Part

Number

24AA1025 1.7-5.5V 400 kHz
24LC1025 2.5-5.5V 400 kHz* I, E
24FC1025 2.5-5.5V 1 MHz I

†

100 kHz for VCC < 2.5V.

*100 kHz for V

VCC

Range

CC < 4.5V, E-temp.

Max. Clock

Frequency

†

Temp

Ranges

I

Features:

• Single supply with operation down to 1.7V for
24AAXX devices, 2.5V for 24LCXX devices

• Low-power CMOS technology:

- Read current 1 mA, typical

- Standby current 100 nA, typical

• 2-wire serial interface, I2C™ compatible

• Cascadable up to four devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz and 400 kHz clock compatibility

• 1 MHz clock for FC versions

• Page write time 3 ms, typical

• Self-timed erase/write cycle

• 128-byte page write buffer

• Hardware write-protect

• ESD protection >400 V

• More than 1 million erase/write cycles

• Data retention >200 years

• Factory programming available

• Packages include 8-lead PDIP, SOIJ

• Pb-free and RoHS compliant

• Temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E):-40°C to +125°C

This device is capable of both random and sequential
reads. Reads may b e sequential within addres s bound­aries 0000h to FFFFh and 10000h to 1FFFFh.
Functional addre ss lines allow up t o four de vices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP and SOIJ packages.

Package Type

PDIP

SOIJ

A0

1

A1

2

A2

3

V

SS

4

1

A0

2

A1

3

A2

4

SS

V

VCC

8

WP

7

SCL

6

SDA

5

8

V

CC

7

WP

6

SCL

5

SDA

Block Diagram

A0A1

Control

I/O

SDA

I/O

Logic

SCL

WP

Memory
Control

Logic

XDEC

HV Generator

EEPROM

Array

Page Latches

YDEC

V

Description:

The Microchip Technology Inc. 24AA1025/24LC1025/

VSS

CC

Sense AMP

Control

R/W

24FC1025 (24XX1025*) is a 128K x 8 (1024K bit)
Serial Ele ctrically E rasable PROM, capable of op era­tion across a broad vo lta ge range (1.8V to 5 .5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device has both byte write and page write
capability of up to 128 bytes of data.

© 2007 Microchip Technology Inc. Preliminary DS21941E-page 1

*24XX1025 is used in this document as a generic part number
for the 24AA1025/24LC1025/24FC1025 devices.

24AA1025/24LC1025/24FC1025

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS .........................................................................................................-0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS

Param.

No.

Sym. Characteristic Min. Max. Units Conditions

D1 A0, A1, SCL, SDA and

Industrial (I): V
Automotive (E): V

———

WP pins:

D2 V

IH High-level input voltage 0.7 VCC —V

D3 VIL Low-level input voltage — 0.3 VCC

D4 V

HYS Hysteresis of Schmitt

CC —VVCC ≥ 2.5V (Note)

0.05 V
Trigger inputs
(SDA, SCL pins)

D5 VOL Low-level output voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V

D6 ILI Input leakage current — ±1 μAVIN = VSS or VCC, WP = VSS

D7 ILO Output leakage current — ±1 μAVOUT = VSS or VCC
D8 CIN,

C

OUT

Pin capacitance
(all inputs/outpu t s)

—10pFVCC = 5.0V (Note)

D9 ICC Read Operating current — 450 μAVCC = 5.5V, SCL = 400kHz

ICC Write — 5 mA VCC = 5.5V

D10 I

CCS Standby current — 5

Note: This parameter is periodically sampled and not 100% tested.

CC = +1.7V to 5.5V TA = -40°C to +85°C

CC = +2.5V to 5.5VTA = -40°C to +125°C

VVVCC ≥ 2.5V

0.2 VCC

CC < 2.5V

V

OL = 2.1 mA @ VCC = 2.5V

I

VIN = VSS or VCC, WP = VCC

T

A = 25°C, FCLK = 1 MHz

μATA = -40°C to 85°C

SCL = SDA = V
A0, A1, WP = V

CC = 5.5V
SS, A2 = VCC

DS21941E-page 2 Preliminary © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025

TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS

Param.

No.

1F

2T

3T

4T

5T

6T

7T

8T
9T

10 T

11 T

12 T

13 T

14 T

15 T

16 T

Note 1: Not 100% tested. C

Sym. Characteristic Min. Max. Units Conditions

CLK Clock frequency —

HIGH Clock high time 4000

LOW Clock low time 4700

R SDA and SCL rise time

(Note 1)

F SDA and SCL fall time

(Note 1)

HD:STA Start condition hold time 4000

SU:STA Start condition setup time 4700

HD:DAT Data input hold time 0 — ns (Note 2)

SU:DAT Data input setup time 250

SU:STO Stop condition setup time 4000

SU:WP WP setup time 4000

HD:WP WP hold time 4700

AA Output valid from clock

(Note 2)

BUF Bus free time: Time the bus

must be free before a new
transmission can start

OF Output fall time from VIH

minimum to VIL maximum

B ≤ 100 pF

C

SP Input filter spike suppression

(SDA and SCL pins)

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combine d T

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but established by characterization. For endurance e stimates in a specific application,

please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used.

Industrial (I): V
Automotive (E): V

—
—

600
500

1300

500

—
—
—

—
—

600
250

600
250

100
100

600
250

600
600

1300
1300

—
—
—

4700
1300

500

10 + 0.1C

CC = +1.7V to 5.5V TA = -40°C to +85°C

CC = +2.5V to 5.5V TA = -40°C to +125°C

100
400

1000

—
—
—

—
—
—

1000

300
300

300
100

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

—
—
—

3500

900
400

—
—
—

B 250

250

kHz 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V (Note 5)
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns All except, 24FC1025

2.5V ≤ V

CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns 1.7V ≤ VCC ≤ 2.5V

2.5V ≤ V

2.5V ≤ V

CC ≤ 5.5V
CC ≤ 5.5V (24FC1025 only)

ns All except, 24FC1025 (Note 1)

24FC1025 (Note 1)

— 50 ns All except, 24FC1025 (Notes 1 and 3)

B = total capacitance of one bus line in pF.

SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike

© 2007 Microchip Technology Inc. Preliminary DS21941E-page 3

24AA1025/24LC1025/24FC1025

AC CHARACTERISTICS (Continued)

Param.

No.

17 TWC Write cycle time (byte or page) — 5 ms 3 ms, typical
18 Endurance 1 M — cycles 25°C (Note 4)

Note 1: Not 100% tested. C

Sym. Characteristic Min. Max. Units Conditions

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but established by characterization. For endurance e stimates in a specific application,

please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.

5: Max. clock frequency is 100 kHz for E-temp devices <4.5V. 1.7-2.5V (100 kHz) timings must be used.

SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike

Industrial (I): V
Automotive (E): V

CC = +1.7V to 5.5V TA = -40°C to +85°C

CC = +2.5V to 5.5V TA = -40°C to +125°C

FIGURE 1-1: BUS TIMING DATA

SCL

SDA
IN

16

5

7

6

3

2

89

D4

4

10

SDA
OUT

WP

13

(protected)

(unprotected)

14

11

12

DS21941E-page 4 Preliminary © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP SOIJ Function

A0 1 1 User Configurable Chip Select
A1 2 2 User Configurable Chip Select
A2 3 3 Non-Configurable Chip Select.

This pin must be hard-wired to
logical 1 state (V
will not operate with this pin
left floating or held to logical 0

SS).

(V

VSS 4 4 Ground
SDA 5 5 Serial Data
SCL 6 6 Serial Clock

WP 7 7 Write-Protect Input

CC 8 8 +1.7 to 5.5V (24AA1025)

V

+2.5 to 5.5V (24LC1025)
+2.5 to 5.5V (24FC1025)

2.1 A0, A1 Chip Address Inputs

CC). Device

2.4 Serial Clock (SCL)

This input is used to sync hronize the data trans fer from
and to the device.

2.5 Write-Protect (WP)

This pin must be conne cted to eithe r VSS or VCC. If tied

SS, write operations are enabled. If tied to VCC,

to V
write operations are inhibited, but read operations are
not affected.

3.0 FUNCTIONAL DESCRIPTION

The 24XX1025 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data, as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1025 works as a slave. Both master and slave
can operate as a transmitt er or receive r , but the m aster
device determines which mode is activated.

The A0, A1 inputs are used by the 24XX1025 fo r multi­ple device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.

Up to four devices may be connected to the same bus
by using differ ent Chip Sele ct bit com binations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which thes e pin s ar e c o nt ro ll ed b y a m ic r oc ont r ol l er o r
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.

2.2 A2 Chip Address Input

The A2 input is non-configurable Chip Select. This pin
must be tied to V

CC in order for this device to operate.

2.3 Serial Data (SDA)

This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open­drain terminal, therefore, the SDA bus requires a pull­up resistor to V
400kHz and 1MHz).

For normal data t ransfer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for indicatin g the Start and Stop conditions.

CC (typical 10 kΩ for 100 kHz, 2 kΩ for

© 2007 Microchip Technology Inc. Preliminary DS21941E-page 5

24AA1025/24LC1025/24FC1025

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable wheneve r the c lock lin e is high . Changes i n
the data line while the clock line is high will be
interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been
defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.

The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.

Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.

Note: The 24XX1025 does not generate any

Acknowledge bits if an internal program­ming cycle is in progress, however, the
control byte that is being polled must
match the control byte used to initiate the
write cycle.

A device that acknowledges must pull-down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is sta ble low d uring the high pe riod of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master m ust s ignal an end of dat a to the sl ave
by NOT generating an Acknow ledge bit on the las t byte
that has been cl ocke d out o f the slave . In th is ca se , the
slave (24XX1025) will leave the data line high to enabl e
the master to generate the Stop condition.

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2: ACKNOWLEDGE TIMING

DS21941E-page 6 Preliminary © 2007 Microchip Technology Inc.

24AA1025/24LC1025/24FC1025

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte c onsis ts of a 4-bit c ontrol code; fo r the
24XX1025, this is set as ‘1010’ binary for read and
write operations. The next bit of the control byte is the
block select bit (B0). This bit acts as the A16 address
bit for accessing the entire array. The next two bits of
the control by te ar e the Chi p Select bits (A1, A0). T he
Chip Select bits allow the use of up to four 24XX1025
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control
byte must correspond to the logic levels on the corre­sponding A1 and A0 pins for the device to respond.
These bits are in effect the two Most Significant bits of
the word address.

The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). The upper
address bits are transferred first, followed by the Less
Significant bits.

Following the Start condition, the 24XX1025 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and appro­priate device select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R /W
write operation.

This device has an internal addressing boundary
limitation that is divided into tw o segment s of 512K bits.
Block select bit ‘B0’ to control ac cess to each s egment.

bit, the 24XX1025 wil l sel ec t a re ad or

FIGURE 5-1: CONTROL BYTE

FORMAT

Chip

Select

Bits

Bit

Read/Write

Block

Select

Control Code

1010B0 A1 A0SACKR/W

Slave Address

Start Bit

Bits

Acknowledge Bit

5.1 Contiguous Addressing Across
Multiple Devices

The Chip Select bits A1, A0 can be used to exp and th e
contiguous add ress sp ace for up to 4 Mbit by add ing up
to four 24XX1025’s on the same bus. In this case,
software ca n use A0 of th e c ontr ol by te
A16 and A1 as address bit A17. It is not possible to
sequentially read across device boundaries.

Each device has internal addressing boundary
limitations. This divides each part into two segments of
512K bits. The block select bit ‘B0’ controls access to
each “half”.

Sequential read operations are limited to 512K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.

as address bit

FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte Address High Byte Address Low Byte

A

A

A

1 010

Control

Code

© 2007 Microchip Technology Inc. Preliminary DS21941E-page 7

B0A1A

Block

Select

Bit

0

Chip

Select

Bits

R/W

15

A

14

13

12

A11A10A

A

9

8

A

••••••

7

X = “don’t care” bit

A
0