MICROCHIP 24AA024, 24LC024, 24AA025, 24LC025 Technical data

24AA024/24LC024/24AA025/24LC025

L A

2K I2C™ Serial EEPROM

Device Selection Table

Part

Number

24AA024 1.7V-5.5V 400 kHz 24AA025 1.7V-5.5V 400 kHz 24LC024 2.5V-5.5V 400 kHz I Yes

24LC025 2.5V-5.5V 400 kHz I No

Note 1: 100 kHz for V

VCC

Range

Max

Clock

CC < 2.5V

Temp.

Range

(1)

IYes

(1)

INo

Write

Protect

Features:

• Single supply with op eration from 1.7 V to 5.5 V for 24AA024/24AA025 device s, 2.5V for 24LC024/ 24LC025 devices

• Low-power CMOS technology:

- Read current 1 mA, typical

- Standby current 1 μA, typical

• 2-wire serial interface, I

• Cascadable up to eight devices

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz and 400 kHz clock compatibility

• Page write time 5 ms maximu m

• Self-timed erase/write cycle

• 16-byte page write buffer

• Hardware write-protect on 24XX024 devices

• ESD protection >4,000V

• More than 1 million erase/write cycles

• Data retention >200 years

• Factory programming available

• Packages include 8-lead PDIP, SOIC, TSSOP, DFN and MSOP

• Pb-free and RoHS compliant

• Temperature ranges:

- Industrial (I): -40°C to +85°C

C™ compatible

Description:

The Microchip Technology Inc. 24AA024/24LC024/ 24AA025/24LC025 is a 2 Kbit Serial Electrically Erasable PROM with a voltage range of 1.7V to 5.5V. The device is organi zed as a singl e block of 256 x8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 1 μA and 1 mA, respectively. The device has a page write capability for up to 16 bytes of data. Functional address lines allow the connection of up to eight 24AA024/24LC024/ 24AA025/24LC025 devices on the same bus for up to 16K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (3.90 mm), TSSOP, 2x3 DFN and MSOP packages.

Package Types

A0 A1

8 7 6 5

SOIC, TSSOP

1 2

3 4

WP SCL SDA

PDIP, MSOP

Note: WP pin is not internally connected on the

A0 A1

24XX025

VCC WP

SCL

SDA

DFN

1 2

Block Diagram

A0 A1 A2

I/O

Control

Logic

WP*

Memory

Control

Logic

HV Generator

XDEC

EEPROM

Array

SDA

SCL

V VSS

Write-Protect

Circuitry

YDEC

Sense Amp. R/W Control

24AA024/24LC024/24AA025/24LC025

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stres s ratin g only and func tional operati on of the devic e at thos e or any other co nditio ns abov e thos e indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

SS .........................................................................................................-0.6V to VCC +1.0V

(†)

TABLE 1-1: DC CHARACTERISTICS

All parameters apply across the specified operating ranges unless otherwise noted.

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High-level input voltage VIH 0.7 VCC —V— Low-level input voltage VIL — 0.3 VCC V— Hysteresis of Schmitt Trigger inputs V Low-level output voltage VOL —0.40VIOL = 3.0 mA, VCC = 4.5V

Input leakage current I Output leakage current ILO —±1μAVOUT = VSS or VCC Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note)

Operating current ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz

Standby current I

Note: This parameter is periodically sampled and not 100% tested.

CC = 1.7V to 5.5V

V Industrial (I): T

HYS 0.05 VCC —V(Note)

LI —±1μAVIN = VSS or VCC

ICC Write — 3 mA VCC = 5.5V

CCS —1μAVCC = 5.5V, SDA = SCL = VCC

A = -40°C to +85°C

OL = 2.1 mA, VCC = 2.5V

A = 25°C, FCLK = 1 MHz

WP = V

SS, A0, A1, A2 = VSS

24AA024/24LC024/24AA025/24LC025

TABLE 1-2: AC CHARACTERISTICS

All parameters apply across the specified operating ranges unless otherwise noted.

CC = 1.7V to 5.5V

Industrial (I): T

A = -40°C to +85°C

Parameter Symbol

STD MODE

Vcc = 2.5V - 5.5V

FAST MODE

Units Remarks

Min. Max. Min. Max.

Clock frequency F

CLK — 100 — 400 kHz —

Clock high time THIGH 4000 — 600 — ns — Clock low time TLOW 4700 — 1300 — ns — SDA and SCL rise time T

R — 1000 — 300 ns (Note 1)

SDA and SCL fall time TF — 300 — 300 ns (Note 1) Start condition hold time THD:STA 4000 — 600 — ns After this period the first

clock pulse is generated

Start condition setup time T

SU:STA 4700 — 600 — ns Only relevant for repeated

Start condition

Data input hold time T

HD:DAT 0—0—ns(Note 2)

Data input setup time TSU:DAT 250 — 100 — ns — Stop condition setup time TSU:STO 4000 — 600 — ns — Output valid from clock T

AA — 3500 — 900 ns (Note 2)

Bus free time TBUF 4700 — 1300 — ns Time the bus must be free

before a new transmission can start

Output fall time from VIH minimum to VIL maximum

Input filter spik e s upp res si on

OF — 250 20 +0.1

SP — 50 — 50 ns (Note 3)

250 ns (Note 1), CB ≤ 100 pF

(SDA and SCL pins) Write cycle time T

WC — 5 — 5 ms Byte or Page mode

Endurance 1M — 1M — cycles 25°C, (Note 4) Note 1: Not 100% tested. C

B = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined T

SP and VHYS specifications are due to Schmitt Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com.

24AA024/24LC024/24AA025/24LC025

FIGURE 1-1: BUS TIMING DATA

SCL

SDA IN

SDA OUT

TSU:STA

TSP

THD:STA

TLOW

THIGH

THD:DAT TSU:DAT TSU:STO

TAA

TBUF

24AA024/24LC024/24AA025/24LC025

2.0 PIN DESCRIPTIONS

Pin Function Table

Name PDIP SOIC TSSOP DFN MSOP Description

A01111 1 Address Pin AO A12222 2 Address Pin A1 A23333 3 Address Pin A2

SS 4444 4 Ground

V SDA5555 5 Serial Address/Data I/O SCL6666 6 Serial Clock WP7777 7 Write-Protect Input

CC 8888 8 +1.7 to 5.5V Power Supply

2.1 SDA Serial Data

SDA is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to V 400 kHz).

For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.

CC (typical 10 kΩ for 100 kHz, 2 kΩ for

2.2 SCL Serial Clock

The SCL input is used to sync hro ni ze th e da t a tra ns fer from and to the device.

2.3 A0, A1, A2

The levels on the A0, A1 and A2 inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true.

Up to eight 24AA024/24LC024/24AA025/24LC025 devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either V

CC or VSS.

2.4 WP (24XX024 Only)

2.5 Noise Protection

The 24AA024/24LC024/24AA025/24LC025 employs a V

CC threshold detector circuit which disables the

internal erase/write logic if th e V nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus.

CC is below 1.5 v olt s at

3.0 FUNCTIONAL DESCRIPTION

The 24AA024/24LC024/24AA025/24LC025 supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24AA024/ 24LC024/24AA025/24LC025 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.

WP is the hardware write-protect pin. It must be tied to V

CC or VSS. If tied to Vcc, hardware write protection is

enabled. If WP is tied to Vss, the hardware write protection is disabled. Note that the WP pin is avail able only on the 24XX024. This pin is not internally connected on the 24LC025.

24AA024/24LC024/24AA025/24LC025

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable wheneve r the c lock lin e is high . Changes i n the data line while the clock line is high will be interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been defined (Figure 4-1).

4.1 Bus Not Busy (A)

Both data and clock lines remain high.

4.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.

4.3 Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.

4.4 Data Valid (D)

The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal.

The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse.

Each data transfer is initiated with a S tart condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is, theoretically , u nlimited, (thoug h only the last six teen will be stored when performin g a write ope ration). When an overwrite does occur, it will replace data in a first-in first-out fashion.

4.5 Acknowledge

Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The ma ster devi ce m ust gener at e an ex tr a cloc k pulse which is associated with this Acknowledge bit.

Note: The 24AA024/24LC024/24AA025/24LC025

does not generate any Acknowledge bits if an internal programming cycle is in progress.

The device that acknowledges has to pull dow n the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Fi gure4-2).

FIGURE 4-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS

(A) (B) (C) (D) (A)(C)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

FIGURE 4-2: ACKNOWLEDGE TIMING

Acknowledge

Bit

SCL

SDA

Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.

987654321 123

Data from transmitterData from transmitter

Receiver must release the SDA line at this point so the Transmitter can continue sending data.

Stop

Condition

24AA024/24LC024/24AA025/24LC025

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte co nsi sts of a four-bit control cod e. F or the 24AA024/24LC024/24AA025/24LC025, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA024/24LC024/24AA025/24LC025 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respon d. These bits are in effect t he three Mos t Significant bits of the word address.

The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. Following the Start condition, the 24AA024/ 24LC024/24AA025/24LC025 monitors the SDA bus checking the control byte being transmitted. Upon receiving a ‘1010’ code and appropriate Chip Select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W the 24AA024/24LC024/24AA0 25/24LC025 wi ll select a read or write operation.

bit,

FIGURE 5-1: CONTROL BYTE FORMAT

Start Bit

Read/Write

Chip Select

Control Code

101 0A2 A1 A0SACKR/W

Slave Address

Acknowledge Bit

Bit

Bits

5.1 Contiguous Addressing Across Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to expand the co ntiguous address space for up to 16K bits by adding up to eight 24AA024/24LC024/24AA025/ 24LC025 devices on the same bus. In this case, software can use A0 of th e con tro l byt e as address bit A8, A1 as address bit A9 and A2 as address bit A10. It is not possible to sequentially read across device boundaries.

24AA024/24LC024/24AA025/24LC025

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the Start signal from the master, the device code(4 bits), the Chip Select bits (3 bits) and theR/W bit (which is a logic-low) is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth cloc k pulse. The ne xt byte transmitte d by th e maste r is the word ad dr ess and w ill be written into the Address Pointer of the 24AA024/ 24LC024/24AA025/24LC025. After receiving another Acknowledge signal from the 24AA024/24LC024/ 24AA025/24LC025, the master device will transmit the data word to be written into the addressed memory location. The 24AA024/24LC024/24AA025/24LC025 acknowledges again and the master generates a Stop condition. This ini tiates the interna l write cycle an d, during this time, the 24AA024/24LC024/24AA025/ 24LC025 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection (24XX024 only) has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if write protection is enabled.

6.2 Page Write

The write control byte, word address and the first data byte are transmitted to the 24AA024/24LC024/ 24AA025/24LC025 in the same way as in a byte write. However, instead of generating a Stop condition, the master transmits up to 15 additional data bytes to the 24AA024/24LC024/24AA025/24LC025, which are temporarily stored in the on-chip pa ge buffer and will be written into the memory once the master has transmitted a Stop condition. Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by one.

The higher-order four bits of the word address remain constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data w ill be ov erwritten . As w ith t he by te-write operation, once the Stop condition is received, an internal write cycle wil l begin (Figure6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will ack nowled ge th e comma nd, but no dat a will be written. The write cycle time must be observed even if write protection is enabled.

Note: Page write operations are limite d to writing

bytes within a single physical page,

regardless

of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buf fer size (or ‘page size’) an d end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might b e expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.

6.3 Write Protection

The WP pin (available on 24XX024 only) must be tied

CC or VSS. If tie d to VCC, the entire array will be

to V write-protected. If the WP pin is tied to V operations to all address locations are allowed.

SS, write

FIGURE 6-1: BYTE WRITE

BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

S T A R T

S P

Control

Byte

Word

Address

A C K

Data

S T O P

A C K

FIGURE 6-2: PAGE WRITE

S BUS ACTIVITY MASTER

SDA LINE

BUS ACTIVITY

Control

S P

Byte

A C K

Word

Address

(n)

Data (n) Data (n + 15)

A C K

Data (n +1)

A C K

S T O P

A C K

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