MICROCHIP 24AA00, 24LC00, 24C00 Technical data
24AA00/24LC00/24C00
128-Bit I2C™ Bus Serial EEPROM
Device Selection Table
Device VCC Range Temp Range
24AA00 1.8-5.5 C,I
24LC00 2.5-5.5 C,I
24C00 4.5-5.5 C,I,E
Features:
• Low-power CMOS technology:
- 500 μA typical ac tive current
- 250 nA typical standby current
• Organized as 16 bytes x 8 bits
• 2-wire serial interface bus, I
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• 4 ms maximum byte write cycle time
• 1,000,000 erase/write cycles
• ESD protection > 4 kV
• Data retention > 200 years
• 8L PDIP, SOIC, TSSOP, DFN and 5L SOT-23
packages
• Pb-free finish available
• Temperature ranges available:
- Commercial (C): 0°Cto+70°C
- Industrial (I): -40°Cto+85°C
- Automotive (E): -40°C to +125°C
2
C™ compatible
Package Types
8-PIN PDIP/SOIC
NC
NC
NC
Vss
8-PIN TSSOP
1
NC
2
NC
3
NC
SS
4
V
5-PIN SOT-23
SCL
15
SS
V
2
SDA
3
Block Diagram
I/O
Control
Logic
Memory
Control
1
2
3
4
4
Logic
VCC
NC
V
XDEC
NC
NC
NC
CC
V
8
7
NC
6
SCL
5
SDA
8
VCC
7
NC
6
SCL
5
SDA
DFN
1
2
3
SS
4
HV Generator
8
7
6
5
EEPROM
Array
CC
V
NC
SCL
SDA
Description:
SCL
The Microchip Technology Inc. 24AA00/24LC00/
24C00 (24XX00*) is a 128-bit Electrically Erasable
PROM memory organized as 16 x 8 with a 2-wire
serial interface. Low-voltage design permits operation
down to 1.8 volts for th e 24AA00 version, an d every
version maintains a maximum standby current of only
1 μA and typical active current of only 500 μA. This
device was designed for where a small amount of
EEPROM is needed for the storage of calibration
values, ID numbers or manufacturing information, etc.
The 24XX00 is available in 8-pin PDIP, 8-pin SOIC
(150 mil), 8-pin TSS OP, 8-pin 2x3 DFN and the 5-pin
SOT-23 packages.
I2C is a trademark of Philips Corporation.
*24XX00 is used in this document as a generic part number for
the 24AA00/24LC00/24C00 devices.
© 2005 Microchip Technology Inc. DS21178E-page 1
SDA
VCC
VSS
Pin Function Table
Name Function
V
SS Ground
SDA Serial Data
SCL Serial Clock
CC +1.8V to 5.5V (24AA00)
V
+2.5V to 5.5V (24LC00)
+4.5V to 5.5V (24C00)
NC No Internal Connection
YDEC
Sense AMP
R/W
Control
24AA00/24LC00/24C00
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indica ted in the opera tional li stings of this sp ecification is not i mplied. Ex posure to maximum rating
conditions for extended periods may affect device reliability.
(†)
SS ......................................................................................................... -0.6V to VCC +1.0V
TABLE 1-1: DC CHARACTERISTICS
All Parameters apply across the
recommended operating ranges unless
otherwise noted
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High-level input voltage
Low-level input voltage VIL —0.3 VCC V (Note)
Hysteresis of Schmitt Trigger
inputs
Low-level output voltage V
Input leakage current I
Output leakage current ILO —±1μAVOUT = VCC or VSS
Pin capacitance (all inputs/outputs) CIN,
Operating current ICC Write — 2 mA VCC = 5.5V, SCL = 400 kHz
Standby current I
Note: This parameter is periodically sampled and not 100% tested.
Commercial (C): TA = 0°C to +70°C, VCC = 1.8V to 5.5V
Industrial (I): T
Automotive (E) T
VIH 0.7 VCC —V(Note)
VHYS .05 VCC —VVCC ≥ 2.5V (Note)
OL —0.4VIOL = 3.0 mA, VCC = 4.5V
LI —±1μAVIN = VCC or VSS
C
OUT
ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz
CCS —1μAVCC = 5.5V, SDA = SCL = VCC
A = -40°C to +85°C, VCC = 1.8V to 5.5V
A = -40°C to +125°C, VCC = 4.5V to 5.5V
OL = 2.1 mA, VCC = 2.5V
I
—10pFVCC = 5.0V (Note)
T
A = 25°C, FCLK = 1 MHz
FIGURE 1-1: BUS TIMING DATA
TF
SCL
SDA
IN
SDA
OUT
DS21178E-page 2 © 2005 Microchip Technology Inc.
TSU:STA
TSP
HD:STA
T
TLOW
THIGH
THD:DAT
TAA
TSU:DAT
TR
TSU:STO
TBUF
TABLE 1-2: AC CHARACTERISTICS
24AA00/24LC00/24C00
All Parameters apply across all
recommended operating ranges
unless otherwise noted
Commercial (C): T
Industrial (I): T
Automotive (E): T
A = 0°C to +70°C, VCC = 1.8V to 5.5V
A = -40°C to +85°C, VCC = 1.8V to 5.5V
A = -40°C to +125°C, VCC = 4.5V to 5.5V
Parameter Symbol Min Max Units Conditions
Clock frequency F
Clock high time THIGH 4000
Clock low time TLOW 4700
SDA and SCL rise time
(Note 1)
CLK —
—
—
4000
600
4700
1300
TR —
—
—
100
100
400
—
—
—
—
—
—
1000
1000
300
kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL fall time TF —300ns(Note 1)
Start condition hold time THD:STA 4000
4000
600
Start condition setup time TSU:STA 4700
4700
600
—
—
—
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
Data input hold time THD:DAT 0—ns(Note 2)
Data input setup time T
Stop condition setup time T
Output valid from clock
(Note 2)
Bus free time: T i me the b us must
be free before a new transmission can start
Output fall time from V
IH
minimum to VIL maximum
Input filter spike suppression
SU:DAT 250
250
100
SU:STO 4000
4000
600
AA —
T
—
—
BUF 4700
T
4700
1300
T
OF 20+0.1
—
—
—
—
—
—
3500
3500
900
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
1.8V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V
250 ns (Note 1), CB ≤ 100 pF
CB
SP —50ns(Notes 1, 3)
T
(SDA and SCL pins)
Write cycle time T
WC —4ms
Endurance 1M — cycles (Note 4)
Note 1: Not 100% tested. C
B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combine d T
SP and VHYS specifications are due to new Schmit t Trigger inputs w h ic h p rov id e i mp rov ed
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by c haracterization. For endurance estimates in a speci fic
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.
© 2005 Microchip Technology Inc. DS21178E-page 3
24AA00/24LC00/24C00
2.0 PIN DESCRIPTIONS
2.1 SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
400 kHz).
For normal data t ransfer SDA is all owed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
CC (typical 10 kΩ for 100 kHz, 2 kΩ for
2.2 SCL Serial Clock
This input is u sed t o sy nchron ize the d ata trans fer fro m
and to the device.
2.3 Noise Protection
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
3.0 FUNCTIONAL DESCRIPTION
The 24XX00 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus has to be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions, while the
24XX00 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable wheneve r the cl ock lin e is high . Changes i n
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to- lo w t ran si t i on of t h e SD A l in e whi l e t h e c lo ck
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a S tart condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited.
DS21178E-page 4 © 2005 Microchip Technology Inc.
24AA00/24LC00/24C00
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note: The 24XX00 does not generate any
Acknowledge bits if an internal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowl edge cloc k pulse in s uch a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not gene rati ng an Ac kno w led ge bi t o n th e last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figur e 4-2).
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A)
Condition
(B)
Start
(C)
Address or
Acknowledge
Valid
Data
Allowed
to Change
(D)
FIGURE 4-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
Stop
Condition
(A)(C)
SCL
SDA
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
987654321 123
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
© 2005 Microchip Technology Inc. DS21178E-page 5
24AA00/24LC00/24C00
5.0 DEVICE ADDRESSING
After generating a Start condition, the bus master
transmits a control byte consisting of a slave address
and a Read/Write bit that indicates what type of
operation is to be perfo rmed. The sl ave addres s for the
24XX00 consists of a 4-bit device code ‘1010’ followed
by three “don’t care” bits.
The last bit of the control byte determine s the operation
to be performed. When set to a o ne a read operati on is
selected, and when set to a zero a write operation is
selected (Figure 5-1). The 24XX00 monitors the bus for
its corresponding slave address all the time. It
generates an Ackn owledge bit if the sla ve addres s was
true and it is not in a programming mode.
FIGURE 5-1: CONTROL BYTE FORMAT
Bit
Bits
Start Bit
Read/Write
Device Select
Bits
1010xxxSACKR/W
Slave Address
Don’t Care
Acknowledge Bit
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code (4 bits), the “don’t care” bits (3 bits), and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowl edge bit durin g
the ninth clock cycl e. Therefore, the next byte t ransmitted by the master is the word address and will be
written into the Address Pointer of the 24XX00. Only
the lower four address bit s are us ed by t he device , and
the upper four bits are “don’t cares.” The 24XX00 will
acknowledge the address byte and the master device
will then transmit the data word to be written into the
addressed memory location. The 24XX00 acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle, and
during this time the 24XX00 will not ge nerate Ack now ledge signals (Figure7-2). After a by te Wr ite co mmand,
the internal address counter will not be incremented
and will point to the s ame address lo cation that was jus t
written. If a Stop bit is transmitted to the device at any
point in the Write comman d sequenc e before the e ntire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the Stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a Stop bit is sent before a
full eight data bits have been transmitted, then the
Write command will abort and no data will be written.
The 24XX00 employs a V
which disables the internal erase/write logic if the V
is below 1.5V (24AA00 and 24LC00) or 3.8V (24C00)
at nominal conditions.
CC threshold detector circuit
CC
DS21178E-page 6 © 2005 Microchip Technology Inc.
24AA00/24LC00/24C00
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issu ed from the mas ter , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W
busy with the write cycle, then no ACK will be returned.
If no ACK is returne d, then th e S t art bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the master can then
proceed with the next Read or Write command. See
Figure 7-1 for flow diagram.
= 0). If the device is still
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Yes
No
FIGURE 7-2: BYTE WRITE
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
x = “don’t care” bit
T
A
R
T
S
10 x10 xxx
Control
Byte
Next
Operation
Word
Address
A
C
K
xxx
A
C
K
0
Data
S
T
O
P
P
A
C
K
© 2005 Microchip Technology Inc. DS21178E-page 7
24AA00/24LC00/24C00
8.0 READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to one. The re are three ba sic types
of read operations: current add ress read , rand om rea d
and sequential read.
8.1 Current Address Read
The 24XX00 contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would acc ess dat a f rom add ress n + 1. Upon
receipt of the slave a ddress with the R/W
the device issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer , but does generate a S top con dition and the
device discontinues transmission (Figure8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operatio n, fi rst the word address must
be set. This is d one by sending the word a ddress to the
device as part of a write operation.
bit of the
bit set to one,
After the word address is sent, the master generates a
Start condition following the acknowledge. This terminates the write operation, but not before the internal
Address Pointer is set. Then the master issues the
control byte again, but with the R/W
bit set to a one.
The 24XX00 will then i ssue an ack nowledge a nd transmits the eight bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the device discontinues transmission
(Figure 8-2). After this command, the internal address
counter will point to the address location following the
one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the device transmits the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide se quential reads the 2 4XX00 contains an
internal Address Pointer which is incremented by one
at the complet ion o f e ach r ead o peratio n. Thi s Add ress
Pointer allows the entire memory contents to be serially
read during one operation.
FIGURE 8-1: CURRENT ADDRESS READ
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
x = “don’t care” bit
T
A
R
T
1100xxx1
Control
Byte
S
Data
A
C
K
T
O
P
PS
N
O
A
C
K
DS21178E-page 8 © 2005 Microchip Technology Inc.
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