3.3V 1:9 HIGH-PERFORMANCE,
LOW-VOLTAGE
BUS CLOCK DRIVER
ClockWorks™
SY89809L
FEATURES
■ 3.3V core supply, 1.8V output supply for reduced
power
■ LVPECL and HSTL inputs
■ 9 differential HSTL (low-voltage swing) output pairs
■ HSTL outputs drive 50Ω to ground with no
offset voltage
■ 500MHz maximum clock frequency
■ Low part-to-part skew (200ps max.)
■ Low pin-to-pin skew (50ps max.)
■ Available in 32-pin TQFP package
PIN CONFIGURATION
Q0
VCCI
HSTL_CLK
HSTL_CLK
CLK_SEL
LVPECL_CLK
LVPECL_CLK
GND
OE
VCCO
Q0
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
910111213141516
Q8
VCCO
Q1
Q1
Top View
TQFP
T32-1
Q7
Q8
Q7
Q2
Q6
Q2
Q6
VCCO
24
23
22
21
20
19
18
17
VCCO
VCCO
Q3
Q3
Q4
Q4
Q5
Q5
VCCO
DESCRIPTION
The SY89809L is a High-Performance Bus Clock Driver
with 9 differential HSTL (High-Speed Transceiver Logic)
output pairs. The part is designed for use in low-voltage
(3.3V/1.8V) applications which require a large number of
outputs to drive precisely aligned, ultralow skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
The SY89809L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)—performance
previously unachievable in a standard product having such
a high number of outputs. The SY89809L is available in a
single space saving package, enabling a lower overall cost
solution.
APPLICATIONS
■ High-performance PCs
■ Workstations
■ Parallel processor-based systems
■ Other high-performance computing
■ Communications
PIN NAMES
Pin Function
HSTL_CLK, /HSTL_CLK Differential HSTL Inputs
LVPECL_CLK, /LVPECL_CLK Differential LVPECL Inputs
CLK_SEL Input CLK Select (LVTTL)
OE Output Enable (LVTTL)
Q0-Q8, /Q0-/Q
8
GND Ground
V
CCI
V
CCO
Differential HSTL Outputs
VCC Core
VCC Output
LOGIC SYMBOL
CLK_SEL
HSTL_CLK
HSTL_CLK
LVPECL_CLK
LVPECL_CLK
OE
1
0
9
Q0 – Q8
9
Q0 – Q8
1
LEN
Q
D
Rev.: A Amendment: /0
Issue Date: March 2000
Micrel
ClockWorks™
SY89809L
TRUTH TABLE
(1)
OE
0 0 LOW HIGH
0 1 LOW HIGH
1 0 HSTL_CLK /HSTL_CLK
1 1 LVPECL_CLK /LVPECL_CLK
NOTE:
1. The OE (output enable) signal is synchronized with the low level of the
HSTL_CLK and LVPECL_CLK signal.
ABSOLUTE MAXIMUM RATINGS
CLK_SEL Q0 – Q
(1)
/Q0 – /Q
8
8
SIGNAL GROUPS
Level Direction Signal
HSTL Input HSTL_CLK, /HSTL_CLK
HSTL Output Q0 – Q8, /Q0 – /Q
LVPECL Input LVPECL_CLK, /LVPECL_CLK
LVCMOS/LVTTL Input CLK_SEL, OE
8
Symbol Rating Value Unit
V
, V
CCI
CCO
V
IN
I
OUT
T
store
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.
VCC Pin Potential to Ground Pin –0.5 to +4.0 V
Input Voltage –0.5 to V
CCI
V
DC Output Current (Output HIGH) –50 mA
Storage Temperature –65 to +150 °C
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = 0°CT
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
V
V
I
CCI
CCO
CCI
VCC Core 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 V
VCC Output 1.6 1.8 2.0 1.6 1.8 2.0 1.6 1.8 2.0 V
ICC Core — 115 140 — 115 140 — 115 140 mA
HSTL
TA = 0°CT
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
(1)
(1)
1.0 — 1.2 1.0 — 1.2 1.0 — 1.2 V
0 — 0.4 0 — 0.4 0 — 0.4 V
V
OH
V
OL
V
IH
V
IL
V
X
I
IH
I
IL
NOTE:
1. Outputs loaded with 50Ω to ground.
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage VX +0.1 — 1.6 VX +0.1 — 1.6 VX +0.1 — 1.6 V
Input LOW Voltage –0.3 — VX –0.1 –0.3 — VX –0.1 –0.3 — VX –0.1 V
Input Crossover Voltage 0.68 — 0.9 0.68 — 0.9 0.68 — 0.9 V
Input HIGH Current +20 —–350 +20 —–350 +20 —–350 µA
Input LOW Current ——–500 ——–500 ——–500 µA
= +25°CT
A
= +25°CT
A
= +70°C
A
= +70°C
A
2