MICREL SY89423V Datasheet
5V/3.3V DUAL
C
AF2A
HIGH-PERFORMANCE
PHASE LOCKED LOOP
ClockWorks™
SY89423V
FEATURES
■ 3.3V and 5V power supply options
■ 1.12GHz maximum VCO frequency
■ 30MHz to 560MHz reference input operating
frequency
■ External 2.0GHz VCO capability
■ Frequency doubler mode
■ Low jitter differential design
■ PECL differential outputs
■ External loop filter optimizes performance/cost
■ Available in 44-pin PLCC package
APPLICATIONS
■ Workstations
■ Advanced communications
■ High-performance computing
PIN CONFIGURATION
NC
VCCOA
FOUTA
FOUTA
VCC
N
HFOUTA
HFOUTA
S1A
S2A
F1
S3A
S5B
HFINA
HFINA
VCCNCFOUTB
65432 44143 42 41 40
7
8
9
10
11
12
13
14
15
16
17
18
19 20 21 22 24 25 26 27 2823
TOP VIEW
PLCC
J44-1
FOUTB
VCCOB
NC
NC
39
HFOUTB
38
HFOUTB
37
36
S1B
35
S2B
F1B
34
F2B
33
32
S3B
31
S4B
30
HFINB
HFINB
29
DESCRIPTION
The SY89423V device consists of two identical, low
jitter, digital Phase Locked Loops based on Micrel-Synergy's
differential PLL technology. Each PLL is capable of
operating in the 30MHz to 560MHz reference input
frequency range, and is independent of the other, and is
configurable separately. The PLLs can be configured to be
matched in all regards, or can be configured so that PLLB
is used as a frequency doubler, while PLLA is used to
regenerate the undoubled frequency. Each PLL is capable
of operating up to 2000MHz with the HFIN input and an
external VCO.
Two reference inputs (RINX and RINX), two feedback
inputs (FINX and FINX), two high frequency inputs (HFINX
and HFINX), two filter pins (F1X and F2X), two normal
outputs (FOUTX and FOUTX), and two high frequency
outputs (HFOUTX and HFOUTX) are provided for each of
the two PLLs. The reference, feedback, and high frequency
inputs can be used as either differential or single-ended
inputs. External reference voltage generators are required
for single-ended drive.
Feedback for the loops is realized by connecting FOUTX,
FOUTX to FINX, FINX by means of external circuitry. This
allows the user the flexibility of inserting additional circuitry
off-chip in the feedback paths, such as an additional
divider. Pulldown resistors are required for the FOUTX and
FOUTX pins, and for the HFOUTX and HFOUTX pins.
Use of a phase-frequency detector in each PLL results
in excellent locking and tracking characteristics. Error
correction voltages are generated by the detector if either
phase or frequency deviations occur. The VCO in each PLL
has a frequency range covering more than a 2:1 ratio from
480MHz to 1120MHz.
Select pins S1A, S2A, S1B, S2B, and S3B are used to
program the N dividers for optimum VCO operation, in
other words with the VCO operating in the center of its
range. When both S3B and S5B are low, PLLB is identical
to PLLA. When S5B is high, the 2X frequency multiplication
option is enabled. Select pins S3A and S4B enable the HF
inputs for PLLA and PLLB respectively, which allows the
use of an external VCO in either PLL. All the select pins are
TTL inputs.
FINA
FINA
RINA
RINA
VEE
RINB
RINB
FINB
FINB
Rev.: G Amendment: /0
1
Issue Date: May 2000
NC
VEE
Micrel
A
B
B
BLOCK DIAGRAM
ClockWorks™
SY89423V
RINA
RIN
FINA
FINA
D
PHASE-FREQUENCY
DETECTOR
D
S1A
S2A
S1B
S2B
S3B
(1, 2, 4, 8, 10, 12, 16, 20)
F1A F2A
LOOP
FILTER
÷ N
A
(2, 4, 8, 16)
÷ N
B
VCO
÷ 2
S3A
1
0
HFINA
HFINA
M
U
X
HFOUTA
HFOUTA
FOUTA
FOUTA
FOUTB
FOUTB
RIN
RIN
FINB
FINB
D
PHASE-FREQUENCY
DETECTOR
÷ P
(1, 2)
S5B
LOOP
FILTER
F1B F2B
LOOP FILTER COMPONENT SELECTION
R
C
S4B
VCO
0
M
U
X
1
÷ 2
C = 1.0µF ±10% (X7R dielectric)
R = 560Ω ±10%
HFOUTB
HFOUTB
HFINB
HFINB
F1X F2X
2
Micrel
PIN NAMES PIN DESCRIPTION
ClockWorks™
SY89423V
Pin Function I/O
F1A Filter Pin 1A I/O
F2A Filter Pin 2A I/O
RINA Inverted Reference Input A I
RINA Reference Input A I
FINA Feedback Input A I
FINA Inverted Feedback Input A I
HFINA High Frequency Input A I
HFINA Inverted High Frequency Input A I
FOUTA Frequency Output A O
FOUTA Inverted Frequency Output A O
HFOUTA High Frequency Output A O
HFOUTA Inverted High Frequency Output A O
F1B Filter Pin 1B I/O
F2B Filter Pin 2B I/O
RINB Reference Input B I
RINB Inverted Reference Input B I
FINB Feedback Input B I
FINB Inverted Feedback Input B I
HFINB High Frequency Input B I
HFINB Inverted High Frequency Input B I
FOUTB Frequency Output B O
FOUTB Inverted Frequency Output B O
HFOUTB High Frequency Output B O
HFOUTB Inverted Frequency Output B O
VCC VCC —
VCCOA Output VCC —
VCCOB Output VCC —
VEE VEE (0V) —
S1A Select Input 1A (TTL) I
S2A Select Input 2A (TTL) I
S3A Select Input 3A (TTL) I
S1B Select Input 1B (TTL) I
S2B Select Input 2B (TTL) I
S3B Select Input 3B (TTL) I
S4B Select Input 4B (TTL) I
S5B Select Input 5B (TTL) I
RINA, RINA, RINB, RINB
Reference frequency inputs for loop A and B. These are
differential signal pairs and may be driven differentially or
single-ended.
FINA, FINA, FINB, FINB
Feedback frequency inputs for loop A and B. These are
differential signal pairs and may be driven differentially or
single-ended.
HFINA, HFINA, HFINB, HFINB
High frequency feedback inputs. Differential drive is
recommended.
F1A, F2A, F1B, F2B
These pins are connection points for the loop filters, which are
to be provided off-chip. F1X is the high impedance side, F2X
is the reference side. The loop filter should be a first order, low
pass with a DC block. The difference voltage on these pins will
be a DC level, which is controlled by the loop feedback and
determined by the required VCO frequency.
FOUTA, FOUTA, FOUTB, FOUTB
Frequency outputs for the loops. These are differential, positive
referenced, emitter-follower signals and must be terminated
off-chip. Termination in 50 ohms is recommended.
HFOUTA, HFOUTA, HFOUTB, HFOUTB
High frequency outputs. These are differential, positive
referenced, emitter-follower signals and must be terminated
off-chip. Termination in 50 ohms is recommended.
S1A, S2A, S3A, S1B, S2B, S3B, S4B, S5B
These inputs are used to select the configuration for PLLA and
PLLB. See the Frequency Selection Table for details of the
logic.
VCC
This is the positive supply for the chip. It should be decoupled
and present a low impedance in order to assure low-jitter
operation.
VCCOA, VCCOB
These are the positive supplies for the output buffers. They are
constrained to be equal to or less than the value of VCC.
VEE
This pin is the negative supply for the chip and is normally
connected to ground (0V).
3
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