MICREL SY604 Datasheet

125MHz TRIGGER

B

0

2

3D4

5D6

PROGRAMMABLE TIMING
EDGE VERNIER

SY604

FEATURES

■ True 125MHz retrigger rate

■ Pin-compatible with Bt604

■ 15ps delay resolution

■ Less than

± 1 LSB timing accuracy

■ Differential TRIGGER inputs

■ Delay spans from 4 to 40ns

■ Compatible with 10KH ECL logic

■ Lower power dissipation 350mW typical

■ Available in 28-pin plastic (PLCC) or metal (MLCC)

J-lead package

BLOCK DIAGRAM

D0 - D7

LAT

88

H

DAC

I/V

DESCRIPTION

Micrel-Synergy's SY604 is an ECL-compatible timing vernier
(delay generator) whose time delay is programmed via an 8­bit code which is loaded concurrently with the circuit trigger.
The SY604 is fabricated in Micrel-Synergy's proprietary
ASSET™ bipolar process.

This device can be retriggered at speeds up to 125MHz,
with a delay span as short as 4ns. At minimum span, the
resolution is 4ns/255 = 15.7ps per step. The delay span is
externally adjustable up to 40ns. The SY604 employs
differential TRIGGER inputs, and produces a differential
OUTPUT pulse; all other control signals are single-ended
ECL. Edge delay is specified by an 8-bit input which is loaded
into the device with the TRIGGER. The output pulse width will
typically be 3.5ns.

The SY604 is commonly used in Automatic Test Equipment
to provide precise timing edge placement; it is also found in
many instrumentation and communications applications.

Micrel-Synergy's circuit design techniques coupled with
ASSET™ technology result in not only ultra-fast performance,
but allow device operation at lower power dissipation than
competing technologies. Outstanding reliability is achieved in
volume production.

V

B

CE

TRIG

+

PULSE

–

D

0 = STOP

FF

1 = RUN

R

GEN

LINEAR

RAMP

GENERATOR

OUT

IEXT

PIN CONFIGURATION

CC

CC

V

OUT

V

25 24 23 21 20 1922

26

D

27

D

1

28

D

1

D

2

D

3
4

TOP VIEW

PLCC

J28-1

5678910 11

7

D

EE1

EE1

V

V

OUT

TRIG

CC

V

TRIG

CC

V

NC

EE0VEE0

V

18

NC

17
16
15
14
13
12

COMP
CE
COMP

NC
V

BB

IEXT

2

1

Rev.: E Amendment: /0

1

Issue Date: May, 1998

Micrel

PIN DESCRIPTION

SY604

D0 – D7

Data input pins (ECL compatible). On the rising edge of TRIG,
a ramp is initiated whereupon D0-D7 are latched into the
device. D0 is the LSB. These inputs specify the amount of
delay from the rising edge of TRIG to the output pulse.

CE

Chip enable input (ECL compatible). CE must be a logical
zero on the rising edge of TRIG to enable the device to
respond to the trigger. If CE is floating, the trigger will always
be enabled.

TRIG, TRIG

Differential trigger inputs (ECL compatible). The rising edge
of TRIG is used to trigger the delay cycle if CE is a logical zero.
If CE is a logical one, no operation occurs. It is recommended
that triggering be performed with differential inputs.

OUT, OUT

Differential outputs (ECL compatible).

IEXT

Current reference pin. The amount of current sourced into this
pin determines the span of output delay. The voltage at IEXT
is typically –1.25V.

COMP1, COMP2

Compensation pins. A 0.1µF ceramic capacitor must be
connected between COMP1 and VEE0, and COMP2 and VEE0
(see Figure 3).

VEE

Device power. All VEE pins must be connected.

V

CC

Device ground. All VCC pins must be connected together.

VBB

A –1.36V (typical) output.

FUNCTIONAL DESCRIPTION

The output pulse generation cycle begins with the arrival of
TRIG shown in Figure 1. When TRIG transitions to a high and
CE is low, the values on D0 - D7 are latched, thereby setting
the DAC values. Simultaneously with the latching of D0 - D7,
the linear ramp generator is enabled.

D0 - D7

CE

TRIG

OUT

When the ramp level reaches that of the DAC, the
comparator initiates the pulse generator to produce an output
pulse of fixed width. The generation of an output pulse resets
the ramp and the cycle is ready to begin again.

DATA

Figure 1.

2

Micrel

SY604

ABSOLUTE MAXIMUM RATING

(1)

Symbol Parameter Value Unit

VEE Power Supply (VCC = 0V) -8 to 0 V
VI Input Voltage (VCC = 0V) 0 to VEE V

OUT Output Current mA

I

— Continuous 50
— Surge 100

TA Operating Temperature Range 0 to +85 ˚C

(1)

(2)

-5.7 to -4.2 V

EE Operating Range

V

NOTES:

1. Beyond which device life may be impaired.

2. Parametric values specified at 10E Series: - 4.75V to - 5.5V.

DC CHARACTERISTICS

TA = +0˚C TA = +25˚C TA = +70˚C

Symbol Parameter Min. Typ. Max. MIn. Typ. Max. Min. Typ. Max. Unit

VIH Input HIGH Voltage (10K) -1170 — -840 -1130 — -810 -1070 — -735 mV
VIL Input LOW Voltage (10K) -1950 — -1480 -1950 — -1480 -1950 — -1450 mV
VOH Output HIGH Voltage (10K) -1020 -975 -840 -980 -920 -810 -920 -850 -735 mV
VOL Output LOW Voltage (10K) -1950 -1755 -1630 -1950 -1750 -1630 -1950 -1720 -1600 mV
I

IH Input High Current (Vin = VIH max) — 100 150 — 100 150 — 100 150 µA

IIH TRIG, TRIG — 100 150 — 100 150 — 100 150 µA

IL Input Low Current (Vin = VIL min) — 100 150 — 100 150 — 100 150 µA

I
IIL TRIG, TRIG — 100 150 — 100 150 — 100 150 µA

Output Delay Spans

L Differential Linearity Error** — ±0.84 ±0.9 — ±0.84 ±0.9 — ±0.84 ±0.9 LSB

D
IL Integral Linearity Error** — ±1.16 ±1.25 — ±0.89 ±1.0 — ±0.89 ±1.0

VBB VBB Output Voltage -1.44 — -1.25 -1.44 -1.35 -1.25 -1.44 — -1.25 V

EXT IEXT for Tspans

I

Tspan = 4ns 1.80 2.38 2.80 1.80 2.38 2.80 1.80 2.38 2.80 mA
Tspan = 5ns 1.45 1.85 2.40 1.45 1.85 2.40 1.45 1.85 2.40 mA
Tspan = 10ns 0.70 0.93 1.20 0.70 0.93 1.20 0.70 0.93 1.20 mA
Tspan = 15ns 0.45 0.62 0.80 0.45 0.62 0.80 0.45 0.62 0.80 mA
Tspan = 20ns 0.34 0.46 0.60 0.34 0.46 0.60 0.34 0.46 0.60 mA
Tspan = 30ns 0.20 0.30 0.40 0.20 0.30 0.40 0.20 0.30 0.40 mA

Tspan with I

EXT = 1.8 mA

(Tspan = Tmax - Tmin) 4.1 — 6.5 4.1 — 6.5 4.1 — 6.5 ns

Tmin Minimum Delay Time*

Data = 00, Tspan = 5ns — 2.8 3.8 — 2.8 3.8 — 2.8 3.8 ns
Tspan = 10ns — 3.4 4.9 — 3.4 4.9 — 3.4 4.9 ns
Tspan = 15ns — 4.0 6.0 — 4.0 6.0 — 4.0 6.0 ns
Tspan = 20ns — 4.6 7.1 — 4.6 7.1 — 4.6 7.1 ns
Tspan = 25ns — 5.2 8.2 — 5.2 8.2 — 5.2 8.2 ns
Tspan = 30ns — 5.8 9.3 — 5.8 9.3 — 5.8 9.3 ns

EE VEE Supply Current ——100 — 70 100 ——100 mA

I

NOTE:

1. 10K series circuits are designed to meet the DC specifications shown in the table after thermal equilibrium has been established. The circuit is in a test
socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50Ω resistor
to -2.0 volts.

3