MICREL SY10H841, SY100H841 Datasheet
SINGLE SUPPLY QUAD
PECL-TO-TTL W/LATCHED
OUTPUT ENABLE
ClockWorks™
SY10H841
SY100H841
FEATURES
■ Translates positive ECL to TTL (PECL-to-TTL)
■ 300ps pin-to-pin skew
■ 500ps part-to-part skew
■ Differential internal design for increased noise
immunity and stable threshold inputs
■ V
BB reference output
■ Single supply
■ Enable input
■ Latch enable input
■ Extra TTL and ECL power/ground pins to reduce
cross-talk/noise
■ High drive capability: 24mA each output
■ Fully compatible with industry standard 10K, 100K
I/O levels
■ Available in 16-pin SOIC package
BLOCK DIAGRAM
DESCRIPTION
The SY10/100H841 are single supply, low skew
translating 1:4 clock drivers.
The devices feature a 24mA TTL output stage, with
AC performance specified into a 50pF load capacitance.
A latch is provided on-chip. When LEN is LOW (or left
open, in which case it is pulled low by the internal pulldowns) the latch is transparent. A HIGH on the enable
pin (EN) forces all outputs LOW.
As frequencies increase to 40MHz and above, precise
timing and shaping of clock signals becomes extremely
important. The H841 solves several clock distribution
problems such as minimizing skew (300ps), maximizing
clock fanout (24mA drive), and precise duty cycle control
through a proprietary differential internal design.
The 10K version is compatible with 10KH ECL logic
levels. The 100K version is compatible with 100K levels.
PIN CONFIGURATION
Q
0
Q
1
Q
V
BB
D
D
DQ
2
Q
3
PIN NAMES
LEN
V
116
2
EN
314
E
G
4
E
V
D
D
BB
T
G
SOIC
Z16-1
512
6
710
8
15
13
11
Q
3
T
G
Q
2
V
T
T
V
1
Q
G
T
9
Q
0
LEN
Pin Function
EN
GT TTL Ground (0V)
VT TTL VCC (+5.0V)
VE ECL VCC (+5.0V)
GE ECL Ground (0V)
D, D Signal Input (PECL)
VBB VBB Reference Output (PECL)
Q0 - Q3 Signal Outputs (TTL)
EN Enable Input (PECL)
LEN Latch Enable Input
Rev.: F Amendment: /0
1
Issue Date: May, 1999
Micrel
ClockWorks™
SY10H841
SY100H841
TRUTH TABLE
D LEN EN Q
LLLL
HLLH
XXHL
X H L Latch
ABSOLUTE MAXIMUM RATINGS
Symbol Rating Value Unit
E (ECL) Power Supply –0.5 to +7.0 V
V
VT (TTL) Voltage –0.5 to +7.0
V
I (ECL) Input Voltage 0.0 to VEE V
VOUT (TTL) 0.0 to VT
Tstore Storage Temperature –65 to +150 ˚C
TA Operating Temperature 0 to +85 ˚C
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections
of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions
for extended periods may affect device reliability.
(1)
PIN DESCRIPTION
Pin Symbol Description
1 LEN Latch Enable Input
2 EN Enable Input (PECL)
3GE ECL Ground (0V)
4VE ECL VCC (+5.0V)
5 D ECL Signal Input (Non-inverting)
6 D ECL Signal Input (Inverting)
7VBB VBB Reference Output (PECL)
8GT TTL Ground (0V)
9Q0 Signal Output (TTL)
10 GT TTL Ground (0V)
11 Q1 Signal Output (TTL)
12 VT TTL VCC (+5.0V)
13 VT TTL VCC (+5.0V)
14 Q2 Signal Output (TTL)
15 GT TTL Ground (0V)
16 Q
3 Signal Output (TTL)
VCC AND CLOAD
Ranges to meet duty cycle requirement: 0°C ≤ TA ≤ 85°C. Output duty cycle measured relative to 1.5V.
Symbol Parameter Min. Typ. Max. Unit Condition
W Ranges of VCC and CL to meet min. VCC 4.75 5.0 5.25 V All Outputs
P
pulse width (HIGH or LOW) at CL 10 — 50 pF
fOUT ≤ 40MHz PW 11 — — ns
W Ranges of VCC and CL to meet min. VCC 4.875 5.0 5.125 V All Outputs
P
pulse width (HIGH or LOW) at CL 15 — 27 pF
fOUT ≤ 50MHz PW 9.0 — — ns
DC CHARACTERISTICS
VT = VE = 5.0V ± 5%
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
IEE Power Supply Current ECL — 40 — 40 — 40 mA VE Pin
CCH Power Supply Current TTL — 20 — 20 — 20 mA Total all VT pins
I
I
CCL —25—25—25
2
Loading...