MICREL SY10E446, SY100E446 Datasheet
4-BIT PARALLEL-TO-SERIAL
CONVERTER
SY10E446
SY100E446
FEATURES
■ On-chip clock ÷4 and ÷8
■ Extended 100E V
EE range of –4.2V to –5.5V
■ 1.6Gb/s typical data rate capability
■ Differential clock and serial inputs
■ VBB output for single-ended use
■ Asynchronous data synchronization
■ Mode select to expand to 8 bits
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E446
■ Available in 28-pin PLCC package
PIN CONFIGURATION
1
3
2
0
D
D
D
TOP VIEW
PLCC
J28-1
MODE
NC
NC
18
NC
17
NC
16
V
CC
15
SOUT
14
SOUT
13
V
CCO
12
NC
CLK
CLK
V
BB
V
EE
SIN
SIN
SYNC
D
25
24 23 22 21 20 19
26
27
28
1
2
3
4
567891011
DESCRIPTION
The SY10/100E446 are integrated 4-bit parallel-toserial data converters. These devices are designed to
operate for NRZ data rates of up to a minimum of 1.3Gb/
s. The chips generate a divide-by-4 and a divide-by-8
clock for both 4-bit conversion and a two-chip 8-bit
conversion function. The conversion sequence was
chosen to convert the parallel data into a serial stream
from bit D
two E446 devices for 8-bit conversion applications.
The SYNC input will asynchronously reset the internal
clock circuitry. This pin allows the user to reset the internal
clock conversion unit and, thus, select the start of the
conversion process.
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the internal load clock will change
on every eighth clock cycle, thus allowing for an 8-bit
conversion scheme using two E446s. When cascaded in
an 8-bit conversion scheme, the devices will not operate
at the 1.3Gb/s data rate of a single device. Refer to the
applications section of this data sheet for more information
on cascading the E446.
For lower data rate applications, a VBB reference
voltage is supplied for single-ended inputs. When
operating at clock rates above 500MHz, differential input
signals are recommended. For single-ended inputs, the
VBB pin is tied to the inverting differential input and
bypassed via a 0.01µF capacitor. The VBB provides the
switching reference for the input differential amplifier. The
VBB can also be used to AC couple an input signal.
0 to D3. A serial input is provided to cascade
CCO
V
CL/8
CL/8
CCO
V
CL/4
CL/4
CCO
V
PIN NAMES
Pin Function
SIN, SIN Differential Serial Data Input
D0 – D3 Parallel Data Input
SOUT, SOUT Differential Serial Data Output
CLK, CLK Differential Clock Input
CL/4, CL/4 Differential 4 Clock Output
CL/8, CL/8 Differential 8 Clock Output
MODE Conversion Mode, 4-bit/8-bit
SYNC Conversion Synchronizing Input
CCO VCC to Output
V
Rev.: C Amendment: /1
1
Issue Date: February, 1998
Micrel
BLOCK DIAGRAM
SY10E446
SY100E446
SIN
SIN
D3
D2
D1
0
DQ
1
CLK
0
DQ
1
CLK
0
DQ
1
CLK
D0
MODE
CLK
CLK
SYNC
VBB
DELAY
0
DQ
1
CLK
01
÷4
R
÷8
R
SOUT
SOUT
CL/8
CL/8
CL/4
CL/4
2
SY10E446
Micrel
SY100E446
TRUTH TABLE
Mode Conversion
L 4-Bit
H 8-Bit
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current ——150 ——150 ——150 µA —
OH Output HIGH Voltage V1
V
(SOUT Only) 10E –1020 —–790 –980 —–760 –910 —–670
(SOUT Only) 100E –1025 —–830 –1025 —–830 –1025 —–830
BB Output Reference Voltage V —
V
10E –1.38 —–1.27 –1.35 —–1.25 –1.31 —–1.19
100E –1.38 —–1.26 –1.38 —–1.26 –1.38 —–1.26
EE Power Supply Current mA —
I
10E — 110 132 — 110 132 — 110 132
100E — 110 132 — 110 132 — 127 152
NOTE:
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E
and 100E VOH levels.
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
A = 0°CTA = +25°CTA = +85°C
T
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
MAX Max. Conversion Frequency 1.3 1.6 — 1.3 1.6 — 1.3 1.6 — Gb/s —
f
NRZ
t
PLH Propagation Delay to Output ps —
tPHL CLK to SOUT 1000 1400 1700 1000 1400 1700 1000 1400 1700
CLK to CL/4 500 800 1100 500 800 1100 500 800 1100
CLK to CL/8 800 1100 1400 800 1100 1400 800 1100 1400
SYNC to CL/4, CL/8 500 800 1100 500 800 1100 500 800 1100
S Set-up Time ps —
t
SIN –200 –400 —–200 –400 —–200 –400 —
Dn –200 –400 —–200 –400 —–200 –400 —
Mode 0 –250 — 0 –250 — 0 –250 —
H Hold Time ps —
t
SIN 750 550 — 750 550 — 750 550 —
Dn 800 600 — 800 600 — 800 600 —
Mode 500 300 — 500 300 — 500 300 —
tRR Reset Recovery Time 500 200 — 500 200 — 500 200 — ps —
PW Minimum Pulse Width 400 ——400 ——400 ——ps —
t
CLK, MR
r Rise/Fall Time ps 20–80%
t
tf SOUT 100 225 350 100 225 350 100 225 350
Other 200 425 650 200 425 650 200 425 650
3
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