MICREL SY10E445, SY100E445 Datasheet
4-BIT SERIAL-to-PARALLEL
CONVERTER
SY10E445
SY100E445
FEATURES
■ On-chip clock ÷4 and ÷8
■ Extended 100E VEE range of –4.2V to –5.5V
■ 2.5Gb/s data rate capability
■ Differential clock and serial inputs
■ VBB output for single-ended use
■ Asynchronous data synchronization
■ Mode select to expand to 8 bits
■ Internal 75kΩ input pull-down resistors
■ Fully compatible with Motorola MC10E/100E445
■ Available in 28-pin PLCC package
PIN CONFIGURATION
SINB
SINB
SEL
VEE
CLK
CLK
VBB
INA
S
25
24 23 22 21 20 19
26
27
28
1
2
3
4
567891011
CL/8
RESET
SYNC
SINA
TOP VIEW
PLCC
J28-1
CCO
CL/8
CL/4
V
MODE
NC
CCO
CL/4
V
VCCO
Q3
18
SOUT
17
SOUT
16
VCC
15
Q0
14
Q1
13
VCCO
12
Q2
PIN NAMES
Pin Function
SINA, SINA Differential Serial Data Input A
SINB, SINB Differential Serial Data Input B
SEL Serial Input Select Pin
SOUT, SOUT Differential Serial Data Output
Q0–Q3 Parallel Data Outputs
CLK, CLK Differential Clock Inputs
CL/4, CL/4 Differential ÷4 Clock Output
CL/8, CL/8 Differential ÷8 Clock Output
MODE Conversion Mode 4-bit/8-bit
SYNC Conversion Synchronizing Input
RESET Input, Resets the Counters
CCO VCC to Output
V
DESCRIPTION
The SY10/100E445 are integrated 4-bit serial-to-parallel
data converters. The devices are designed to operate for
NRZ data rates of up to 2.5Gb/s. The chip generates a
divide-by-4 and a divide-by-8 clock for both 4-bit conversion
and a two-chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q
the second to Q1, etc.
Two selectable serial inputs provide a loopback capability
for testing purposes when the device is used in conjunction
with the E446 parallel-to-serial converter.
The start bit for conversion can be moved using the
SYNC input. A single pulse, applied asynchronously for at
least two input clock cycles, shifts the start bit for conversion
from Qn to Qn-1 by one bit. For each additional shift required,
an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers
to "swallow" a clock pulse, effectively shifting a bit from the
Qn to the Qn-1 output (see Timing Diagram B).
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change on
every eighth clock cycle, thus allowing for an 8-bit conversion
scheme using two E445s. When cascaded in an 8-bit
conversion scheme, the devices will not operate at the
2.5Gb/s data rate of a single device. Refer to the applications
section of this data sheet for more information on cascading
the E445.
For lower data rate applications, a VBB reference voltage
is supplied for single-ended inputs. When operating at clock
rates above 500MHz, differential input signals are
recommended. For single-ended inputs, the VBB pin is tied
to the inverting differential input and bypassed via a 0.01µF
capacitor. The VBB provides the switching reference for the
input differential amplifier. The VBB can also be used to AC
couple an input signal.
0,
Rev.: D Amendment: /0
1
Issue Date: October, 1998
Micrel
BLOCK DIAGRAM
SY10E445
SY100E445
SINB
SINB
SINA
SINA
SEL
CLK
CLK
0
1
DQ
D
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Q
3
Q
2
Q
1
Q
0
SOUT
SOUT
÷4
R
CL/4
CL/4
0
MODE
RESET
SYNC
VBB
R
÷2
1
CL/8
CL/8
2
Micrel
TRUTH TABLES
LOGIC DIAGRAM
SY10E445
SY100E445
Mode Conversion
L 4-Bit
H 8-Bit
DC CHARACTERISTICS
LOGIC DIAGRAM
SEL Serial Input
HA
LB
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current ——150 ——150 ——150 µA —
OH Output HIGH Voltage V
V
(SOUT only) 10E –1020 —–790 –980 —–760 –910 —–670 1
(SOUT only) 100E –1025 —–830 –1025 —–830 –1025 —–830 1
V
BB Output Reference Voltage V
10E –1.38 —–1.27 –1.35 —–1.25 –1.31 —–1.19
100E –1.38 —–1.26 –1.38 —–1.26 –1.38 —–1.26
EE Power Supply Current mA —
I
10E — 154 185 — 154 185 — 154 185
100E — 154 185 — 154 185 — 177 212
NOTE:
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E
and 100E VOH levels.
AC CHARACTERISTICS
LOGIC DIAGRAM
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
MAX Max. Conversion Frequency 2.0 ——2.0 ——2.0 ——Gb/s 1
f
2.5 ——2.5 ——2.5 ——NRZ 2
PLH Propagation Delay to Output ps —
t
tPHL CLK to Q 1500 1800 2100 1500 1800 2100 1500 1800 2100
CLK to SOUT 800 975 1150 800 975 1150 800 975 1150
CLK to CL/4 1100 1325 1550 1100 1325 1550 1100 1325 1550
CLK to CL/8 1100 1325 1550 1100 1325 1550 1100 1325 1550
S Set-up Time ps —
t
SINA, SINB –100 –250 —–100 –250 —–100 –250 —
SEL 0 –200 — 0 –200 — 0 –200 —
tH Hold Time, SINA, SINB, SEL 450 300 — 450 300 — 450 300 — ps —
tRR Reset Recovery Time 500 300 — 500 300 — 500 300 — ps —
t
PW Minimum Pulse Width 400 ——400 ——400 ——ps —
CLK, MR
r Rise/Fall Times ps —
t
tf 20% to 80%
SOUT 100 225 350 100 225 350 100 225 350
Other 200 425 650 200 425 650 200 425 550
NOTES:
1. Guaranteed for input clock amplitudes of 150mV to 800mV.
2. Guaranteed for input clock amplitudes of 150mV to 400mV.
3
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