MICREL SY10E137, SY100E137 Datasheet
8-BIT RIPPLE
K
COUNTER
SY10E137
SY100E137
FEATURES
■ 1.8GHz min. count frequency
■ Extended 100E V
EE range of –4.2V to –5.5V
■ Synchronous and asynchronous enable pins
■ Differential clock input and data output pins
■ VBB output for single-ended use
■ Asynchronous Master Reset
■ Internal 75KΩ input pull-down resistors
■ Available in 28-pin PLCC packge
PIN CONFIGURATION
A_Start
EN
EN
V
EE
CL
CLK
V
BB
7
Q
25 24 23 22 21 20 19
26
1
27
2
28
1
2
3
4
567891011
MR
Q
Q
PLCC
TOP VIEW
J28-1
0
Q
CCO
V
Q
0
Q
6
6
7
CCO
V
1
Q
5
5
Q
Q
18
Q
17
Q
16
V
15
Q
Q
14
Q
13
12
Q
1
Q
CCO
V
PIN NAMES
Pin Function
CLK, CLK Differential Clock Inputs
Q0–Q7, Q0–Q7 Differential Q Outputs
A_Start Asynchronous Enable Input
EN1, EN2 Synchronous Enable Inputs
MR Asynchronous Master Reset
VBB Switching Reference Output
CCO VCC to Output
V
4
4
CC
3
3
2
2
DESCRIPTION
The SY10/100E137 are very high speed binary ripple
counters. The two least significant bits were designed
with very fast edge rates, while the more significant bits
maintain standard ECLinPS output edge rates. This allows
the counters to operate at very high frequencies, while
maintaining a moderate power dissipation level.
The devices are ideally suited for multiple frequency
clock generation, as well as for counters in highperformance ATE time measurement boards.
Both asynchronous and synchronous enables are
available to maximize the device's flexibility for various
applications. The asynchronous enable input, A_Start,
when asserted, enables the counter while overriding any
synchronous enable signals. The E137 features XOR'ed
enable inputs, EN
the CLK input. When only one synchronous enable is
asserted, the counter becomes disabled on the next CLK
transition. All outputs remain in the previous state poised
for the other synchronous enable or A_Start to be
asserted in order to re-enable the counter. Asserting
both synchronous enables causes the counter to become
enabled on the next transition of the CLK. EN1 (or EN2)
and CLK edges are coincident. Sufficient delay has been
inserted in the CLK path (to compensate for the XOR
gate delay and the internal D-flip-flop set-up time) to
ensure that the synchronous enable signal is clocked
correctly; hence, the counter is disabled.
The E137 can also be driven single-endedly utilizing
the VBB output supply as the voltage reference for the
CLK input signal. If a single-ended signal is to be used,
the VBB pin should be connected to the CLK input and
bypassed to ground via a 0.01µF capacitor. VBB can
only source/sink 0.5mA; therefore, it should be used as
a switching reference for the E137 only.
All input pins left open will be pulled LOW via an input
pull-down resistor. Therefore, do not leave the differential
CLK inputs open. Doing so causes the current source
transistor of the input clock gate to become saturated,
thus upsetting the internal bias regulators and
jeopardizing the stability of the device.
The asynchronous Master Reset resets the counter to
an all zero state upon assertion.
1 and EN2, which are synchronous to
Rev.: C Amendment: /1
1
Issue Date: February, 1998
Micrel
BLOCK DIAGRAM
A_Start
EN1
EN2
CLK
CLK
MR
VBB
D
CLK
CLK
SY10E137
SY100E137
R
Q
Q
CLK
CLK
D
D
Q0Q
0
Q
Q
R
CLK
CLK
D
Q1Q
1
Q
Q
R
CLK
CLK
D
Q6Q
6
Q
Q
R
CLK
CLK
D
Q7Q
7
Q
Q
R
SEQUENTIAL TRUTH TABLE
(1)
Function EN1 EN2 A_Start MR CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Reset X X X H X LLLLLLLL
Count LLLLZLLLLLLLH
LLLLZLLLLLLHL
LLLLZLLLLLLHH
Stop H L L L Z LLLLLLHH
HLLLZLLLLLLHH
Async. Start H L H L Z LLLLLHLL
HLHLZLLLLLHLH
LLHLZLLLLLHHL
Count LLLLZLLLLLHHH
LLLLZLLLLHLLL
LLLLZLLLLHLLH
Stop L H L L Z LLLLHLLH
LHLLZLLLLHLLH
Sync. Start H H L L Z LLLLHLHL
HHLLZLLLLHLHH
HHLLZLLLLHHLL
Stop H L L L Z LLLLHHLL
HLLLZLLLLHHLL
Count LLLLZLLLLHHLH
LLLLZLLLLHHHL
LLLLZLLLLHHHH
Reset X X X H X LLLLLLLL
NOTE:
1. Z = LOW-to-HIGH transition
2
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