MICREL SY10E104, SY100E104 Datasheet
QUINT 2-INPUT
AND/NAND GATE
SY10E104
SY100E104
FEATURES
■ 600ps max. propagation delay
■ Extended 100E VEE range of –4.2V to –5.5V
■ True and complementary outputs
■ OR/NOR function outputs
■ Fully compatible with Industry standard 10KH,
100K I/O levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E104
■ Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0a
D
0b
D
1a
D
1b
D
2a
D
2b
D
3a
DESCRIPTION
The SY10/100E104 are quint 2-input AND/NAND gates
designed for use in new, high-performance ECL systems.
The E104 also features a function output, F, which is the
OR of all five AND gate outputs, while F is the NOR. Both
true and complementary outputs are provided.
PIN CONFIGURATION
F
3a
4a
3b
D
D
F
25 24 23 22 21 20 19
D
3b
2a
2b
EE
1a
0a
26
27
28
1
2
1b
3
4
TOP VIEW
567891011
0b
D
CCO
V
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
D
D
V
D
D
D
NC
D
PLCC
J28-1
0
Q
CCO
F
F
V
18
Q
4
17
Q
4
16
V
CC
15
Q
3
14
Q
3
13
Q
2
12
Q
2
1
1
0
Q
Q
Q
CCO
V
D
3b
D
4a
D
4b
Q
3
Q
4
Q
4
PIN NAMES
Pin Function
Dna, Dnb Data Inputs
Q0-Q4 AND Outputs
Q0-Q4 NAND Outputs
F OR Output
F NOR Output
CCO VCC to Output
V
Rev.: E Amendment: /0
1
Issue Date: November, 1998
SY10E104
Micrel
SY100E104
LOGIC EQUATION
F = (D0a • D0b) + (D1a • D1b) + (D2a • D2b) + (D3a • D3b) + (D4a • D4b)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
IIH Input HIGH Current — — 200 — — 200 — — 200 — — 200 µA
EE Power Supply Current mA
I
10E — 38 46 — 38 46 — 38 46 — 38 46
100E — 38 46 — 38 46 — 38 46 — 44 53
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
PLH Propagation Delay to ps
t
tPHL Output D to Q 225 385 600 225 385 600 225 385 600 225 385 600
D to F 500 725 1000 500 725 1000 500 725 1000 500 725 1000
t
skew Within-Device Skew,
r Rise/Fall Time ps
t
tf 20% to 80% Q 275 425 700 275 425 700 275 425 700 275 425 700
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
D to Q
(1)
—75——75 ——75——75 —ps
F 300 475 700 300 475 700 300 475 700 300 475 700
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E104JC J28-1 Commercial
SY10E104JCTR J28-1 Commercial
SY100E104JC J28-1 Commercial
SY100E104JCTR J28-1 Commercial
Ordering Package Operating
Code Type Range
SY10E104JI J28-1 Industrial
SY10E104JITR J28-1 Industrial
SY100E104JI J28-1 Industrial
SY100E104JITR J28-1 Industrial
2
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