MICREL SY100S834, SY100S834L Datasheet
(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)
CLOCK GENERATION CHIP
ClockWorks™
SY100S834
SY100S834L
FEATURES
■ 3.3V and 5V power supply options
■ 50ps output-to-output skew
■ Synchronous enable/disable
■ Master Reset for synchronization
■ Internal 75KΩ input pull-down resistors
■ Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
1
Q
0
2
Q
0
3
V
CC
4
Q
1
5
Q
1
6
V
CC
7
Q
2
8
Q
2
Q
÷1 or ÷2
R
Q
÷2 or ÷4
R
Q
÷4 or ÷8
R
SOIC
TOP VIEW
Q
16
V
CC
15
14
13
12
11
10
EN
F
SEL
CLK
CLK
BB
V
MR
9
EE
V
D
R
PIN NAMES
Pin Function
CLK Differential Clock Inputs
FSEL Function Select
EN Synchronous Enable
MR Master Reset
VBB Reference Output
Q0 Differential ÷1 or ÷2 Outputs
Q1 Differential ÷2 or ÷4 Outputs
Q
2 Differential ÷4 or ÷8 Outputs
DESCRIPTION
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,
÷4, ÷8) clock generation chip designed explicitly for low
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
be driven by either a differential or single-ended ECL or,
if positive power supplies are used, PECL input signal.
In addition, by using the VBB output, a sinusoidal source
can be AC-coupled into the device. If a single-ended
input is to be used, the VBB output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
can only source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input
is LOW, SY100S834/L functions as a divide by 2, by 4
and by 8 clock generation chip. However, if FSEL input
is HIGH, it functions as a divide by 1, by 2 and by 4
clock generation chip. This latter feature will increase
the clock frequency by two folds.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
TRUTH TABLE
CLK EN MR Function
Z L L Divide
ZZ H L Hold Q0–2
X X H Reset Q0–2
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
FSEL Q0 Outputs Q1 Outputs Q2 Outputs
L Divide by 2 Divide by 4 Divide by 8
H Divide by 1 Divide by 2 Divide by 4
Rev.: F Amendment: /0
1
Issue Date: September, 1999
Micrel
ClockWorks™
SY100S834
SY100S834L
DC ELECTRICAL CHARACTERISTICS
(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
IEE Power Supply Current ——49 ——49 ——49 ——54 mA
VBB Output Reference Voltage -1.38 — -1.26 -1.38 — -1.26 -1.38 — -1.26 -1.38 — -1.26 V
IH Input HIGH Current ——150 ——150 ——150 ——150 µA
I
NOTE:
1. Parametric values specified at: 5 volt Power Supply Range 100S834 Series: -4.2V to -5.5V.
3 volt Power Supply Range 100S834L Series -3.0V to -3.8V.
AC ELECTRICAL CHARACTERISTICS
(1)
VEE = VEE (Min.) to VEE (Max.); VCC = GND
A = –40°CTA = 0°CTA = +25°CTA = +85°C
T
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
PLH Propagation Delay CLK 960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200 ps
t
tPHL to Output MR 650 800 1010 650 800 1010 650 800 1010 650 800 1010
tskew Within-Device Skew
tS Set-up Time EN 400 ——400 ——400 ——400 ——ps
tH Hold Time EN 200 ——200 ——200 ——200 ——ps
VPP Minimum Input Swing 250 ——250 ——250 ——250 ——mV
CMR Common Mode Range
V
r Output Rise/Fall Times 275 400 525 275 400 525 275 400 525 275 400 525 ps
t
tf Q (20% – 80%)
NOTES:
1. Parametric values specified at: 5 volt Power Supply Range 100S834 Series: -4.2V to -5.5V.
2. Within-Device Skew is specified for identical transition.
3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table
assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I.
(2)
——50 ——50 ——50 ——50 ps
(3)
CLK –1.3 —–0.4 –1.4 —–0.4 –1.4 —–0.4 –1.4 —–0.4 V
3 volt Power Supply Range 100S834L Series -3.0V to -3.8V.
2
Loading...