MICREL SY100S811 Datasheet
SINGLE SUPPLY 1:9
PECL/TTL-TO-PECL
ClockWorks™
SY100S811
FEATURES
■ PECL version of popular ECLinPS E111
■ Low skew
■ Guaranteed skew spec
■ VBB output
■ TTL enable input
■ Selectable TTL or PECL clock input
■ Single +5V supply
■ Differential internal design
■ Similar pin configuration to E111
■ PECL I/O fully compatible with industry standard
■ Internal 75KΩ PECL input pull-down resistors
■ Available in 28-pin PLCC and SOIC packages
BLOCK DIAGRAM
Q
Q
Q
E
IN
E
IN
T
IN
T
EN
V
BB
0
1
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
DESCRIPTION
The SY100S811 is a low skew 1-to-9 PECL differential
driver designed for clock distribution in new, highperformance PECL systems. It accepts either a PECL
clock input or a TTL input by using the TTL enable pin TEN.
When the TTL enable pin is HIGH, the TTL input is enabled
and the PECL input is disabled. When the enable pin is set
LOW, the TTL input is disabled and the PECL input is
enabled.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the S811 shares a common set of “basic”
processing with the other members of the ECLinPS family,
wafer characterization at the point of device personalization
allows for tighter control of parameters, including
propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
terminated into 50Ω, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
to maintain minimum skew.
The VBB output is intended for use as a reference
voltage for single-ended reception of PECL signals to that
device only. When using VBB for this purpose, it is
recommended that VBB is decoupled to VCC via a 0.01µF
capacitor.
PIN CONFIGURATION
Q0
VEE
TEN
EIN
VCC
EIN
VBB
TIN
Q1
25 24 23 22 21 20 19
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
567891011
VCCO
Q2Q0Q1
Q2
18
Q3
17
Q3
16
Q4
15
VCCO
14
Q4
13
Q5
12
Q5
VCCO
Q7
Q6
Q6
Rev.: F Amendment: /0
Issue Date: October, 1998
Q8Q8Q7
1
Micrel
B
ClockWorks™
SY100S811
PIN CONFIGURATION
1
V
CC
2
E
IN
3
V
B
4
T
IN
5
Q
8
6
Q
8
TOP VIEW
7
Q
7
8
V
CCO
9
Q
7
10
Q
6
11
Q
6
12
Q
5
13
Q
5
14
Q
4
SOIC
Z28-1
TRUTH TABLE
28
E
IN
27
T
EN
26
V
EE
25
Q
0
24
Q
0
23
Q
1
22
V
CCO
21
Q
1
20
Q
2
19
Q
2
18
Q
3
17
Q
3
16
Q
4
15
V
CCO
TEN EIN TIN Q
LLXL
LHXH
HXLL
HXHH
PIN NAMES
Pin Function
EIN, EIN Differential PECL Input Pair
TIN TTL Input
TEN TTL Input Enable
Q0, Q0 – Q8, Q8 Differential PECL Outputs
VBB VBB Output
VCC PECL VCC (+5.0V)
EE PECL Ground (0V)
V
PECL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = +5.0V ± 5%
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
(3)
(1)
(1)
(1)
3.62 — 3.74 3.62 — 3.74 3.62 — 3.74 V
3.835 — 4.120 3.835 — 4.120 3.835 — 4.120 V
3.190 — 3.525 3.190 — 3.525 3.190 — 3.525 V
(2)
VCC –1025 VCC –955 VCC –870 VCC –1025 VCC –955 VCC –870 VCC –1025 VCC –955 VCC –870 mV
(2)
VCC –1890 VCC –1705 VCC –1620 VCC –1890 VCC –1705 VCC –1620 VCC –1890 VCC –1705VCC –1620 mV
— 53 65 — 53 65 — 60 74 mA
BB Output Reference
V
Voltage
IIH Input HIGH Current ——150 ——150 ——150 µA
IIL Input LOW Current 0.5 ——0.5 ——0.5 ——µA
VIH Input HIGH Voltage
VIL Input LOW Voltage
VOH Output HIGH Voltage
VOL Output LOW Voltage
ICC Power Supply
Current
NOTES:
1. VCC = VCCO = 5.0V
2. VIN = VIH (Max.) or VIL (Min.) Loading with 50Ω to VCC –2V.
3. All inputs and outputs open.
2
Loading...