MICREL SY100S360 Datasheet

DUAL PARITY
CHECKER/
GENERATOR

FEATURES

■ Max. propagation delay of 2200ps

■ IEE min. of –70mA

■ Industry standard 100K ECL levels

■ Extended supply voltage option:

VEE = –4.2V to –5.5V

■ Voltage and temperature compensation for improved

noise immunity

■ Internal 75KΩ input pull-down resistors

■ 15% faster than Fairchild 300K

■ Approximately 30% lower power than Fairchild 300K

■ Function and pinout compatible with Fairchild F100K

■ Available in 24-pin CERPACK and 28-pin PLCC

packages

BLOCK DIAGRAM

I

0a

I

1a

I

2a

I

3a

I

4a

I

5a

I

6a

I

7a

I

a

I

0b

I

1b

I

2b

I

3b

I

4b

I

5b

I

6b

I

7b

I

b

Z

a

C

Z

b

SY100S360

DESCRIPTION

The SY100S360 is a dual parity checker/generator and
is designed for use in high-performance ECL systems. The
inputs are segmented into two groups of nine inputs each
and the parity output is at a logic LOW when an even
number of inputs are at a logic HIGH. In each group, one of
the nine inputs (Ia, Ib) has a shorter propagation delay and,
therefore, is ideal as the expansion input for parity
generation of wider data.

A Compare output (C) is also provided which allows
comparison of two 8-bit words. A logic LOW on the C output
indicates a match. The inputs on this device have 75KΩ
pull-down resistors.

PIN CONFIGURATIONS

I5a

I6a
I7a

VEE

VEES

I0b

I1b
I2b

I4a

12
13
14
15
16
17

1911201021922823724

I4b

I3b

I3a

VEES

Top View

PLCC
J28-1

I5b

VEES

I2a

I1a

I0a

5

6

Ia

4
3

Za
VCCA

2
1

VCC
V

CC

28
27

C

2618

b

Z

25

0b

Ib

I6b

I7b

I2bI1bI

VEEI7aI

6a

19

1

I

3b

2

I

4b

3

I

5b

I

6b

I

7b

I

b

Top View

Flatpack

4

F24-1

5
6

18
17
16
15
14
13

I

5a

I

4a

I

3a

I

2a

I

1a

I

0a

7248239221021112012

b

C

Z

CC

V

CCA

V

a

a

I

Z

Rev.: G Amendment: /0

1

Issue Date: July, 1999

Micrel

SY100S360

PIN NAMES

Pin Function

Ia, Ib, Ina, Inb Data Inputs (n = 1...7)
Za – Zb Parity Odd Outputs
C Compare Output
VEES VEE Substrate

CCA VCCO for ECL Outputs

V

TRUTH TABLE

Sum of Output

High Inputs Z

Even HIGH

Odd LOW

NOTE:

1. Comparator Function:

C = (I0a ⊕ I1a) + (I2a ⊕ I3a) + (I4a ⊕ I5a) + (I6a ⊕ I7a) +

(I0b ⊕ I1b) + (I2b ⊕ I3b) + (I4b ⊕ I5b) + (I6b ⊕ I7b)

(1)

DC ELECTRICAL CHARACTERISTICS

VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND

Symbol Parameter Min. Typ. Max. Unit Condition

I

IH Input HIGH Current µAVIN = VIH (Max.)

I

a, Ib ——300

Ina, Inb ——200

EE Power Supply Current –70 –45 –30 mA Inputs Open

I

AC ELECTRICAL CHARACTERISTICS

CERPACK

VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND

TA = 0°CTA = +25°CTA = +85°C

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition

t

PLH Propagation Delay 500 2300 500 2300 500 2300 ps

tPHL Ina, Inb to Za, Zb
tPLH Propagation Delay 500 1800 500 1800 500 1800 ps

tPHL Ina, Inb to C

PLH Propagation Delay 300 1000 300 1000 300 1000 ps

t
tPHL Ia, Ib to Za, Zb

tTLH Transition Time 300 900 300 900 300 900 ps
tTHL 20% to 80%, 80% to 20%

PLCC

VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND

TA = 0°CTA = +25°CTA = +85°C

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition

t

PLH Propagation Delay 500 2200 500 2200 500 2200 ps

tPHL Ina, Inb to Za, Zb
tPLH Propagation Delay 500 1700 500 1700 500 1700 ps

tPHL Ina, Inb to C

PLH Propagation Delay 300 900 300 900 300 900 ps

t
tPHL Ia, Ib to Za, Zb

tTLH Transition Time 300 900 300 900 300 900 ps
tTHL 20% to 80%, 80% to 20%

2