MICREL SY100S336 Datasheet
4-STAGE COUNTER/
R
SHIFT REGISTER
SY100S336
FEATURES
■ Max. shift frequency of 700MHz
■ Clock to Q delay max. of 1100ps
■ IEE min. of –170mA
■ Internal 75KΩ input pull-down resistors
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
■ 50% faster than Fairchild 300K at lower power
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
PIN CONFIGURATIONS
3
3
3
Top View
PLCC
J28-1
CEP
/CET
0
D
EES
D
V
6
TC
EES
V
CEP
D0/CET
Q3Q
0
Q
S2
TC
Q0
Q
25
0
5
Q
2
4
3
Q
2
V
CCA
2
1
V
CC
V
CC
28
27
Q
1
2618
0
Q
1
Q
S1
S0
M
1
2
3
Top View
Flatpack
4
5
6
F24-1
7248239221021112012
Q1
VCC
VEE
VCCA
CP
19
Q2Q1Q2
P0
18
17
16
15
14
13
P1
P2
P3
D3
Q3
Q3
P1P2P
P
0
12
CP
13
V
EE
14
V
EES
15
MR
16
17
0
S
S
1
1911201021922823724
2
S
DESCRIPTION
The SY100S336 functions either as a modulo-16 up/
down counter or as a 4-bit bidirectional shift register and is
designed for use in high-performance ECL systems. Three
Select inputs (Sn) are provided for determining the mode of
operation. The Function Table lists the available modes of
operation. In order to allow cascading for multistage
counters, two Count Enable controls (CEP, CET) are
provided. The CET input also functions as the Serial Data
input (S0) for a shift-up operation, while the D3 input serves
as the Serial Data input for the shift-down operation.
When the device is in the counting mode, the Terminal
Count (TC) goes to a logical LOW when the count reaches
15 for count-up or reaches 0 for count-down. When in the
shift mode, the TC output simply repeats the Q3 output.
The flexiblity provided by the TC/Q3 output and the D0/
CET input allows these signals to be interconnected from
one stage to the next higher stage for multistage counting
or shift-up operations. The individual Presets (Pn) allow
initialization of the counter by entering data in parallel to
preset the counter. A logic HIGH on the Master Reset (MR)
overrides all other inputs and asynchronously clears the
flip-flops. An additional synchronous Clear is provided, as
well as a complement function which synchronously inverts
the contents of the flip-flops. All inputs have 75KΩ pulldown resistors.
PIN NAMES
Pin Function
CP Clock Pulse Input
CEP Count Enable Parallel Input (Active LOW)
0/CET Serial Data Input/Count Enable Trickle
D
Input (Active LOW)
S0 — S2 Select Inputs
MR Master Reset Input
VEES VEE Substrate
VCCA VCCO for ECL Outputs
P0 – P3 Preset Inputs
D3 Serial Data Input
TC Terminal Count Output
Q0 — Q3 Data Outputs
0 — Q3 Complementary Data Outputs
Q
Rev.: G Amendment: /0
1
Issue Date: July, 1999
Micrel
BLOCK DIAGRAM
S
0
S
1
S
2
SY100S336
D3
D0/CET
CEP
CP
MR
Q
0
T
T
Q
0
R
T
C
R
Q
1
T
Q
1
R
T
TT
2
Q
T
T
2
Q
R
T
TCTC
P0 Q0 Q0 P1 Q1 Q1 P2 Q2 Q2
T
Q
3
T
T
T
R
Q
3
T
TC
P3 Q3 Q3
TC
2
Micrel
SY100S336
TRUTH TABLE
(1)
Inputs Outputs
MR S2 S1 S0 CEP D0/CET D3 CP Q0 Q1 Q2 Q3 TC Mode
LLLL X X X uP0 P1 P2 P3 L Preset (Parallel Load)
LLLH X X X uQ0 Q1 Q2 Q3 L Invert
LLHL X X X uQ1 Q2 Q3 D3 D3 Shift Left
LLHH X X X uD0 Q0 Q1 Q2 Q3* Shift Right
LHLL L L X u (Q
LHLL H L X XQ
0–3) minus 1 ① Count Down
0 Q1 Q2 Q3 ① Count Down with CEP
Not Active
LHLL X H X XQ
0 Q1 Q2 Q3 H Count Down with CET
Not Active
LHLH X X X uLLLLHClear
LHHL L L X u (Q
LHHL H L X XQ
0–3) plus 1 ≠ Count Up
0 Q1 Q2 Q3 ≠ Count Up with CEP
Not Active
LHHL X H X XQ0 Q1 Q2 Q3 H Count Up with CET
Not Active
LHHH X X X XQ0 Q1 Q2 Q3 H Hold
HLLL X X X XLLLLLAsynchronous Master
HLLHX X X XLLLLLReset
HLHL X X X XLLLLL
HLHHX X X XLLLLL
HHLL X L X XLLLLL
HHLL X H XXLLLLH
HHLHX X X XLLLLH
HHHL X X X XLLLLH
HHHH X X X XLLLLH
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
u = LOW-to-HIGH Transition
① = L if Q0 – Q3 = LLLL
H if Q0 – Q3 ≠ LLLL
≠ = L if Q0 – Q3 = HHHH
H if Q0 – Q3 ≠ HHHH
* Before the clock, TC is Q3; after the clock, TC is Q2
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol Parameter Min. Typ. Max. Unit Condition
IIH Input HIGH Current, All Inputs ——200 µAVIN = VIH (Max.)
EE Power Supply Current –170 –145 –90 mA Inputs Open
I
3
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