MICREL SY100S331 Datasheet
TRIPLE D
FLIP-FLOP
SY100S331
FEATURES
■ Max. toggle frequency of 800MHz
■ Differential outputs
■ IEE min. of –80mA
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
■ Internal 75KΩ input pull-down resistors
■ 150% faster than Fairchild
■ 40% lower power than Fairchild
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
CD
2
C
CP
CP
SD
CD
CP
SD
CD
CP
SD
C
2
D
2
2
1
1
D
1
1
0
0
D
0
0
CP
D
CP
D
CP
D
D
S
D
C
D
S
D
C
D
S
D
Q
2
Q
2
Q
1
Q
1
Q
0
Q
0
DESCRIPTION
The SY100S331 offers three D-type, edge-triggered
master/slave flip-flops with true and complement outputs,
designed for use in high-performance ECL systems. Each
flip-flop is controlled by a common clock (CP
c), as well as
its own clock pulse (CPn). The resultant clock signal
controlling the flip-flop is the logical OR operation of these
two clock signals. Data enters the master when both CPc
and CPn are LOW and enters the slave on the rising edge
of either CPc or CPn (or both).
Additional control signals include Master Set (MS) and
Master Reset (MR) inputs. Each flip-flop also has its own
Direct Set (SDn) and Direct Clear (CDn) signals. The MR,
MS, SDn and DCn signals override the clock signals. The
inputs on this device have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
0
0
V
CP
V
SD
MS
EES
MR
D
0
SD
CD
CP
12
C
13
14
EE
15
16
17
1
1
Top View
PLCC
J28-1
1911201021922823724
2
1
1
SD
CD
CP
EES
V
EES
V
CP
CD
SD
CD
CP
0
D
2
CD
D
0
0
Q
Q
6
5
Q
1
4
3
Q
1
2
V
CCA
1
V
CC
28
V
CC
27
Q
2
2
CP
25
2618
2
D
2
Q
1
D1SD
MR
EE
V
CPCMS
19
SD
CD
CP
D
Q
Q
0
0
0
0
0
0
1
1
1
2
2
2
2
2
Top View
3
Flatpack
4
F24-1
5
6
18
17
16
15
14
13
7248239221021112012
MS MR
2
2
Q
Q
1
1
CCA
V
1
Q
Q
CC
V
Rev.: G Amendment: /0
Issue Date: July, 1999
Micrel
PIN NAMES
Pin Function
CP0 – CP2 Individual Clock Inputs
CPc Common Clock Input
D0 – D2 Data Inputs
CD0 – CD2 Individual Direct Clear Inputs
SDn Individual Direct Set Inputs
MR Master Reset Input
MS Master Set Input
Q0 – Q2 Data Outputs
Q0 – Q2 Complementary Data Outputs
VEES VEE Substrate
CCA VCCO for ECL Outputs
V
TRUTH TABLES
SY100S331
Asynchronous Operation
(1)
Inputs Outputs
MS MR
Dn CPn CPc SDn DCn Qn (t+1)
XX XH L H
XX XL H L
XX XH H U
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
Dn CPn CPc SDn DCn Qn
Lu LL L L
Hu LL L H
LL uL L L
HL uL L H
XL L L LQn (t)
XH XL LQn (t)
XX HL LQ
NOTE:
1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U =
Undefined, t = Time before CP Positive Transition, t+1 = Time after CP
Positive Transition, u = Low-to-High Transition
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Synchronous Operation
(1)
Inputs Outputs
MS MR
n (t)
Symbol Parameter Min. Typ. Max. Unit Condition
IIH Input HIGH Current, All Inputs — — 200 µAVIN = VIH (Max.)
EE Power Supply Current –80 –65 –35 mA Inputs Open
I
2
Micrel
SY100S331
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
fmax Toggle Frequency 800 — 800 — 800 — MHz
PLH Propagation Delay 300 800 300 800 300 800 ps
t
tPHL CPc to Output
PLH Propagation Delay 300 800 300 800 300 800 ps
t
tPHL CPn to Output
PLH Propagation Delay 300 900 300 900 300 900 ps
t
tPHL CDn, SDn to Output
t
PLH Propagation Delay 300 1000 300 1000 300 1000 ps
tPHL MS, MR to Output
TLH Transition Time 300 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
S Set-up Time ps
t
Dn 400 — 400 — 400 —
CDn, SDn (Release Time) 500 — 500 — 500 —
MS, MR (Release Time) 800 — 800 — 800 —
tH Hold Time Dn 300 — 300 — 300 — ps
pw (H) Pulse Width HIGH 800 — 800 — 800 — ps
t
CPn, CPc, DCn
SDn, MR, MS
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
fmax Toggle Frequency 800 — 800 — 800 — MHz
PLH Propagation Delay 300 700 300 700 300 700 ps
t
tPHL CPc to Output
PLH Propagation Delay 300 700 300 700 300 700 ps
t
tPHL CPn to Output
PLH Propagation Delay 300 800 300 800 300 800 ps
t
tPHL CDn, SDn to Output
PLH Propagation Delay 300 900 300 900 300 900 ps
t
tPHL MS, MR to Output
t
TLH Transition Time 300 900 300 900 300 900 ps
tTHL 20% to 80%, 80% to 20%
S Set-up Time ps
t
Dn 400 — 400 — 400 —
CDn, SDn (Release Time) 500 — 500 — 500 —
MS, MR (Release Time) 800 — 800 — 800 —
tH Hold Time Dn 300 — 300 — 300 — ps
pw (H) Pulse Width HIGH 800 — 800 — 800 — ps
t
CPn, CPc, DCn
SDn, MR, MS
3
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