9-BIT ECL-TO-TTL
WITH 3-STATE ENABLE
SY10H601
SY100H601
FEATURES
■ 9-bit ideal for byte-parity applications
■ 3-state TTL outputs
■ Flow-through configuration
■ Extra TTL and ECL power/ground pins to minimize
switching noise
■ ECL and TTL 3-state control inputs
■ 4.8ns max. delay into 50pF, 9.6ns into 200pF (all
outputs switching)
■ PNP TTL inputs for low loading
■ Choice of ECL compatibility: MECL 10KH (10Hxxx)
DESCRIPTION
The SY10/100H601 are 9-bit, dual supply ECL-to-TTL
translators. Devices in the Micrel-Synergy 9-bit translator
series utilize the 28-lead PLCC for optimal power pinning,
signal flow-through and electrical performance.
The devices feature a 48mA TTL output stage and AC
performance is specified into both a 50pF and 200pF
load capacitance. For the 3-state output disable, both
ECL and TTL control inputs are provided, allowing
maximum design flexibility.
The 10H version is compatible with MECL 10KH ECL
logic levels. The 100H version is compatible with 100K
levels.
or 100K (100Hxxx)
■ Fully compatible with Motorola MC10H/100H601
■ Available in 28-pin PLCC package
BLOCK DIAGRAM PIN CONFIGURATION
OEECL
OETTL
D
D
D
D
Q
0
0
Q4
Q3
Q
1
1
VCCT
Q2
GND
Q
2
2
Q1
Q0
Q
3
Q5
25
24 23 22 21 20 19
26
27
28
1
2
3
4
567891011
VCCTQ6
GND
TOP VIEW
PLCC
GND
7
8
Q
Q
18
D8
17
D7
16
VCCE
15
D6
14
D5
13
D4
12
D3
D1
D0
ECL TTL
D
4
D
Q
4
Q
5
NC
OETTL
VEE
OEECL
D2
PIN NAMES
Q
D
6
D
7
D
8
6
Q
7
Pin Function
GND TTL Ground (0V)
VCCE ECL VCC (0V)
Q
8
VCCT TTL Supply (+5.0V)
VEE ECL Supply (–5.2/–4.5V)
D0–D8 Data Inputs (ECL)
Q0–Q8 Data Outputs (TTL)
OEECL 3-State Control (ECL)
OETTL 3-State Control (TTL)
Rev.: D Amendment: /0
1
Issue Date: February, 1998
SY10H601
Micrel
SY100H601
LOGIC DIAGRAMTRUTH TABLE
OEECL OETTL D Q
LLL L
LLH H
HXX Z
XHX Z
DC ELECTRICAL CHARACTERISTICS
VCCT = 5.0V ± 10%; VEE = –4.75V to –5.5V (10H Version); VEE = –4.2V to –5.5V (100H Version)
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
IEE Power Supply Current, ECL — 46 — 46 — 50 mA —
I
CCH Power Supply Current, TTL — 110 — 110 — 110 mA —
ICCL — 110 — 110 — 110
ICCZ — 105 — 105 — 105
IOS Output Short Circuit Current –100 –225 –100 –225 –100 –225 mA VOUT = 0V
IOZH Output Disable Current HIGH — 50 — 50 — 50 µAVOUT = 2.7V
I
OZL Output Disable Current LOW —–50 —–50 —–50 µAVOUT = 0.5V
LOGIC DIAGRAMAC ELECTRICAL CHARACTERISTICS
VCCT = 5.0V ± 10%; VEE = –4.75V to –5.5V (10H Version); VEE = –4.2V to –5.5V (100H Version)
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
PLH Propagation Delay to Output 1.7 4.8 1.7 4.8 1.7 4.8 ns CL = 50pF
t
tPHL 3.4 9.6 3.4 9.6 3.4 9.6 CL = 200pF
tPLZ Output Disable Time, OEECL 3.7 6.5 3.7 6.5 3.7 6.5 ns CL = 50pF
tPHZ 5.4 13 5.4 13 5.4 13 CL = 200pF
t
PLZ Output Disable Time, OETTL 4.3 7.5 4.3 7.5 4.3 7.5 ns CL = 50pF
tPHZ 7.0 15 7.0 15 7.0 15 CL = 200pF
t
PZL Output Enable Time, OEECL 3.5 6.0 3.5 6.0 3.5 6.0 ns CL = 50pF
tPZH 5.0 12 5.0 12 5.0 12 CL = 200pF
tPZL Output Enable Time, OETTL 4.2 7.0 4.2 7.0 4.2 7.0 ns CL = 50pF
tPZH 6.0 14 6.0 14 6.0 14 CL = 200pF
t
r Output Rise/Fall Time — 1.2 — 1.2 — 1.2 ns CL = 50pF
tf 1.0V – 2.0V — 3.0 — 3.0 — 3.0 CL = 200pF
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10H601JC J28-1 Commercial
SY10H601JCTR J28-1 Commercial
SY100H601JC J28-1 Commercial
SY100H601JCTR J28-1 Commercial
2