MICREL SY10E111A, SY10E111L, SY100E111L, SY100E111A Datasheet

DESCRIPTION
FEATURES
Rev.: F Amendment: /0 Rev. Date: October, 1998
ClockWorks™
SY10E111A/L
SY100E111A/L
5V/3.3V 1:9 DIFFERENTIAL CLOCK DRIVER (w/o ENABLE)
5V and 3.3V power supply options
200ps part-to-part skew
50ps output-to-output skew
Differential design
VBB output
Voltage and temperature compensated outputs
75K input pulldown resistors
Fully compatible with Motorola MC100LVE111
Available in 28-pin PLCC package
The SY10/100E111A/L are low skew 1-to-9 differential driver designed for clock distribution in mind. The SY10/ 100E111A/L's function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs.
The E111A/L are specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer that nine pairs are used, it is necessary to terminate at least the output pairs on the same package side as the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of the output(s) being used which, while not being catastrophic to most designs, will mean a loss of skew margin.
The E111A/L, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the E111A/L to be used for high performance clock distribution in +5V/+3.3V systems. Designers can take advantage of the E111A/L's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For systems incorporating GTL, parallel termination offers the lowest power by taking advantage of the 1.2V supply as terminating voltage.
BLOCK DIAGRAM
IN
V
BB
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
Q
8
IN
1
2
ClockWorks™
SY10E111A/L
SY100E111A/L
Micrel
T
A = –40°CTA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
V
OH Output HIGH Voltage mV
10EL –1080 –890 –1020 –840 –980 –810 –910 –720
100EL –1085 –880 –1025 –880 –1025 –880 –1025 –880
V
OL Output LOW Voltage mV
10EL –1950 –1650 –1950 –1630 –1950 –1630 –1950 –1595
100EL –1830 –1550 –1810 –1620 –1810 –1620 –1810 –1620
V
IH Input HIGH Voltage mV
10EL –1230 –890 –1170 –840 –1130 –810 –1060 –720
100EL –1165 –880 –1165 –880 –1165 –880 –1165 –880
V
IL Input LOW Voltage mV
10EL –1950 –1500 –1950 –1480 –1950 –1480 –1950 –1445
100EL –1810 –1475 –1810 –1475 –1810 –1475 –1810 –1475
V
BB Output Reference V
Voltage 10EL –1.43 –1.30 –1.38 –1.27 –1.35 –1.25 –1.31 –1.19
100EL –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 IIH Input HIGH Current 150 150 150 150 µA I
IL Input LOW Current µA
10EL 0.5 0.5 0.5 0.3
100EL 0.5 0.5 0.5 0.5 — I
EE Power Supply Current mA
10EL 35 65 35 65 35 65 35 65
100EL 35 65 35 65 35 65 35 75
VEE = VEE (Min.) to VEE (Max.); VCC = GND
NOTE:
1. Parametric values specified at: 5 volt Power Supply Range 100E111A Series: -4.2V to -5.5V. 10E111A Series -4.75V to -5.5V.
3 volt Power Supply Range 10/100E111L Series: -3.0V to -3.8V.
ECL DC ELECTRICAL CHARACTERISTICS
(1)
PIN CONFIGURATION
V
CC
V
EE
NC
V
BB
IN
Q
2
26 27 28
1 2 3 4
18 17 16 15 14 13 12
25 24 23 22 21 20 19
567891011
NC
IN
Q6Q
6
Q
3
Q
1
PLCC
TOP VIEW
J28-1
Q
2
Q0Q
0
V
CCO
Q
1
Q
3
Q
4
V
CCO
Q
4
Q
5
Q
5
Q
7
V
CCO
Q
7
Q
8
Q
8
PIN NAMES
Pin Function
IN, IN Differential Input Pair Q0, Q0 Q8, Q8 Differential Outputs VBB VBB Output V
CCO VCC to Output
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