MICREL MIC59P50BN, MIC59P50BV, MIC59P50BWM Datasheet

MIC59P50 Micrel

MIC59P50

8-Bit Parallel-Input Protected Latched Driver

General Description

The MIC59P50 parallel-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common CLEAR, STROBE, and OUTPUT ENABLE func­tions. Similar to the MIC5801, additional protection circuitry
supplied on this device includes thermal shutdown, under
voltage lockout (UVLO), and over-current shutdown.

The bipolar/MOS combination provides an extremely low­power latch with maximum interface flexibility. The MIC59P50
has open-collector outputs capable of sinking 500mA and
integral diodes for inductive load transient suppression with
a minimum output breakdown voltage rating of 80V above V
(50V sustaining). The drivers can be operated with a split
supply, where the negative supply is down to –20V and may
be paralleled for higher load current capability.

With a 5V logic supply, the MIC59P50 will typically operate at
better than 5MHz. With a 12V logic supply, significantly
higher speeds are obtained. The CMOS inputs are compat­ible with standard CMOS, PMOS, and NMOS circuits. TTL
circuits may require pull-up resistors.

Each of these eight outputs has an independent over-current
shutdown at 500 mA. Upon current shutdown, the affected
channel will turn OFF and the flag will go low until VDD is
cycled or the ENABLE/RESET pin is pulsed high. Current
pulses less than 2µs will not activate over-current shutdown.
Temperatures above 165°C will shut down the device and
activate the open collector FLAG output at pin 1. The UVLO
circuit disables the outputs at low VDD; hysteresis of 0.5V is

provided.

Features

• 4.4 MHz Minimum Data Input Rate

• High-Voltage, High-Current Outputs

• Per-Output Over-Current Shutdown (500mA Typical)

• Undervoltage Lockout

• Thermal Shutdown

• Output Fault Flag

• Output Transient Protection Diodes

• CMOS, PMOS, NMOS, and TTL Compatible Inputs

• Internal Pull-Down Resistors

• Low-Power CMOS Latches

• Single or Split Supply Operation

EE

Ordering Information

Part Number Temperature Range Package

MIC59P50BN –40°C to +85°C 24-Pin Plastic DIP*
MIC59P50BV –40°C to +85°C 28-Pin PLCC
MIC59P50BWM –40°C to +85°C 24-Pin Wide SOIC

* 300-mil “skinny DIP”

Functional Diagram

STROBE

V

DD

2.2R

+
–

1.25V
R

UVLO

IN

CLEAR

FLAG

THERMAL

SHUTDOWN

ENABLE/RESET

SRQ

Circuitry below dashed line is
included in each of the 8 channels.

I

SHUTDOWN

Pin Configuration

(DIP and SOIC)

I

1

FLAG

I

REF

–

+

R1

70k

COMMON

V

EE

I

OUT

R2
3k

/ N

OUTPUT

CLEAR

STROBE

IN 1

IN 2

IN 3
IN 4

IN 5

IN 6

IN 7

IN 8

V

2

3

4

5

6

7

8

9

10

11

12

EE

7-58 October 1998

THERMAL

SHUTDOWN

LATCHES

UVLO

LIMIT

24

V

SS

OUTPUT

23

ENABLE/RESET

22

V

DD

21

OUT 1

20

OUT 2

19

OUT 3
OUT 4

18

OUT 5

17

OUT 6

16

15

OUT 7

14

OUT 8

13

COMMON

MIC59P50 Micrel

Absolute Maximum Ratings T

= +25°C

A

Output Voltage (VCE) ....................................................80V

Supply Voltage (VDD) ....................................................15V

(VDD – VEE) ...............................................................25V

Input Voltage (VIN) ............................... –0.3V to VDD+0.3V

Continuous Collector Current (IC) ............................500mA

Protected Current............................................1.5A, Note 1

Power Dissipation (PD)

Plastic DIP (N).........................................................2.4W

Derate above TA = +25°C ............................24mW/°C

PLCC (V).................................................................1.6W

Derate above TA = +25°C ............................16mW/°C

Wide SOIC (WM) ....................................................1.4W

Derate above TA = +25°C ............................14mW/°C

Operating Temperature (TA)

Plastic DIP (N), PLCC (V), SOIC (WM)..–40°C to +85°C

Storage Temperature (TS) .......................–65°C to +150°C

Junction Temperature (TJ) ...................................... +150°C

ESD ......................................................................... Note 2

Note 1: Each channel. VEE connection must be designed to minimize
Note 2: Devices are input-static protected but can be damage by

inductance and resistance.
extremely high static charges.

PLCC Pin Configuration

SS

EE

V

V

CLEAR

FLAG

2

28 27 26

1

MIC59P50BV

1615

14

EE

NC

NC

NC

V

IN 1
IN 2

IN 3
IN 4

IN 5
IN 6
IN 7

STROBE

4

3

5

6

7

8

9

10

11

12 13

IN 8

Allowable Output Current

MIC59P50BN

450

DD

V

OE/RESET

18

17

OUT 8

COMMON

25

OUT 1

24

OUT 2
OUT 3

23

22

OUT 4
OUT 5

21

20

OUT 6

19

OUT 7

Typical Input

IN

Pin Description

Pin Name Description

1 FLAG Error Flag. Open Collector Output is Low upon Overcurrent Fault or

2 CLEAR Sets All Latches OFF (open).
3 STROBE Input Strobe Pin. Loads output latches when High.

4–11 INPUT Parallel Inputs, 1 through 8

12 V

13 COMMON Transient suppression diodes cathode common pin.

14–21 OUTPUT Parallel Outputs, 8 through 1.

22 V
23 OUTPUT ENABLE RESET Output Enable Reset. When Low, Outputs are active. When High, outputs

24 V

EE

DD

SS

400

350

V

DD

300

250

200

NUMBER OF OUTPUTS

150

CONDUCTING
SIMULTANEOUSLY

100

0102030405060708090100

ALLOWABLE COLLECTOR CURRENT IN mA AT 50°C

PERCENT DUTY CYCLE

4

5

6

7

8

1 or 2

3

7

Overtemperature Fault. OUTPUT ENABLE/RESET must be pulled high to
reset the flag and fault condition.

Output Ground (Substrate). Most negative voltage in the system connects
here.

Logic Positive Supply voltage.

are inactive and the Flag and outputs are reset from a fault condition. An
undervoltage condition emulates a high OE input.

Logic reference (Ground) pin.

October 1998 7-59