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Micrel KSZ8692 SPI Controller
Programmer’s Guide
Micrel KSZ8692 SPI Controller Programmer’s Guide
Version 1.0
07/18/2008
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Micrel KSZ8692 SPI Controller
Programmer’s Guide
Table of Contents
1 Overview ................................................................................................................................. 3
2 Atmel AT25160A EEPROM .................................................................................................. 4
2.1 Read/Write 1-byte From SPI device ............................................................................... 4
2.2 Read/Write 4-byte From SPI device ............................................................................... 6
3 Micrel KS8995M Switch ........................................................................................................ 8
3.1 Read/Write 1-byte From SPI device ............................................................................... 8
3.2 Read/Write 2-byte From SPI device ............................................................................... 9
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Micrel KSZ8692 SPI Controller
Programmer’s Guide
1 Overview
This document shows two examples of the programming sequences for the KSZ8692 SPI
controller when Linux u-boot SPI driver performs read/write data from/to SPI device.
The first SPI device is an Atmel AT25160A memory (EEPROM) which uses 2 byte
address offset and 8-bit data per transfer.
The second SPI device is a Micrel KS8995M switch which uses 1 byte address offset and
16-bit data per transfer.
Please refer to KSZ8692 datasheet for detail register programming information.
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Micrel KSZ8692 SPI Controller
Programmer’s Guide
2 Atmel AT25160A EEPROM
The AT25160A memory (EEPROM) can be read/write through the SPI interface. It is organized
as 2048 words of 8 bits each with 2-byte address (A15-A0) offset.
The following examples shows how to read/write data from/to EPPROM address offset (2-byte)
under the Linux U-boot 1.1.4 “sspi” command. KS8692 SPI controller is configured as 8-bit data
per transfer and SPI mode 2.
2.1 Read/Write 1-byte From SPI device
Write 1-byte data ‘0x11’ to address offset 0x10
boot > sspi 0 8 021011
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_byte: regOffset=0010, length=1
write_enable: spi_tdr 1FFFE908:00068000
spi_issue_cmd: spi_tdr 1FFFE908:00020000
spi_write_byte: spi_tdr 1FFFE908:00100000
spi_write_byte: spi_tdr 1FFFE908:00000000
spi_write_byte: spi_tdr 1FFFE908:00118000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Write 1-byte data ‘0x22’ to address offset 0x11
boot > sspi 0 8 021122
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_byte: regOffset=0011, length=1
write_enable: spi_tdr 1FFFE908:00068000
spi_issue_cmd: spi_tdr 1FFFE908:00020000
spi_write_byte: spi_tdr 1FFFE908:00110000
spi_write_byte: spi_tdr 1FFFE908:00000000
spi_write_byte: spi_tdr 1FFFE908:00228000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Write 1-byte data ‘0x33’ to address offset 0x12
boot > sspi 0 8 021233
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Programmer’s Guide
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_byte: regOffset=0012, length=1
write_enable: spi_tdr 1FFFE908:00068000
spi_issue_cmd: spi_tdr 1FFFE908:00020000
spi_write_byte: spi_tdr 1FFFE908:00120000
spi_write_byte: spi_tdr 1FFFE908:00000000
spi_write_byte: spi_tdr 1FFFE908:00338000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Write 1-byte data ‘0x44’ to address offset 0x13
boot > sspi 0 8 021344
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_byte: regOffset=0013, length=1
write_enable: spi_tdr 1FFFE908:00068000
spi_issue_cmd: spi_tdr 1FFFE908:00020000
spi_write_byte: spi_tdr 1FFFE908:00130000
spi_write_byte: spi_tdr 1FFFE908:00000000
spi_write_byte: spi_tdr 1FFFE908:00448000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Read 1-byte data from dress offset 0x10
boot > sspi 0 8 0310
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_byte: regOffset=0010, length=1
spi_issue_cmd: spi_tdr 1FFFE908:00030000
spi_read_byte: spi_tdr 1FFFE908:00100000
spi_read_byte: spi_tdr 1FFFE908:0000a001
spi_read_byte: spi_rdr 1FFFE904:00110000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
11
Read 1-byte data from dress offset 0x11
boot > sspi 0 8 0311
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
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Programmer’s Guide
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_byte: regOffset=0011, length=1
spi_issue_cmd: spi_tdr 1FFFE908:00030000
spi_read_byte: spi_tdr 1FFFE908:00110000
spi_read_byte: spi_tdr 1FFFE908:0000a001
spi_read_byte: spi_rdr 1FFFE904:00220000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
22
Read 1-byte data from dress offset 0x12
boot > sspi 0 8 0312
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_byte: regOffset=0012, length=1
spi_issue_cmd: spi_tdr 1FFFE908:00030000
spi_read_byte: spi_tdr 1FFFE908:00120000
spi_read_byte: spi_tdr 1FFFE908:0000a001
spi_read_byte: spi_rdr 1FFFE904:00330000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
33
Read 1-byte data from dress offset 0x13
boot > sspi 0 8 0313
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_byte: regOffset=0013, length=1
spi_issue_cmd: spi_tdr 1FFFE908:00030000
spi_read_byte: spi_tdr 1FFFE908:00130000
spi_read_byte: spi_tdr 1FFFE908:0000a001
spi_read_byte: spi_rdr 1FFFE904:00440000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
44
2.2 Read/Write 4-byte From SPI device
Write 4-byte data ‘0x12345678’ to address offset 0x20
boot > sspi 0 32 022012345678
spi_reset: spi_ctr 1FFFE900:80000000
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Programmer’s Guide
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_byte: regOffset=0020, length=4
write_enable: spi_tdr 1FFFE908:00068000
spi_issue_cmd: spi_tdr 1FFFE908:00020000
spi_write_byte: spi_tdr 1FFFE908:00200000
spi_write_byte: spi_tdr 1FFFE908:00000000
spi_write_byte: spi_tdr 1FFFE908:00120000
spi_write_byte: spi_tdr 1FFFE908:00340000
spi_write_byte: spi_tdr 1FFFE908:00560000
spi_write_byte: spi_tdr 1FFFE908:00788000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Read 4-byte data from dress offset 0x20
boot > sspi 0 32 0320
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:98880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_byte: regOffset=0020, length=4
spi_issue_cmd: spi_tdr 1FFFE908:00030000
spi_read_byte: spi_tdr 1FFFE908:00200000
spi_read_byte: spi_tdr 1FFFE908:0000a004
spi_read_byte: spi_rdr 1FFFE904:00120000
spi_read_byte: spi_rdr 1FFFE904:00340000
spi_read_byte: spi_rdr 1FFFE904:00560000
spi_read_byte: spi_rdr 1FFFE904:00780000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
12345678
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Programmer’s Guide
1
3 Micrel KS8995M Switch
The Micrel KS8995M switch can be configured through the SPI interface1. It uses 1 byte of
address offset and 16-bit data per transfer.
The following examples shows how to read/write data from/to KS8995M switch register offset
(1-byte) under U-boot 1.1.4 “sspi” command. KS8692 SPI controller is configured as 16-bit data
per transfer, and SPI mode 0.
3.1 Read/Write 1-byte From SPI device
Write 1-byte data ‘0x12’ to address offset 0x68
boot > sspi 0 8 026812
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:18880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_word: regOffset=68, length=1
spi_write_word: spi_tdr 1FFFE908:02680800
spi_write_word: spi_tdr 1FFFE908:12000800
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Write 1-byte data ‘0x34’ to address offset 0x69
boot > sspi 0 8 026934
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:18880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_word: regOffset=69, length=1
spi_write_word: spi_tdr 1FFFE908:02690800
spi_write_word: spi_tdr 1FFFE908:34340800
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Read 1-byte data from dress offset 0x68
boot > sspi 0 8 0368
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:18880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_word: regOffset=68, length=1
Set KS8995 SPI to slave mode when access from KS8692 SPI controller.
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spi_read_word: spi_tdr 1FFFE908:0368a801
spi_read_word: spi_rdr 1FFFE904:12340000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
12
Read 1-byte data from dress offset 0x69
boot > sspi 0 8 0369
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:18880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_word: regOffset=69, length=1
spi_read_word: spi_tdr 1FFFE908:0369a801
spi_read_word: spi_rdr 1FFFE904:34340000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
34
3.2 Read/Write 2-byte From SPI device
Write 2-byte data ‘0x5678’ to address offset 0x6A
boot > sspi 0 16 026a5678
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:18880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_write_word: regOffset=6A, length=2
spi_write_word: spi_tdr 1FFFE908:026a0800
spi_write_word: spi_tdr 1FFFE908:56788800
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
Read 2-byte data from dress offset 0x06A
boot > sspi 0 16 036a
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:18880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_word: regOffset=6A, length=2
spi_read_word: spi_tdr 1FFFE908:036aa802
spi_read_word: spi_rdr 1FFFE904:56780000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
5678
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Programmer’s Guide
Read 2-byte data from dress offset 0x0
boot > sspi 0 16 0300
spi_reset: spi_ctr 1FFFE900:80000000
spi_init: spi_csr 1FFFE91C:18880101
spi_ks_chipsel: spi_ctr 1FFFE900:40000000
spi_read_word: regOffset=00, length=2
spi_read_word: spi_tdr 1FFFE908:0300a802
spi_read_word: spi_rdr 1FFFE904:95060000
spi_ks_chipsel: spi_ctr 1FFFE900:00000000
9506
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