Micrel KS8995MA User Manual

KS8995MA Micrel, Inc.

KS8995MA

Integrated 5-Port 10/100 Managed Switch

Rev 2.4

General Description

The KS8995MA is a highly integrated Layer 2 managed switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set such as tag/port-based VLAN, quality of service (QoS) priority, management, MIB counters, dual MII interfaces and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications.

The KS8995MA contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory.

All PHY units support 10BASE-T and 100BASE-TX. In addition, two of the PHY units support 100BASE-FX (ports 4 and 5).

Functional Diagram

Features

•Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard

• Shared memory based switch fabric with fully nonblocking configuration

•1.4Gbps high-performance memory bandwidth

• 10BASE-T, 100BASE-TX, and 100BASE-FX modes (FX in ports 4 and 5)

• Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII)

•IEEE 802.1q tag-based VLAN (16 VLANs, full-range VID) for DMZ port, WAN/LAN separation or inter-VLAN switch links

• VLAN ID tag/untag options, per-port basis

•Programmable rate limiting 0Mbps to 100Mbps, ingress and egress port, rate options for high and low priority, per-port basis in 32Kbps increments

•Flow control or drop packet rate limiting (ingress port)

•Integrated MIB counters for fully compliant statistics gathering, 34 MIB counters per port

Auto

MDI/MDI-X

Auto

MDI/MDI-X

Auto

MDI/MDI-X

Auto

MDI/MDI-X

Auto

MDI/MDI-X

MII-P5

MDC, MDI/O

MII-SW or SNI

Control Reg I/F

LED0[5:1] LED1[5:1] LED2[5:1]

10/100

T/Tx 1

10/100

T/Tx 2

10/100

T/Tx 3

10/100

T/Tx/Fx 4

10/100

T/Tx/Fx 5

LED I/F

10/100 MAC 1

10/100 MAC 2

10/100 MAC 3

10/100 MAC 4

10/100 MAC 5

SNI

SPI

Control

Registers

FIFO, Flow Control, VLAN

Ta gging, Priority

1K Look-Up

Engine

Queue Mgmnt

Buffer

Mgmnt

Frame

Buffers

MIB

Counters

EEPROM

I/F

KS8995MA

Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

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Features (continued)

• Enable/Disable option for huge frame size up to 1916 bytes per frame

•IGMP v1/v2 snooping for multicast packet filtering

• Special tagging mode to send CPU info on ingress packet’s port value

• SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configuration

• MAC-id based security lock option

• Control registers configurable on-the-fly (port-priority,

802.1p/d/q, AN...)

• CPU read access to MAC forwarding table entries

• 802.1d Spanning Tree Protocol

• Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII

•Broadcast storm protection with % control – global and per-port basis

• Optimization for fiber-to-copper media conversion

• Full-chip hardware power-down support (register configuration not saved)

• Per-port based software power-save on PHY (idle link detection, register configuration preserved)

• QoS/CoS packets prioritization supports: per port,

802.1p and DiffServ based

• 802.1p/q tag insertion or removal on a per-port basis (egress)

• MDC and MDI/O interface support to access the MII PHY control registers (not all control registers)

•MII local loopback support

• On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table)

•Wire-speed reception and transmission

•Integrated look-up engine with dedicated 1K MAC addresses

• Full duplex IEEE 802.3x and half-duplex back pressure flow control

• Comprehensive LED support

•7-wire SNI support for legacy MAC interface

• Automatic MDI/MDI-X crossover for plug-and-play

•Disable automatic MDI/MDI-X option

• Low power:

Core: 1.8V I/O: 2.5V or 3.3V

•0.18µm CMOS technology

• Commercial temperature range: 0°C to +70°C

•Industrial temperature range: –40°C to +85°C

• Available in 128-pin PQFP package

Applications

•Broadband gateway/firewall/VPN

•Integrated DSL or cable modem multi-port router

•Wireless LAN access point plus gateway

• Home networking expansion

•Standalone 10/100 switch

• Hotel/campus/MxU gateway

• Enterprise VoIP gateway/phone

• FTTx customer premise equipment

• Managed Media converter

Ordering Information

Part Number Temp. Range Package Lead Finish

KS8995MA 0°C to +70°C 128-Pin PQFP Standard

KSZ8995MA 0°C to +70°C 128-Pin PQFP Lead-Free

KS8995MAI –40°C to +85°C 128-Pin PQFP Standard

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Revision History

Revision Date Summary of Changes

2.0 10/10/03 Created.

2.1 10/30/03 Editorial changes on electrical characteristics.

2.2 4/1/04 Editorial changes on the TTL input and output electrical characteristics.

2.3 1/19/05 Insert recommended reset circuit., Pg. 70. Editorial, Pg. 36

2.4 4/13/05 Changed VDDIO to 3.3V. Changed Jitter to 16 ns Max.

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Table of Contents

System Level Applications ......................................................................................................................................... 7

Pin Description by Number ........................................................................................................................................ 9

Pin Description by Name .......................................................................................................................................... 15

Pin Configuration ...................................................................................................................................................... 21

Introduction ........................................................................................................................................................... 22

Functional Overview: Physical Layer Transceiver ............................................................................................... 22

100BASE-TX Transmit ........................................................................................................................................ 22

100BASE-TX Receive ......................................................................................................................................... 22

PLL Clock Synthesizer......................................................................................................................................... 22

Scrambler/De-scrambler (100BASE-TX only) ..................................................................................................... 22

100BASE-FX Operation....................................................................................................................................... 22

100BASE-FX Signal Detection ............................................................................................................................ 22

100BASE-FX Far End Fault ................................................................................................................................ 23

10BASE-T Transmit ............................................................................................................................................. 23

10BASE-T Receive .............................................................................................................................................. 23

Power Management ............................................................................................................................................. 23

MDI/MDI-X Auto Crossover ................................................................................................................................. 23

Auto-Negotiation .................................................................................................................................................. 23

Functional Overview: Switch Core ......................................................................................................................... 24

Address Look-Up ................................................................................................................................................. 24

Learning ........................................................................................................................................................... 24

Migration ........................................................................................................................................................... 24

Aging ........................................................................................................................................................... 24

Forwarding ........................................................................................................................................................... 24

Switching Engine ................................................................................................................................................. 24

MAC Operation .................................................................................................................................................... 24

Inter-Packet Gap (IPG) ................................................................................................................................ 24

Backoff Algorithm ......................................................................................................................................... 24

Late Collision................................................................................................................................................ 26

Illegal Frames .............................................................................................................................................. 26

Flow Control ................................................................................................................................................. 26

Half-Duplex Back Pressure .......................................................................................................................... 26

Broadcast Storm Protection ......................................................................................................................... 26

MII Interface Operation ........................................................................................................................................ 26

SNI Interface Operation ....................................................................................................................................... 28

Advanced Functionality............................................................................................................................................ 28

Spanning Tree Support ........................................................................................................................................ 28

Special Tagging Mode ......................................................................................................................................... 29

IGMP Support ...................................................................................................................................................... 30

Port Mirroring Support ......................................................................................................................................... 31

VLAN Support ...................................................................................................................................................... 31

Rate Limit Support ............................................................................................................................................... 32

Configuration Interface ........................................................................................................................................ 33

I2C Master Serial Bus Configuration ............................................................................................................ 35

SPI Slave Serial Bus Configuration ............................................................................................................. 35

MII Management Interface (MIIM) ....................................................................................................................... 38

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Register Description ................................................................................................................................................. 39

Global Registers .................................................................................................................................................. 39

Register 0 (0x00): Chip ID0 ......................................................................................................................... 39

Register 1 (0x01): Chip ID1/Start Switch ..................................................................................................... 39

Register 2 (0x02): Global Control 0 ............................................................................................................. 40

Register 3 (0x03): Global Control 1 ............................................................................................................. 40

Register 4 (0x04): Global Control 2 ............................................................................................................. 41

Register 5 (0x05): Global Control 3 ............................................................................................................. 42

Register 6 (0x06): Global Control 4 ............................................................................................................. 42

Register 7 (0x07): Global Control 5 ............................................................................................................. 43

Register 8 (0x08): Global Control 6 ............................................................................................................. 43

Register 9 (0x09): Global Control 7 ............................................................................................................. 43

Register 10 (0x0A): Global Control 8 ........................................................................................................... 43

Register 11 (0x0B): Global Control 9 ........................................................................................................... 43

Port Registers ...................................................................................................................................................... 44

Register 16 (0x10): Port 1 Control 0 ........................................................................................................... 44

Register 17 (0x11): Port 1 Control 1 ........................................................................................................... 44

Register 18 (0x12): Port 1 Control 2 ........................................................................................................... 45

Register 19 (0x13): Port 1 Control 3 ........................................................................................................... 46

Register 20 (0x14): Port 1 Control 4 ........................................................................................................... 46

Register 21 (0x15): Port 1 Control 5 ........................................................................................................... 46

Register 22 (0x16): Port 1 Control 6 ........................................................................................................... 46

Register 23 (0x17): Port 1 Control 7 ........................................................................................................... 46

Register 24 (0x18): Port 1 Control 8 ........................................................................................................... 47

Register 25 (0x19): Port 1 Control 9 ........................................................................................................... 47

Register 26 (0x1A): Port 1 Control 10 ......................................................................................................... 47

Register 27 (0x1B): Port 1 Control 11 ......................................................................................................... 47

Register 28 (0x1C): Port 1 Control 12 ......................................................................................................... 48

Register 29 (0x1D): Port 1 Control 13 ......................................................................................................... 49

Register 30 (0x1E): Port 1 Status 0 ............................................................................................................ 49

Register 31 (0x1F): Port 1 Control 14 ......................................................................................................... 50

Advanced Control Registers ................................................................................................................................ 50

Register 96 (0x60): TOS Priority Control Register 0 ................................................................................... 50

Register 97 (0x61): TOS Priority Control Register 1 ................................................................................... 50

Register 98 (0x62): TOS Priority Control Register 2 ................................................................................... 50

Register 99 (0x63): TOS Priority Control Register 3 ................................................................................... 50

Register 100 (0x64): TOS Priority Control Register 4 ................................................................................. 50

Register 101 (0x65): TOS Priority Control Register 5 ................................................................................. 50

Register 102 (0x66): TOS Priority Control Register 6 ................................................................................. 50

Register 103 (0x67): TOS Priority Control Register 7 ................................................................................. 50

Register 104 (0x68): MAC Address Register 0 ........................................................................................... 50

Register 105 (0x69): MAC Address Register 1 ........................................................................................... 50

Register 106 (0x6A): MAC Address Register 2 .......................................................................................... 51

Register 107 (0x6B): MAC Address Register 3 .......................................................................................... 51

Register 108 (0x6C): MAC Address Register 4 .......................................................................................... 51

Register 109 (0X6D): MAC Address Register 5 .......................................................................................... 51

Register 110 (0x6E): Indirect Access Control 0 .......................................................................................... 51

Register 111 (0x6F): Indirect Access Control 1 .......................................................................................... 51

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Register 112 (0x70): Indirect Data Register 8 ............................................................................................. 51

Register 113 (0x71): Indirect Data Register 7 ............................................................................................. 51

Register 114 (0x72): Indirect Data Register 6 ............................................................................................. 51

Register 115 (0x73): Indirect Data Register 5 ............................................................................................. 51

Register 116 (0x74): Indirect Data Register 4 ............................................................................................. 51

Register 117 (0x75): Indirect Data Register 3 ............................................................................................. 51

Register 118 (0x76): Indirect Data Register 2 ............................................................................................. 51

Register 119 (0x77): Indirect Data Register 1 ............................................................................................. 51

Register 120 (0x78): Indirect Data Register 0 ............................................................................................. 51

Register 121 (0x79): Digital Testing Status 0 ............................................................................................. 52

Register 122 (0x7A): Digital Testing Status 1 ............................................................................................. 52

Register 123 (0x7B): Digital Testing Control 0 ............................................................................................ 52

Register 124 (0x7C): Digital Testing Control 1............................................................................................ 52

Register 125 (0x7D): Analog Testing Control 0 .......................................................................................... 52

Register 126 (0x7E): Analog Testing Control 1 ........................................................................................... 52

Register 127 (0x7F): Analog Testing Status ............................................................................................... 52

Static MAC Address .................................................................................................................................................. 53

VLAN Address ........................................................................................................................................................... 55

Dynamic MAC Address ............................................................................................................................................. 56

MIB Counters ........................................................................................................................................................... 57

MIIM Registers ........................................................................................................................................................... 60

Register 0: MII Control ................................................................................................................................. 60

Register 1: MII Status .................................................................................................................................. 61

Register 2: PHYID HIGH ............................................................................................................................. 61

Register 3: PHYID LOW .............................................................................................................................. 61

Register 4: Advertisement Ability ................................................................................................................. 61

Register 5: Link Partner Ability .................................................................................................................... 62

Absolute Maximum Ratings ..................................................................................................................................... 63

Operating Ratings ..................................................................................................................................................... 63

Electrical Characteristics ......................................................................................................................................... 63

Timing Diagrams ....................................................................................................................................................... 65

Selection of Isolation Transformers........................................................................................................................ 72

Qualified Magnetic Lists ........................................................................................................................................... 72

Package Information ................................................................................................................................................. 73

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System Level Applications

CPU

SPI/GPIO

Ethernet

MAC

Ethernet

MAC

10/100 MAC 1

10/100

ff u

B e

m a

r F ip

-C n

MAC 2

10/100 MAC 3

10/100 MAC 4

lle tro

n o

itch w S

10/100 MAC 5

SPI

MII-SW

MII-P5

External WAN port PHY not required.

Figure 1. Broadband Gateway

10/100

PHY 1

10/100

PHY 2

10/100

PHY 3

10/100

PHY 4

10/100

PHY 5

4-port

LAN

1-port

WAN I/F

WAN PHY & AFE

(xDSL, CM...)

r e

f u

lle

r F

h c

SPISPI/GPIO

CPU

Ethernet

MAC

MII-SW

Figure 2. Integrated Broadband Router

10/100 MAC 1

10/100 MAC 2

10/100 MAC 3

10/100 MAC 4

10/100 MAC 5

10/100

PHY 1

10/100

PHY 2

10/100

PHY 3

10/100

PHY 4

10/100

PHY 5

MII-P5

4-port

LAN

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10/100 MAC 1

10/100

f u

lle o

t n o

C h

c it

w S

MAC 2

B e m

10/100

MAC 3

F ip

10/100

MAC 4

10/100 MAC 5

10/100

PHY 1

10/100

PHY 2

10/100

PHY 3

10/100

PHY 4

10/100

PHY 5

Figure 3. Standalone Switch

5-port

LAN

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Pin Description (by Number)

Pin Number Pin Name Type

(1)

Port Pin Function

1 MDI-XDIS Ipd 1-5 Disable auto MDI/MDI-X.

PD (default) = normal operation. PU = disable auto MDI/MDI-X on all ports.

2 GNDA Gnd Analog ground.

3 VDDAR P 1.8V analog VDD.

4 RXP1 I 1 Physical receive signal + (differential).

5 RXM1 I 1 Physical receive signal – (differential).

6 GNDA Gnd Analog ground.

7 TXP1 O 1 Physical transmit signal + (differential).

8 TXM1 O 1 Physical transmit signal – (differential).

9 VDDAT P 2.5V or 3.3V analog VDD.

10 RXP2 I 2 Physical receive signal + (differential).

11 RXM2 I 2 Physical receive signal - (differential).

12 GNDA Gnd Analog ground.

13 TXP2 O 2 Physical transmit signal + (differential).

14 TXM2 O 2 Physical transmit signal – (differential).

15 VDDAR P 1.8V analog VDD.

16 GNDA Gnd Analog ground.

17 ISET Set physical transmit output current. Pull-down with a 3.01kΩ 1%

resistor.

18 VDDAT P 2.5V or 3.3V analog VDD.

19 RXP3 I 3 Physical receive signal + (differential).

20 RXM3 I 3 Physical receive signal – (differential).

21 GNDA Gnd Analog ground.

22 TXP3 O 3 Physical transmit signal + (differential).

23 TXM3 O 3 Physical transmit signal – (differential).

24 VDDAT P 2.5V or 3.3V analog VDD.

25 RXP4 I 4 Physical receive signal + (differential).

26 RXM4 I 4 Physical receive signal – (differential).

27 GNDA Gnd Analog ground.

28 TXP4 O 4 Physical transmit signal + (differential).

29 TXM4 O 4 Physical transmit signal – (differential).

30 GNDA Gnd Analog ground.

(2)

Note:

1. P = Power supply. I = Input. O = Output. I/O = Bidirectional. Gnd = Ground. Ipu = Input w/ internal pull-up. Ipd = Input w/ internal pull-down. Ipd/O = Input w/ internal pull-down during reset, output pin otherwise. Ipu/O = Input w/ internal pull-up during reset, output pin otherwise. NC = No connect.

2. PU = Strap pin pull-up.

PD = Strap pin pull-down.

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Pin Number Pin Name Type

(1)

Port Pin Function

31 VDDAR P 1.8V analog VDD.

32 RXP5 I 5 Physical receive signal + (differential).

33 RXM5 I 5 Physical receive signal – (differential).

34 GNDA Gnd Analog ground.

35 TXP5 O 5 Physical transmit signal + (differential).

36 TXM5 O 5 Physical transmit signal – (differential).

37 VDDAT P 2.5V or 3.3V analog VDD.

38 FXSD5 I 5 Fiber signal detect/factory test pin.

39 FXSD4 I 4 Fiber signal detect/factory test pin.

40 GNDA Gnd Analog ground.

41 VDDAR P 1.8V analog VDD.

42 GNDA Gnd Analog ground.

43 VDDAR P 1.8V analog VDD.

44 GNDA Gnd Analog ground.

45 MUX1 NC Factory test pins. MUX1 and MUX2 should be left unconnected for 46 MUX2 NC normal operation.

Mode MUX1 MUX2

Normal Operation NC NC

47 PWRDN_N Ipu Full-chip power down. Active low.

48 RESERVE NC Reserved pin. No connect.

49 GNDD Gnd Digital ground.

50 VDDC P 1.8V digital core VDD.

51 PMTXEN Ipd 5 PHY[5] MII transmit enable.

52 PMTXD3 Ipd 5 PHY[5] MII transmit bit 3.

53 PMTXD2 Ipd 5 PHY[5] MII transmit bit 2.

54 PMTXD1 Ipd 5 PHY[5] MII transmit bit 1.

55 PMTXD0 Ipd 5 PHY[5] MII transmit bit 0.

56 PMTXER Ipd 5 PHY[5] MII transmit error.

57 PMTXC O 5 PHY[5] MII transmit clock. PHY mode MII.

58 GNDD Gnd Digital ground.

59 VDDIO P 3.3V digital VDD for digital I/O circuitry.

60 PMRXC O 5 PHY[5] MII receive clock. PHY mode MII.

Note:

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KS8995MA Micrel, Inc.

Pin Number Pin Name Type

(1)

Port Pin Function

(2)

61 PMRXDV Ipd/O 5 PHY[5] MII receive data valid.

62 PMRXD3 Ipd/O 5 PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow

control; PU = disable flow control.

63 PMRXD2 Ipd/O 5 PHY[5] MII receive bit 2. Strap option: PD (default) = disable back

pressure; PU = enable back pressure.

64 PMRXD1 Ipd/O 5 PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive

collision packets; PU = does not drop excessive collision packets.

65 PMRXD0 Ipd/O 5 PHY[5] MII receive bit 0. Strap option: PD (default) = disable

aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement.

66 PMRXER Ipd/O 5 PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;

PU = packet size up to 1536 bytes.

67 PCRS Ipd/O 5 PHY[5] MII carrier sense/force duplex mode. See “Register 76” for

port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-negotiation is disabled or fails.

68 PCOL Ipd/O 5 PHY[5] MII collision detect/force flow control. See “Register 66” for

port 4 only. PD (default) = no force flow control. normal operation. PU = force flow control.

69 SMTXEN Ipd Switch MII transmit enable.

70 SMTXD3 Ipd Switch MII transmit bit 3.

71 SMTXD2 Ipd Switch MII transmit bit 2.

72 SMTXD1 Ipd Switch MII transmit bit 1.

73 SMTXD0 Ipd Switch MII transmit bit 0.

74 SMTXER Ipd Switch MII transmit error.

75 SMTXC I/O Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.

76 GNDD Gnd Digital ground.

77 VDDIO P 3.3V digital VDD for digital I/O circuitry

78 SMRXC I/O Switch MII receive clock. Input in MAC mode, output in PHY mode MII.

79 SMRXDV Ipd/O Switch MII receive data valid

80 SMRXD3 Ipd/O Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII

full-duplex flow control; PU = enable switch MII full-duplex flow control.

81 SMRXD2 Ipd/O Switch MII receive bit 2. Strap option: PD (default) = switch MII in full

duplex mode; PU = switch MII in half-duplex mode.

Note:

2. PU = Strap pin pull-up. PD = Strap pin pull-down.

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Pin Number Pin Name Type

(1)

Port Pin Function

(2)

82 SMRXD1 Ipd/O Switch MII receive bit 1. Strap option: PD (default) = switch MII in

100Mbps mode; PU = switch MII in 10Mbps mode.

83 SMRXD0 Ipd/O Switch MII receive bit 0. Strap option: LED mode

PD (default) = mode 0; PU = mode 1. See “Register 11.”

Mode 0 Mode 1

LEDX_2 Lnk/Act 100Lnk/Act

LEDX_1 Fulld/Col 10Lnk/Act

LEDX_0 Speed Full duplex

84 SCOL Ipd/O Switch MII collision detect.

85 SCRS Ipd/O Switch MII carrier sense.

86 SCONF1 Ipd Dual MII configuration pin.

Pin (91, 86, 87): Switch MII PHY [5] MII

000 Disable, Otri Disable, Otri

001 PHY Mode MII Disable, Otri

010 MAC Mode MII Disable, Otri

011 PHY Mode SNI Disable, Otri

100 Disable Disable

101 PHY Mode MII PHY Mode MII

110 MAC Mode MII PHY Mode MII

111 PHY Mode SNI PHY Mode MII

87 SCONF0 Ipd Dual MII configuration pin.

88 GNDD Gnd Digital ground.

89 VDDC P 1.8V digital core VDD.

90 LED5-2 Ipu/O 5 LED indicator 2. Strap option: aging setup. See “Aging” section.

PU (default) = aging enable; PD = aging disable.

91 LED5-1 Ipu/O 5 LED indicator 1. Strap option: PU (default) = enable PHY MII I/F.

PD: tristate all PHY MII output. See “Pin 86 SCONF1.”

92 LED5-0 Ipu/O 5 LED indicator 0

93 LED4-2 Ipu/O 4 LED indicator 2

94 LED4-1 Ipu/O 4 LED indicator 1

95 LED4-0 Ipu/O 4 LED indicator 0

96 LED3-2 Ipu/O 3 LED indicator 2

97 LED3-1 Ipu/O 3 LED indicator 1

Note:

2. PU = Strap pin pull-up. Otri = Output tristated. PD = Strap pin pull-down. Fulld = Full duplex.

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KS8995MA Micrel, Inc.

Pin Number Pin Name Type

(1)

Port Pin Function

98 LED3-0 Ipu/O 3 LED indicator 0.

99 GNDD Gnd Digital ground.

100 VDDIO P 3.3V digital VDD for digital I/O.

101 LED2-2 Ipu/O 2 LED indicator 2.

102 LED2-1 Ipu/O 2 LED indicator 1.

103 LED2-0 Ipu/O 2 LED indicator 0.

104 LED1-2 Ipu/O 1 LED indicator 2.

105 LED1-1 Ipu/O 1 LED indicator 1.

106 LED1-0 Ipu/O 1 LED indicator 0.

107 MDC Ipu All Switch or PHY[5] MII management data clock.

108 MDIO I/O All Switch or PHY[5] MII management data I/O.

Features internal pull down to define pin state when not driven.

109 SPIQ Otri All (1) SPI serial data output in SPI slave mode; (2) not used in I2C master

mode. See “Pin 113.”

110 SPIC/SCL I/O All (1) Input clock up to 5MHz in SPI slave mode; (2) output clock at

81kHz in I2C master mode. See “Pin 113.”

111 SPID/SDA I/O All (1) Serial data input in SPI slave mode; (2) serial data input/output in

I2C master mode. See “Pin 113.”

112 SPIS_N Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N

is high, the KS8995MA is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) not used in I2C master mode.

113 PS1 Ipd Serial bus configuration pin.

For this case, if the EEPROM is not present, the KS8995MA will start itself with the PS[1:0] = 00 default register values .

Pin Configuration Serial Bus Configuration

PS[1:0]=00 I2C Master Mode for EEPROM

PS[1:0]=01 Reserved

PS[1:0]=10 SPI Slave Mode for CPU Interface

PS[1:0]=11 Factory Test Mode (BIST)

114 PS0 Ipd Serial bus configuration pin. See “Pin 113.”

115 RST_N Ipu Reset the KS8995MA. Active low.

116 GNDD Gnd Digital ground.

117 VDDC P 1.8V digital core VDD.

118 TESTEN Ipd NC for normal operation. Factory test pin.

Note:

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Pin Number Pin Name Type

(1)

Port Pin Function

119 SCANEN Ipd NC for normal operation. Factory test pin.

120 NC NC No connect.

121 X1 I 25MHz crystal clock connection/or 3.3V tolerant oscillator input.

Oscillator should be ±100ppm.

122 X2 O 25MHz crystal clock connection.

123 VDDAP P 1.8V analog VDD for PLL.

124 GNDA Gnd Analog ground.

125 VDDAR P 1.8V analog V

DD.

126 GNDA Gnd Analog ground.

127 GNDA Gnd Analog ground.

128 TEST2 NC NC for normal operation. Factory test pin.

Note:

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KS8995MA Micrel, Inc.

Pin Description (by Name)

Pin Number Pin Name Type

39 FXSD4 I 4 Fiber signal detect/factory test pin.

38 FXSD5 I 5 Fiber signal detect/factory test pin.

124 GNDA Gnd Analog ground.

42 GNDA Gnd Analog ground.

44 GNDA Gnd Analog ground.

2 GNDA Gnd Analog ground.

16 GNDA Gnd Analog ground.

30 GNDA Gnd Analog ground.

6 GNDA Gnd Analog ground.

12 GNDA Gnd Analog ground.

21 GNDA Gnd Analog ground.

27 GNDA Gnd Analog ground.

34 GNDA Gnd Analog ground.

40 GNDA Gnd Analog ground.

120 NC NC No connect.

127 GNDA Gnd Analog ground.

126 GNDA Gnd Analog ground.

49 GNDD Gnd Digital ground.

88 GNDD Gnd Digital ground.

116 GNDD Gnd Digital ground.

58 GNDD Gnd Digital ground.

76 GNDD Gnd Digital ground.

99 GNDD Gnd Digital ground.

17 ISET Set physical transmit output current. Pull-down with a 3.01kΩ 1%

106 LED1-0 Ipu/O 1 LED indicator 0.

105 LED1-1 Ipu/O 1 LED indicator 1.

104 LED1-2 Ipu/O 1 LED indicator 2.

103 LED2-0 Ipu/O 2 LED indicator 0.

102 LED2-1 Ipu/O 2 LED indicator 1.

101 LED2-2 Ipu/O 2 LED indicator 2.

98 LED3-0 Ipu/O 3 LED indicator 0.

(1)

Port Pin Function

resistor.

Note:

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Pin Number Pin Name Type

(1)

Port Pin Function

(2)

97 LED3-1 Ipu/O 3 LED indicator 1.

96 LED3-2 Ipu/O 3 LED indicator 2.

95 LED4-0 Ipu/O 4 LED indicator 0.

94 LED4-1 Ipu/O 4 LED indicator 1.

93 LED4-2 Ipu/O 4 LED indicator 2.

92 LED5-0 Ipu/O 5 LED indicator 0.

91 LED5-1 Ipu/O 5 LED indicator 1. Strap option: PU (default) = enable PHY MII I/F

PD: tristate all PHY MII output. See “Pin 86 SCONF1.”

90 LED5-2 Ipu/O 5 LED indicator 2. Strap option: aging setup. See “Aging” section.

(default) = aging enable; PD = aging disable.

107 MDC Ipu All Switch or PHY[5] MII management data clock.

108 MDIO I/O All Switch or PHY[5] MII management data I/O.

1 MDI-XDIS Ipd 1-5 Disable auto MDI/MDI-X.

45 MUX1 NC Factory test pins. MUX1 and MUX2 should be left unconnected for

46 MUX2 NC normal operation.

Mode MUX1 MUX2

Normal Operation NC NC

68 PCOL Ipd/O 5 PHY[5] MII collision detect/force flow control. See “Register 18.”

For port 4 only. PD (default) = no force flow control. PU = force flow control.

67 PCRS Ipd/O 5 PHY[5] MII carrier sense/force duplex mode. See “Register 28.”

For port 4 only. PD (default) = force half-duplex if auto-negotiation is disabled or fails. PU = force full-duplex if auto-negotiation is disabled or fails.

60 PMRXC O 5 PHY[5] MII receive clock. PHY mode MII.

65 PMRXD0 Ipd/O 5 PHY[5] MII receive bit 0. Strap option: PD (default) = disable

aggressive back-off algorithm in half-duplex mode; PU = enable for performance enhancement.

64 PMRXD1 Ipd/O 5 PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive

collision packets; PU = does not drop excessive collision packets.

63 PMRXD2 Ipd/O 5 PHY[5] MII receive bit 2. Strap option: PD (default) = disable back

pressure; PU = enable back pressure.

62 PMRXD3 Ipd/O 5 PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow

control; PU = disable flow control.

61 PMRXDV Ipd/O 5 PHY[5] MII receive data valid.

66 PMRXER Ipd/O 5 PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;

PU = packet size up to 1536 bytes.

Note:

2. PU = Strap pin pull-up. PD = Strap pin pull-down.

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Pin Number Pin Name Type

(1)

Port Pin Function

57 PMTXC O 5 PHY[5] MII transmit clock. PHY mode MII.

55 PMTXD0 Ipd 5 PHY[5] MII transmit bit 0.

54 PMTXD1 Ipd 5 PHY[5] MII transmit bit 1.

53 PMTXD2 Ipd 5 PHY[5] MII transmit bit 2.

52 PMTXD3 Ipd 5 PHY[5] MII transmit bit 3.

51 PMTXEN Ipd 5 PHY[5] MII transmit enable.

56 PMTXER Ipd 5 PHY[5] MII transmit error.

114 PS0 Ipd Serial bus configuration pin. See “Pin 113.”

113 PS1 Ipd Serial bus configuration pin.

If EEPROM is not present, the KS8995MA will start itself with chip default (00)...

Pin Configuration Serial Bus Configuration

PS[1:0]=00 I2C Master Mode for EEPROM

PS[1:0]=01 Reserved

PS[1:0]=10 SPI Slave Mode for CPU Interface

PS[1:0]=11 Factory Test Mode (BIST)

47 PWRDN_N Ipu Full-chip power down. Active low.

48 RESERVE NC Reserved pin. No connect.

115 RST_N Ipu Reset the KS8995MA. Active low.

5 RXM1 I 1 Physical receive signal – (differential).

11 RXM2 I 2 Physical receive signal – (differential).

20 RXM3 I 3 Physical receive signal – (differential).

26 RXM4 I 4 Physical receive signal – (differential).

33 RXM5 I 5 Physical receive signal – (differential).

4 RXP1 I 1 Physical receive signal + (differential).

10 RXP2 I 2 Physical receive signal + (differential).

19 RXP3 I 3 Physical receive signal + (differential).

25 RXP4 I 4 Physical receive signal + (differential).

32 RXP5 I 5 Physical receive signal + (differential).

119 SCANEN Ipd NC for normal operation. Factory test pin.

84 SCOL Ipd/O Switch MII collision detect.

87 SCONF0 Ipd Dual MII configuration pin.

Note:

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Pin Number Pin Name Type

(1)

Port Pin Function

(2)

86 SCONF1 Ipd Dual MII configuration pin.

Pin (91, 86, 87): Switch MII PHY [5] MII

000 Disable, Otri Disable, Otri

001 PHY Mode MII Disable, Otri

010 MAC Mode MII Disable, Otri

011 PHY Mode SNI Disable, Otri

100 Disable Disable

101 PHY Mode MII PHY Mode MII

110 MAC Mode MII PHY Mode MII

111 PHY Mode SNI PHY Mode MII

85 SCRS Ipd/O Switch MII carrier sense.

78 SMRXC I/O Switch MII receive clock. Input in MAC mode, output in PHY mode MII.

83 SMRXD0 Ipd/O Switch MII receive bit 0; strap option: LED mode

PD (default) = mode 0; PU = mode 1. See “Register 11.”

Mode 0 Mode 1

LEDX_2 Lnk/Act 100Lnk/Act

LEDX_1 Fulld/Col 10Lnk/Act

LEDX_0 Speed Full duplex

82 SMRXD1 Ipd/O Switch MII receive bit 1. Strap option: PD (default) = switch MII in

100Mbps mode; PU = switch MII in 10Mbps mode.

81 SMRXD2 Ipd/O Switch MII receive bit 2. Strap option: PD (default) = switch MII in

full-duplex mode; PU = switch MII in half-duplex mode.

80 SMRXD3 Ipd/O Switch MII receive bit 3. Strap option: PD (default) = disable switch

MII full-duplex flow control; PU = enable switch MII full-duplex flow control.

79 SMRXDV Ipd/O Switch MII receive data valid.

75 SMTXC I/O Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.

73 SMTXD0 Ipd Switch MII transmit bit 0.

72 SMTXD1 Ipd Switch MII transmit bit 1.

71 SMTXD2 Ipd Switch MII transmit bit 2.

70 SMTXD3 Ipd Switch MII transmit bit 3.

69 SMTXEN Ipd Switch MII transmit enable.

74 SMTXER Ipd Switch MII transmit error.

Note:

2. PU = Strap pin pull-up. PD = Strap pin pull-down. Fulld = Full duplex.

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Pin Number Pin Name Type

(1)

Port Pin Function

110 SPIC/SCL I/O All (1) Input clock up to 5MHz in SPI slave mode; (2) Output clock at 81kHz

in I2C master mode. See “Pin 113.”

111 SPID/SDA I/O All (1) Serial data input in SPI slave mode; (2) Serial data input/output in

I2C master mode. See “Pin 113.”

109 SPIQ Otri All (1) SPI serial data output in SPI slave mode; (2) Not used in I

C master

mode. See “Pin 113.”

112 SPIS_N Ipu All Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N

is high, the KS8995MA is deselected and SPIQ is held in high impedance state, a high-to-low transition to initiate the SPI data transfer; (2) Not used in I2C master mode.

128 TEST2 NC No connect for normal operation. Factory test pin.

118 TESTEN Ipd No connect for normal operation. Factory test pin.

8 TXM1 O 1 Physical transmit signal – (differential).

14 TXM2 O 2 Physical transmit signal – (differential).

23 TXM3 O 3 Physical transmit signal – (differential).

29 TXM4 O 4 Physical transmit signal – (differential).

36 TXM5 O 5 Physical transmit signal – (differential).

7 TXP1 O 1 Physical transmit signal + (differential).

13 TXP2 O 2 Physical transmit signal + (differential).

22 TXP3 O 3 Physical transmit signal + (differential).

28 TXP4 O 4 Physical transmit signal + (differential).

35 TXP5 O 5 Physical transmit signal + (differential).

123 VDDAP P 1.8V analog VDD for PLL.

41 VDDAR P 1.8V analog VDD.

43 VDDAR P 1.8V analog VDD.

3 VDDAR P 1.8V analog VDD.

15 VDDAR P 1.8V analog VDD.

31 VDDAR P 1.8V analog VDD.

125 VDDAR P 1.8V analog VDD.

18 VDDAT P 2.5V or 3.3V analog VDD.

9 VDDAT P 2.5V or 3.3V analog VDD.

24 VDDAT P 2.5V or 3.3V analog VDD.

37 VDDAT P 2.5V or 3.3V analog VDD.

50 VDDC P 1.8V digital core VDD.

Note:

NC = No connect.

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Pin Number Pin Name Type

(1)

Port Pin Function

89 VDDC P 1.8V digital core VDD.

117 VDDC P 1.8V digital core VDD.

59 VDDIO P 3.3V digital VDD for digital I/O circuitry.

77 VDDIO P 3.3V digital VDD for digital I/O circuitry.

100 VDDIO P 3.3V digital VDD for digital I/O circuitry.

121 X1 I 25MHz crystal clock connection/or 3.3V tolerant oscillator input.

Oscillator should be ±100ppm.

122 X2 O 25MHz crystal clock connection.

Note:

1. P = Power supply. I = Input.

O = Output.

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KS8995MA Micrel, Inc.

Pin Configuration

LED2-1

LED2-2

VDDIO

GNDD

LED3-0

LED3-1

LED3-2

LED4-0

LED4-1

LED4-2

LED5-0

LED5-1

LED5-2

VDDC

GNDD

SCONF0

SCONF1

SCRS

SCOL

SMRXD0

SMRXD1

SMRXD2

SMRXD3

SMRXDV

SMRXC

VDDIO

GNDD

SMTXC

SMTXER

SMTXD0

SMTXD1

SMTXD2

SMTXD3

SMTEXN

PCOL

PCRS

PMRXER

PMRXD0

LED2-0 LED1-2 LED1-1 LED1-0

MDC

MDIO

SPIQ SPIC/SCL SPID/SDA

SPIS_N

PS1 PS0

RST_N

GNDD

VDDC

TESTEN

SCANEN

X1 X2

VDDAP

GNDA

VDDAR

GNDA GNDA

TEST2

103

MDIXDIS

TXP1

RXP1

GNDA

VDDAR

RXM1

GNDA

TXM1

VDDAT

RXP2

RXM2

GNDA

TXP2

TXM2

VDDAR

GNDA

ISET

VDDAT

RXP3

RXM3

GNDA

TXP3

TXM3

VDDAT

RXP4

RXM4

GNDA

TXP4

TXM4

TXP5

RXP5

GNDA

VDDAR

RXM5

GNDA

TXM5

VDDAT

FXSD5

PMRXD1 PMRXD2 PMRXD3 PMRXDV PMRXC VDDIO GNDD PMTXC PMTXER PMTXD0 PMTXD1 PMTXD2 PMTXD3 PMTXEN VDDC GNDD RESERVE PWRDN_N MUX2 MUX1 GNDA VDDAR GNDA VDDAR GNDA FXSD4

128-Pin PQFP (PQ)

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Introduction

The KS8995MA contains five 10/100 physical layer transceivers and five media access control (MAC) units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this mode, access to the fifth MAC is provided through a media independent interface (MII) . This is useful for implementing an integrated broadband router. The third mode uses the dual MII feature to recover the use of the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed through the MII-P5 port.

The KS8995MA has the flexibility to reside in a managed or unmanaged design. In a managed design, a host processor has complete control of the KS8995MA via the SPI bus, or partial control via the MDC/MDIO interface. An unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.

On the media side, the KS8995MA supports IEEE 802.3 10BASE-T, 100BASE-TX on all ports, and 100BASE-FX on ports 4 and 5. The KS8995MA can be used as two separate media converters.

Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the design more efficient and allows for lower power consumption and smaller chip die size.

The major enhancements from the KS8995E to the KS8995MA are support for host processor management, a dual MII interface, tag as well as port based VLAN, spanning tree protocol support, IGMP snooping support, port mirroring support and rate limiting functionality.

Functional Overview: Physical Layer Transceiver

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01kΩ resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as temperature variations.

The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.

PLL Clock Synthesizer

The KS8995MA generates 125MHz, 42MHz, 25MHz, and 10MHz clocks for system timing. Internal clocks are generated from an external 25MHz crystal or oscillator.

Scrambler/De-scrambler (100BASE-TX only)

The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-bit nonrepetitive sequence. The receiver will then de-scramble the incoming data stream with the same sequence at the transmitter.

100BASE-FX Operation

100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/de-scrambler and MLT3 encoder/ decoder are bypassed on transmission and reception. In this mode the auto-negotiation feature is bypassed since there is no standard that supports fiber auto-negotiation.

100BASE-FX Signal Detection

The physical port runs in 100BASE-FX mode if FXSDx >0.6V for ports 4 and 5 only. This signal is internally referenced to 1.25V. The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is above this 1.25V reference, indicating signal

M9999-051305 22 May 2005

+ 51 hidden pages

Micrel KS8995MA User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual