Mesa 7I43, 7I43H User Manual
7I43/7I43H MANUAL
V3.0
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iii
Table of Contents
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
HARDWARE CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
FPGA CONFIGURATION SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
USB POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
POWER ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
CONNECTOR POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
BUS SWITCH MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PRE-CONFIGURATION PULL-UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS . . . . . . . . 4
I/O CONNECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
JTAG CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
POWER CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EPP INTERFACE CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EPP CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
USB CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EEPROM CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EXTRA EEPROM SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RECONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CONFIGURATION FILE STARTUP OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 13
SC7I43P and SC7I43W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
EPP-FPGA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
USB-FPGA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ADDITIONAL 7I43H INTERFACE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
BUS SWITCH MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I/O LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STARTUP I/O STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DRIVING 5V REFERRED LOADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TERMINATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
iv
Table of Contents
SUPPLIED CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EPPIOPR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
USBIOPR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LBP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EXAMPLE COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LOCAL LBP COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LOCAL LBP READ COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LOCAL LBP WRITE COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RPC COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EXAMPLE RPC COMMAND LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AVAILABLE DAUGHTER CARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REFERENCE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7I43 1
GENERAL
DESCRIPTION
The 7I43 is a USB/EPP version of the FPGA based Anything I/O card series. It
provides 48 programmable I/O bits The 7I43H variant is a high speed USB version.
Initial FPGA configurations can be downloaded to the 7I43 via the USB (7I43 and
7I43H) or EPP (7I43 only) port. The 7I43/7I43H also has a serial EEPROM for FPGA
configuration storage when the 7I43/7I43H is used in stand-alone applications.
The 48 I/O bits are available on two 50 pin connectors, 24 bits per connector. The
50 pin connectors have I/O module rack compatible pin-outs. The connector pin-out uses
interleaved grounds for lower crosstalk and controlled impedance.
/Done, /Init and power status LEDs are provided for debugging puposes as are 8
FPGA driven LEDs. Several I/O interface daughter cards are available for the 7I43/7I43H.
These cards include a 4 axis 3A Hbridge, a 2 Axis 3A stepper motor driver, an analog
servo amp. interface, an RS-422/485 interface, and a debug LED card. One daughter card
can plug directly onto the 7I43/7I43H.
Many IO configuration files are provided with the 7I43/7I43H including simple
remote I/O, 4 and 8 axis servo motion control, 4 and 8 axis microstepping stepper motor
control, multiple channel PWM generator, quadrature counters and more. VHDL source
is provided for all configurations.
FPGA system clock is 50MHZ Oscillator. The Spartan3 used can multiply or divide
this frequency to suitable values for application use.
The 7I43 uses a 200K or 400K gate Xilinx SpartanIII FPGA, and the 7I43H uses
a 400K SpartanIII FPGA. Free development tools for the SpartanIII are available (Xilinx
WebPack) from Xilinx’s web site.
7I43 2
HARDWARE CONFIGURATION
GENERAL
Hardware setup jumper positions assume that the 7I43 or 7I43H card is oriented in
an upright position, that is, with the USB connector towards the person doing the
configuration, and the power connector on top right. In the following, "7I43" refers to both
the 7I43 and the 7I43H.
FPGA CONFIGURATION SOURCE
The 7I43's FPGA can be configured via the USB port, The EPP port, or the on card
serial EEPROM. Jumpers W4 and W5 select the configuration source. The 7I43H does
not have the EPP configuration option.
W4 W5 MODE
DOWN DOWN EPP (PARALLEL PORT) CONFIG
DOWN UP USB CONFIG
UP DOWN EEPROM CONFIG
USB POWER
The 7I43 can be powered by the USB host. The maximum power that can be
supplied by a USB host is 450 mA. This will be sufficient for most but not all 7I43
applications. For applications that require more than the 450 mA supplied by the host, the
7I43 has provisions for external power. W6 connects host USB power to the 7I43's power
supplies. To use host power, W6 must be set to the "UP" position. If external 5Vpower is
used, W6 must be set to the "DOWN" position.
WARNING: Connecting an external 5V supply to the 7I43 while W6 is in the "UP"
position and a USB cable connects the 7I43 to a host computer is likely to damage
the computer by feeding external power ‘backwards’ into the USB port!
POWER ENABLE
The 7I43 can be set to power-up only after the USB interface is activated. This is
the suggested operational mode when the 7I43 is interfaced via USB. For applications
where the 7I43 must operate without the USB interface, This function must be disabled.
W7 controls the power up enable mode. When W7 is in the "UP" position, the 7I43 power
supplies are always enabled. When W7 is in the "DOWN" position, the 7I43 power
supplies will only be enabled when the USB interface is active.
7I43 3
HARDWARE CONFIGURATION
CONNECTOR POWER
The power connection on both I/O connectors (Pin 49) can supply either 3.3V or
5V power. Supplied power should be limited to 400 mA total. W1 selects the power
supplied to both P3 and P4 . When W1 is in the "UP" position, 5V power is supplied to the
connector. When W1 is in the "DOWN" position, 3.3V power is supplied to P3 and P4.
Note that most Mesa I/O adapter cards that connect to Anything I/O cards require 5V.
BUS SWITCH MODE
Jumper W2 determines bus switch mode for all user I/O pins. When jumper W2 is
in the "UP" position, 5V tolerant mode is selected, when ‘down’, 3.3V mode is selected.
Note that 3.3V mode is not 5V tolerant. The FPGA can be damaged by input voltages
greater than 4V in 3.3V mode.
PRE-CONFIGURATION PULL-UPS
The 7I43 has no pull-up resistors on its user I/O pins. This means that before these
pins are configured, they will not have a defined state. If this is not desired, internal pull-up
resistors on all FPGA pins can be enabled via Jumper W3. When W3 is in the "DOWN"
position, user I/O will float until the FPGA is configured. When W3 is in the "UP" position,
all FPGA pins including user I/O pins will have a pull-up resistor to 3.3V so the pins will be
in a "HIGH" state. It is suggested that the internal pull-ups be enabled unless this causes
a problem with connected I/O devices. Note that once the FPGA is configured, each FPGA
input pin can have programmable pull-up or pull-down resistors.
7I43 4
CONNECTORS
CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS
7I43-U shown -P version has different defaults
7I43 5
CONNECTORS
7I43H CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS
7I43 6
CONNECTORS
I/O CONNECTORS
P3 and P4 are the 7I43s I/O connectors. These are 50 pin box headers that mate
with standard 50 conductor female IDC connectors. For information on which I/O pin
connects to which FPGA pin, please see the 7I43IO.PIN file on the 7I43 distribution disk.
7I43 IO connector pinouts are as follows:
P4 CONNECTOR PINOUT
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
1 IO0 2 GND 3 IO1 4 GND
5 IO2 6 GND 7 IO3 8 GND
9 IO4 10 GND 11 IO5 12 GND
13 IO6 14 GND 15 IO7 16 GND
17 IO8 18 GND 19 IO9 20 GND
21 IO10 22 GND 23 IO11 24 GND
25 IO12 26 GND 27 IO13 28 GND
29 IO14 30 GND 31 IO15 32 GND
33 IO16 34 GND 35 IO17 36 GND
37 IO18 38 GND 39 IO19 40 GND
41 IO20 42 GND 43 IO21 44 GND
45 IO22 46 GND 47 IO23 48 GND
49 POWER 50 GND
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