Mentor FastScan and FlexTest User Manual

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FastScan and FlexTest

Reference Manual

Software Version V8.6_4

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TABLE OF CONTENTS

About This Manual .............................................................................................xvii

Overview.............................................................................................................xvii

Related Publications ............................................................................................xix

Mentor Graphics Documentation......................................................................xix

Acronyms Used in This Manual..........................................................................xxi

Command Line Syntax Conventions................................................................ xxiii

Chapter 1

Introduction......................................................................................................... 1-1

Features............................................................................................................... 1-1

Inputs and Outputs.............................................................................................. 1-2

Chapter 2

Command Dictionary.......................................................................................... 2-1

Command Summary........................................................................................... 2-1

Command Descriptions .................................................................................... 2-27

Abort Interrupted Process .............................................................................. 2-28

Add Ambiguous Paths.................................................................................... 2-29

Add Atpg Constraints..................................................................................... 2-31

Add Atpg Functions....................................................................................... 2-36

Add Capture Handling ................................................................................... 2-40

Add Cell Constraints...................................................................................... 2-43

Add Cell Library ............................................................................................ 2-46

Add Clocks..................................................................................................... 2-47

Add Cone Blocks ........................................................................................... 2-49

Add Control Points......................................................................................... 2-51

Add Display Instances.................................................................................... 2-53

Add Display Loop.......................................................................................... 2-57

Add Display Path ........................................................................................... 2-60

Add Display Scanpath.................................................................................... 2-63

Add Faults...................................................................................................... 2-66

Add Iddq Constraints ..................................................................................... 2-68

Add Initial States............................................................................................ 2-70

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TABLE OF CONTENTS [continued]

Add LFSR Connections ................................................................................. 2-72

Add LFSR Taps.............................................................................................. 2-74

Add LFSRs..................................................................................................... 2-76

Add Lists........................................................................................................ 2-79

Add Mos Direction......................................................................................... 2-81

Add Net Property ........................................................................................... 2-83

Add Nofaults.................................................................................................. 2-84

Add Nonscan Handling.................................................................................. 2-87

Add Notest Points .......................................................................................... 2-89

Add Observe Points........................................................................................ 2-90

Add Output Masks ......................................................................................... 2-92

Add Pin Constraints ....................................................................................... 2-93

Add Pin Equivalences .................................................................................... 2-98

Add Pin Strobes............................................................................................ 2-101

Add Primary Inputs...................................................................................... 2-103

Add Primary Outputs ................................................................................... 2-105

Add Random Weights.................................................................................. 2-106

Add Read Controls....................................................................................... 2-108

Add Scan Chains.......................................................................................... 2-110

Add Scan Groups ......................................................................................... 2-112

Add Scan Instances ...................................................................................... 2-114

Add Scan Models......................................................................................... 2-115

Add Slow Pad............................................................................................... 2-116

Add Tied Signals.......................................................................................... 2-117

Add Write Controls...................................................................................... 2-119

Analyze Atpg Constraints ............................................................................ 2-120

Analyze Bus ................................................................................................. 2-123

Analyze Control ........................................................................................... 2-126

Analyze Control Signals .............................................................................. 2-128

Analyze Drc Violation ................................................................................. 2-131

Analyze Fault ............................................................................................... 2-137

Analyze Observe.......................................................................................... 2-143

Analyze Race ............................................................................................... 2-145

Analyze Restrictions .................................................................................... 2-147

Close Schematic Viewer .............................................................................. 2-148

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TABLE OF CONTENTS [continued]

Compress Patterns........................................................................................ 2-149

Create Initialization Patterns........................................................................ 2-152

Create Patterns ............................................................................................. 2-154

Delete Atpg Constraints............................................................................... 2-156

Delete Atpg Functions.................................................................................. 2-158

Delete Capture Handling.............................................................................. 2-160

Delete Cell Constraints ................................................................................ 2-162

Delete Clocks ............................................................................................... 2-164

Delete Cone Blocks...................................................................................... 2-165

Delete Control Points................................................................................... 2-167

Delete Display Instances.............................................................................. 2-169

Delete Faults................................................................................................. 2-171

Delete Iddq Constraints................................................................................ 2-174

Delete Initial States ...................................................................................... 2-176

Delete LFSR Connections............................................................................ 2-177

Delete LFSR Taps........................................................................................ 2-179

Delete LFSRs............................................................................................... 2-181

Delete Lists................................................................................................... 2-183

Delete Mos Direction................................................................................... 2-184

Delete Net Property...................................................................................... 2-185

Delete Nofaults............................................................................................. 2-186

Delete Nonscan Handling ............................................................................ 2-189

Delete Notest Points..................................................................................... 2-191

Delete Observe Points.................................................................................. 2-193

Delete Output Masks.................................................................................... 2-195

Delete Paths.................................................................................................. 2-197

Delete Pin Constraints.................................................................................. 2-199

Delete Pin Equivalences............................................................................... 2-201

Delete Pin Strobes........................................................................................ 2-202

Delete Primary Inputs .................................................................................. 2-204

Delete Primary Outputs................................................................................ 2-206

Delete Random Weights .............................................................................. 2-208

Delete Read Controls ................................................................................... 2-210

Delete Scan Chains ...................................................................................... 2-211

Delete Scan Groups...................................................................................... 2-212

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TABLE OF CONTENTS [continued]

Delete Scan Instances................................................................................... 2-214

Delete Scan Models...................................................................................... 2-215

Delete Slow Pad........................................................................................... 2-216

Delete Tied Signals ...................................................................................... 2-217

Delete Write Controls .................................................................................. 2-219

Diagnose Failures......................................................................................... 2-220

Dofile............................................................................................................ 2-224

Exit............................................................................................................... 2-226

Extract Subckts............................................................................................. 2-227

Flatten Model............................................................................................... 2-228

Flatten Subckt............................................................................................... 2-229

Help.............................................................................................................. 2-230

Insert Testability........................................................................................... 2-232

Load Faults................................................................................................... 2-234

Load Paths.................................................................................................... 2-238

Macrotest...................................................................................................... 2-242

Mark............................................................................................................. 2-248

Open Schematic Viewer............................................................................... 2-250

Read Modelfile............................................................................................. 2-252

Read Procfile................................................................................................ 2-255

Read Subckts Library................................................................................... 2-256

Redo Display................................................................................................ 2-257

Report Aborted Faults.................................................................................. 2-259

Report Atpg Constraints............................................................................... 2-262

Report Atpg Functions................................................................................. 2-263

Report AU Faults ......................................................................................... 2-264

Report Bus Data........................................................................................... 2-268

Report Capture Handling ............................................................................. 2-272

Report Cell Constraints................................................................................ 2-274

Report Clocks............................................................................................... 2-276

Report Cone Blocks ..................................................................................... 2-277

Report Control Data..................................................................................... 2-278

Report Control Points................................................................................... 2-280

Report Core Memory ................................................................................... 2-281

Report Display Instances.............................................................................. 2-282

FastScan and FlexTest Reference Manual, V8.6_4

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TABLE OF CONTENTS [continued]

Report Drc Rules.......................................................................................... 2-285

Report Environment..................................................................................... 2-293

Report Failures............................................................................................. 2-295

Report Faults................................................................................................ 2-298

Report Feedback Paths................................................................................. 2-303

Report Flatten Rules..................................................................................... 2-305

Report Gates................................................................................................. 2-309

Report Hosts................................................................................................. 2-326

Report Id Stamp ........................................................................................... 2-327

Report Iddq Constraints ............................................................................... 2-329

Report Initial States...................................................................................... 2-331

Report LFSR Connections ........................................................................... 2-333

Report LFSRs............................................................................................... 2-334

Report Lists.................................................................................................. 2-335

Report Loops................................................................................................ 2-336

Report Mos Direction................................................................................... 2-337

Report Net Properties................................................................................... 2-338

Report Nofaults............................................................................................ 2-339

Report Nonscan Cells................................................................................... 2-341

Report Nonscan Handling............................................................................ 2-345

Report Notest Points .................................................................................... 2-346

Report Observe Data.................................................................................... 2-347

Report Observe Points.................................................................................. 2-349

Report Output Masks ................................................................................... 2-350

Report Paths................................................................................................. 2-351

Report Pin Constraints ................................................................................. 2-353

Report Pin Equivalences .............................................................................. 2-355

Report Pin Strobes........................................................................................ 2-356

Report Primary Inputs.................................................................................. 2-357

Report Primary Outputs ............................................................................... 2-359

Report Procedure.......................................................................................... 2-361

Report Pulse Generators............................................................................... 2-362

Report Random Weights.............................................................................. 2-363

Report Read Controls................................................................................... 2-364

Report Scan Cells......................................................................................... 2-365

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TABLE OF CONTENTS [continued]

Report Scan Chains...................................................................................... 2-368

Report Scan Groups ..................................................................................... 2-369

Report Scan Instances .................................................................................. 2-370

Report Scan Models..................................................................................... 2-371

Report Seq_transparent Procedures ............................................................. 2-372

Report Slow Pads......................................................................................... 2-374

Report Statistics ........................................................................................... 2-375

Report Test Stimulus.................................................................................... 2-380

Report Testability Data ................................................................................ 2-386

Report Tied Signals...................................................................................... 2-389

Report Timeplate.......................................................................................... 2-391

Report Version Data..................................................................................... 2-392

Report Write Controls.................................................................................. 2-393

Reset Au Faults............................................................................................ 2-394

Reset State.................................................................................................... 2-396

Resume Interrupted Process......................................................................... 2-397

Run............................................................................................................... 2-399

Save Flattened Model................................................................................... 2-403

Save Patterns................................................................................................ 2-405

Save Schematic ............................................................................................ 2-416

Select Iddq Patterns...................................................................................... 2-417

Select Object ................................................................................................ 2-422

Set Abort Limit ............................................................................................ 2-424

Set Atpg Compression.................................................................................. 2-427

Set Atpg Limits............................................................................................ 2-430

Set Atpg Window......................................................................................... 2-433

Set AU Analysis........................................................................................... 2-434

Set Bist Initialization.................................................................................... 2-436

Set Bus Handling.......................................................................................... 2-438

Set Bus Simulation....................................................................................... 2-440

Set Capture Clock ........................................................................................ 2-441

Set Capture Handling................................................................................... 2-444

Set Capture Limit......................................................................................... 2-447

Set Checkpoint............................................................................................. 2-449

Set Clock Restriction.................................................................................... 2-451

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TABLE OF CONTENTS [continued]

Set Clock_off Simulation............................................................................. 2-454

Set Clockpo Patterns.................................................................................... 2-455

Set Contention Check................................................................................... 2-456

Set Control Threshold.................................................................................. 2-461

Set Decision Order....................................................................................... 2-462

Set Dofile Abort........................................................................................... 2-464

Set Drc Handling.......................................................................................... 2-465

Set Driver Restriction................................................................................... 2-475

Set Fails Report............................................................................................ 2-477

Set Fault Mode............................................................................................. 2-478

Set Fault Sampling....................................................................................... 2-480

Set Fault Type.............................................................................................. 2-482

Set Flatten Handling..................................................................................... 2-484

Set Gate Level.............................................................................................. 2-489

Set Gate Report ............................................................................................ 2-491

Set Hypertrophic Limit ................................................................................ 2-500

Set Iddq Checks............................................................................................ 2-502

Set Iddq Strobe............................................................................................. 2-506

Set Instancename Visibility.......................................................................... 2-508

Set Instruction Atpg ..................................................................................... 2-511

Set Internal Fault.......................................................................................... 2-513

Set Internal Name......................................................................................... 2-514

Set Interrupt Handling.................................................................................. 2-515

Set IO Mask.................................................................................................. 2-517

Set Learn Report .......................................................................................... 2-518

Set List File.................................................................................................. 2-520

Set Logfile Handling.................................................................................... 2-522

Set Loop Handling ....................................................................................... 2-524

Set Multiple Load......................................................................................... 2-527

Set Net Dominance ...................................................................................... 2-529

Set Net Resolution........................................................................................ 2-531

Set Nonscan Model ...................................................................................... 2-533

Set Number Shifts........................................................................................ 2-536

Set Observation Point................................................................................... 2-537

Set Observe Threshold................................................................................. 2-539

FastScan and FlexTest Reference Manual, V8.6_4

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TABLE OF CONTENTS [continued]

Set Output Comparison................................................................................ 2-541

Set Output Mask........................................................................................... 2-543

Set Pathdelay Holdpi.................................................................................... 2-545

Set Pattern Source ........................................................................................ 2-546

Set Possible Credit ....................................................................................... 2-550

Set Procedure Cycle_checking..................................................................... 2-551

Set Pulse Generators .................................................................................... 2-552

Set Race Data............................................................................................... 2-553

Set Rail Strength .......................................................................................... 2-554

Set Ram Initialization................................................................................... 2-555

Set Ram Test................................................................................................ 2-557

Set Random Atpg......................................................................................... 2-559

Set Random Clocks...................................................................................... 2-560

Set Random Patterns.................................................................................... 2-562

Set Random Weights.................................................................................... 2-563

Set Redundancy Identification..................................................................... 2-565

Set Schematic Display.................................................................................. 2-566

Set Screen Display ....................................................................................... 2-569

Set Self Initialization.................................................................................... 2-570

Set Sensitization Checking........................................................................... 2-572

Set Sequential Learning ............................................................................... 2-573

Set Shadow Check........................................................................................ 2-575

Set Simulation Mode.................................................................................... 2-576

Set Skewed Load.......................................................................................... 2-581

Set Split Capture_cycle................................................................................ 2-583

Set Stability Check....................................................................................... 2-584

Set Static Learning....................................................................................... 2-586

Set Stg Extraction......................................................................................... 2-588

Set System Mode.......................................................................................... 2-589

Set Test Cycle .............................................................................................. 2-592

Set Trace Report........................................................................................... 2-593

Set Transition Holdpi................................................................................... 2-594

Set Unused Net............................................................................................. 2-595

Set Workspace Size...................................................................................... 2-597

Set Xclock Handling .................................................................................... 2-598

FastScan and FlexTest Reference Manual, V8.6_4

Table of Contents

TABLE OF CONTENTS [continued]

Set Z Handling ............................................................................................. 2-599

Set Zhold Behavior ...................................................................................... 2-601

Set Zoom Factor........................................................................................... 2-603

Setup Checkpoint......................................................................................... 2-604

Setup LFSRs................................................................................................. 2-607

Setup Pin Constraints................................................................................... 2-609

Setup Pin Strobes ......................................................................................... 2-612

Setup Tied Signals........................................................................................ 2-613

Step............................................................................................................... 2-615

System.......................................................................................................... 2-616

Undo Display ............................................................................................... 2-617

Unmark......................................................................................................... 2-619

Unselect Object............................................................................................ 2-621

Update Implication Detections..................................................................... 2-623

View............................................................................................................. 2-625

View Area .................................................................................................... 2-627

Write Core Memory..................................................................................... 2-629

Write Environment....................................................................................... 2-631

Write Failures............................................................................................... 2-634

Write Faults.................................................................................................. 2-638

Write Initial States........................................................................................ 2-642

Write Library_verification Setup................................................................. 2-644

Write Loops.................................................................................................. 2-646

Write Modelfile............................................................................................ 2-647

Write Netlist................................................................................................. 2-649

Write Paths................................................................................................... 2-651

Write Primary Inputs.................................................................................... 2-653

Write Primary Outputs................................................................................. 2-655

Write Procfile............................................................................................... 2-657

Write Statistics............................................................................................. 2-658

Write Timeplate ........................................................................................... 2-661

Zoom In........................................................................................................ 2-663

Zoom Out..................................................................................................... 2-664

FastScan and FlexTest Reference Manual, V8.6_4

Table of Contents

TABLE OF CONTENTS [continued]

Chapter 3

Shell Commands.................................................................................................. 3-1

Shell Command Descriptions ............................................................................. 3-1

fastscan............................................................................................................. 3-2

flextest.............................................................................................................. 3-7

Chapter 4

Test Pattern File Formats ................................................................................... 4-1

FastScan Test Pattern File Format...................................................................... 4-1

Header_Data..................................................................................................... 4-1

Setup_Data....................................................................................................... 4-2

Functional_Chain_Test.................................................................................... 4-5

Scan_Test......................................................................................................... 4-8

Scan_Cell ....................................................................................................... 4-11

FlexTest Test Pattern File Format .................................................................... 4-12

ASCII Pattern Format .................................................................................... 4-12

Table Pattern Format...................................................................................... 4-20

VCD Support Using VCD Plus...................................................................... 4-27

Chapter 5

Distributed FlexTest............................................................................................ 5-1

Environment Setup........................................................................................... 5-4

Host File Setup................................................................................................. 5-4

Appendix A

Timing Command Dictionary............................................................................A-1

Timing Command Summary ..............................................................................A-1

FastScan Timing Commands..............................................................................A-3

SET END_MEASURE_CYCLE TIME ..........................................................A-4

SET PROCEDURE FILE ................................................................................A-8

SET SINGLE_CYCLE TIME........................................................................A-10

SET SPLIT_BIDI_CYCLE TIME.................................................................A-12

SET SPLIT_MEASURE_CYCLE TIME......................................................A-15

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TABLE OF CONTENTS [continued]

SET STROBE_WINDOW TIME..................................................................A-20

SET TIME SCALE........................................................................................A-22

TIMEPLATE..................................................................................................A-23

FlexTest Timing Commands ............................................................................A-32

SET BIDI_FORCE TIME..............................................................................A-33

SET CYCLE...................................................................................................A-35

SET END_MEASURE_CYCLE TIME ........................................................A-38

SET FIRST_FORCE TIME...........................................................................A-41

SET FORCE TIME........................................................................................A-42

SET MEASURE TIME..................................................................................A-45

SET PROCEDURE FILE ..............................................................................A-47

SET SINGLE_CYCLE TIME........................................................................A-49

SET SKEW_FORCE TIME...........................................................................A-52

SET SPLIT_BIDI_CYCLE TIME.................................................................A-54

SET SPLIT_MEASURE_CYCLE TIME......................................................A-57

SET STROBE_WINDOW TIME..................................................................A-60

SET TIME SCALE........................................................................................A-62

Appendix B

FlexTest WDB Translation Support ..................................................................B-1

Invoking wdb2flex..............................................................................................B-1

Control File.........................................................................................................B-2

Example..............................................................................................................B-4

Using wdb2flex Effectively................................................................................B-6

Index

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Table of Contents

LIST OF FIGURES

Figure 1. DFT Documentation Roadmap ...........................................................xix

Figure 2-1. MISR placement ........................................................................... 2-72

Figure 5-1. Master and Slave Workstations ...................................................... 5-2

Figure 5-2. FlexTest Invocation Arguments Dialog Box.................................. 5-5

Figure A-1. Scan Event Timing for SET END_MEASURE_CYCLE TIME...A-4

Figure A-2. Scan Event Timing for SET SPLIT_MEASURE_CYCLE TIME ......

A-15 Figure A-3. SET SPLIT_MEASURE_CYCLE TIME Non-scan Event Timing

Diagram ............................................................................................................A-19

Figure A-4. SET STROBE_WINDOW Timing Diagram...............................A-21

Figure A-5. Template Timing for Example 1..................................................A-28

Figure A-6. SET BIDI_FORCE Timing Example ..........................................A-34

Figure A-7. SET CYCLE Timing Example ....................................................A-36

Figure A-8. SET FORCE Timing Example.....................................................A-43

Figure A-9. SET MEASURE Timing Example ..............................................A-46

Figure A-10. SET SKEW_FORCE Timing Example .....................................A-53

Figure A-11. SET STROBE_WINDOW Timing Diagram.............................A-61

Figure B-1. Example WDB2FLEX Circuit Timing Example ...........................B-4

Figure B-2. Detailed Pin Timing .......................................................................B-9

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FastScan and FlexTest Reference Manual, V8.6_4

Table of Contents

LIST OF TABLES

Table 2-1. Command Summary ......................................................................... 2-1

Table 2-2. Fault Class Codes and Names ...................................................... 2-299

Table 2-3. Reportable Gate Types ................................................................ 2-321

Table 2-4. FlexTest Learned Gate Types ...................................................... 2-323

Table 2-5. FastScan Clock Port Categories ................................................... 2-324

Table 2-6. WIRE Bus Contention Truth Table .............................................. 2-529

Table 2-7. AND Bus Contention Truth Table ............................................... 2-529

Table 2-8. OR Bus Contention Truth Table .................................................. 2-530

Table 2-9. DRC Non-scan Cell Classifications ............................................. 2-534

Table A-1. Timing Command Summary ...........................................................A-2

FastScan and FlexTest Reference Manual, V8.6_4

LIST OF TABLES [continued]

Table of Contents

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FastScan and FlexTest Reference Manual, V8.6_4

About This Manual Overview

About This Manual

Overview

FastScan and FlexTest are Mentor Graphics ATPG tools which are an integral part of the Mentor Graphics Design-For-Test solution.

FastScan is a comprehensive combinational Automatic Test Pattern Generation (ATPG) system optimized for full scan designs. It offers the highest speed and accurately measured high test coverage to guarantee your product quality and reliability.

FlexTest is a high performance sequential Automatic Test Pattern Generation (ATPG) system that allows you to create a set of test patterns that achieves a high, accurately measured test coverage for your cycle-based circuits.

Optionally available with FastScan and FlexTest is Mentor Graphics DFTInsight which can translate a specified portion of a netlist-based design to schematic form. DFTInsight adds the ability to graphically investigate and interact with designs, thus facilitating testability debugging efforts.

This manual contains information on each of the FastScan, FlexTest, and DFTInsight application commands. Additionally, the manual contains reference information specific to each of these applications. For procedural information on how to use FastScan, FlexTest, or DFTInsight in the ASIC/IC design environment, refer to the Scan and ATPG Process Guide.

This manual is divided into the sections and appendices that follow:

• Chapter 1 — Introduction - briefly describes the inputs, outputs, and

features of FastScan, FlexTest, and DFTInsight.

• Chapter 2 — Command Dictionary - lists the detailed information for

each command.

FastScan and FlexTest Reference Manual, V8.6_4

xvii

Overview About This Manual

• Chapter 3 — Shell Commands - lists the detailed information on the

FastScan, FlexTest, and DFTInsight invocation commands.

• Chapter 4 —Test Pattern File Formats - describes the test pattern file

format.

• Chapter 5 —Distributed FlexTest - describes how to divide ATPG

processes into smaller sets and run these sets simultaneously on multiple workstations.

• Appendix A —Timing Command Dictionary - describes how to create a

timing file and apply it to the test pattern set.

• Appendix B —FlexTest WDB Translation Support - describes

FlexTest’s usage of the “wdb2flex” utility to translate Waveform Databases to FlexTest Table Format Patterns.

The DFT applications use Adobe Acrobat Exchange as their online documentation and help viewer. Online help requires installing the Mentor Graphics-supplied Acrobat Exchange program with Mentor Graphics-specific plugins and also requires setting an environment variable. For more information, refer to the section, “Setting Up Online Manuals and Help” in Using Mentor Graphics Documentation with Acrobat Exchange.

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FastScan and FlexTest Reference Manual, V8.6_4

About This Manual Related Publications

Related Publications

This section gives references to both Mentor Graphics product documentation and industry DFT documentation.

Mentor Graphics Documentation

Figure 1 shows the Mentor Graphics DFT manuals and their relationship to each

other and is followed by a list of descriptions for these documents.

Design-for-Test

Common Resources

Manual

DFTAdvisor

Reference Manual

Scan and ATPG

Process Guide

Boundary Scan

Process Guide

Release Notes

Design-for-Test

Built-in Self-Test

Process Guide

FastScan & FlexTest

Reference Manual

BSDArchitect

Reference Manual

LBISTArchitect

Reference Manual

Figure 1. DFT Documentation Roadmap

Boundary Scan Process Guide — provides process, concept, and procedure

information for the boundary scan product, BSDArchitect. It also includes information on how to integrate boundary scan with the other DFT technologies.

BSDArchitect Reference Manual — provides reference information for

BSDArchitect, the boundary scan product.

FastScan and FlexTest Reference Manual, V8.6_4

MBISTArchitect

Reference Manual

xix

Related Publications About This Manual

Built-in Self-Test Process Guide — provides process, concept, and

procedure information for using MBISTArchitect, LBISTArchitect, and other Mentor Graphics tools in the context of your BIST design process.

Design-for-Test Common Resources Manual — contains information

common to many of the DFT tools: design rule checks (DRC), DFTInsight (the schematic viewer), library creation, VHDL support, Verilog support, Spice support, and test procedure file format.

Design-for-Test Release Notes — provides release information that reflects

changes to the DFT products for the software version release.

DFTAdvisor Reference Manual — provides reference information for

DFTAdvisor (internal scan insertion) and DFTInsight (schematic viewer) products.

FastScan and FlexTest Reference Manual — provides reference

information for FastScan (full-scan ATPG), FlexTest (non- to partial-scan ATPG), and DFTInsight (schematic viewer) products.

LBISTArchitect Reference Manual — provides reference information for

LBISTArchitect, the logic built-in self-test product.

MBISTArchitect Reference Manual — provides reference information for

MBISTArchitect, the memory built-in self-test product.

Scan and ATPG Process Guide — provides process, concept, and

procedure information for using DFTAdvisor, FastScan, and FlexTest in the context of your DFT design process.

Using Mentor Graphics Documentation with Acrobat Exchange —

describes how to set up and use the Mentor Graphics-supplied Acrobat Exchange with enhancement plugins for online viewing of Mentor Graphics PDF-based documentation and help. The manual contains procedures for using Mentor Graphics documentation, including setting up online manuals and help, opening documents, and using full-text searches. Also included are tips on using Exchange.

FastScan and FlexTest Reference Manual, V8.6_4

About This Manual Acronyms Used in This Manual

Acronyms Used in This Manual

Below is an alphabetical listing of the acronyms used in this manual: ASIC - Application Specific IC ATE - Automatic Test Equipment ATPG - Automatic Test Pattern Generation AU - ATPG_Untestable fault AVI - ASIC Vector Interfaces BIST - Built-In Self Test BSDA - Boundary Scan Design Architect BSDL - Boundary Scan Design Language CUT - Circuit Under Test DFT - Design For Test DFTA - DFTAdvisor DFTI - DFTInsight DRC - Design Rules Check DUT - Device Under Test EDDM - Electronic Design Data Model EDIF - Electronic Design Interchange Format FS - FastScan FT - FlexTest

FastScan and FlexTest Reference Manual, V8.6_4

xxi

Acronyms Used in This Manual About This Manual

GENIE - General Interpreted Environment IDDQ - Quiescent Drain Current I/O - Input/Output JTAG - Joint Test Action Group LFSR - Linear Feedback Shift Register LSSD - Level Sensitive Scan Design MCM - Multi-Chip Module MISR - Multiple Input Signature Register PGS - Pulse Generator Sink PI - Primary Input PRPG - Pseudo-Random Pattern Generator PO - Primary Output PU - Posdet_Untestable fault SFP - Single Fault Propagation TDL - TEGAS Design Language UI - User Interface VHDL - VHSIC Hardware Description Language VHSIC - Very High Speed IC WDB - Waveform DataBase

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FastScan and FlexTest Reference Manual, V8.6_4

About This Manual Command Line Syntax Conventions

Command Line Syntax Conventions

Each point-tool manual will include the following notation conventions section in the ATM chapter. For more information on Mentor Graphics documentation conventions, see the “Mentor Graphics Learning Products Style Guide”

The notational elements for command line syntax are as follows:

Bold A bold font indicates a required argument. [ ] Square brackets enclose optional arguments (in command line

syntax only). Do not enter the brackets.

UPPercase Required command letters are in uppercase; in most cases, you

may omit lowercase letters when entering commands or literal arguments and you need not use uppercase. Command names and options are normally case insensitive, but for some tools the initial command name is case sensitive and must be lowercase. Commands usually follow the 3-2-1 rule: the first three letters of the first word, the first two letters of the second word, and the first letter of the third, fourth, etc. words.

Italic An italic font indicates a user-supplied argument.

An underlined item indicates either the default argument or the default value of an argument.

{ } Braces enclose arguments to show grouping. Do not enter the

braces.

| The vertical bar indicates an either/or choice between items. Do

not include the bar in the command.

… An ellipsis follows an argument that may appear more than once.

Do not include the ellipsis in commands.

You should enter literal text (that which is not in italics) exactly as shown.

FastScan and FlexTest Reference Manual, V8.6_4

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Command Line Syntax Conventions About This Manual

xxiv

FastScan and FlexTest Reference Manual, V8.6_4

Chapter 1

Introduction

FastScan and FlexTest are Mentor Graphics high-performance Automatic Test Pattern Generation (ATPG) tools. FastScan performs full-scan and scansequential ATPG, while FlexTest performs sequential ATPG. These are two of several tools in the Mentor Graphics Design-for-Test (DFT) tool suite. The following subsections list the features and inputs/outputs of the tools. For information on using FastScan or FlexTest in the context of a DFT flow, refer to the “Generating Test Patterns” chapter in the Scan and ATPG Process Guide.

Features

FastScan and FlexTest share numerous features, including the following:

• You can use them within a Mentor Graphics flow or as a point tool within

other design flows.

• Contain an internal high-speed fault simulator.

• Read most standard gate-level netlists.

• Produce a number of standard test pattern data formats.

• Contain a powerful design rules checker.

FastScan-specific features include the following:

• Produces very high coverage test pattern sets for full-scan and scan-

sequential designs. Scan-sequential designs contain well-behaved sequential scan circuitry, including non-scan latches, sequential memories, and limited sequential depth.

FastScan and FlexTest Reference Manual, V8.6_4

1-1

Inputs and Outputs Introduction

• Contains functionality for handling embedded RAM and ROM.

• Contains functionality for simulating and generating test pattern sets for

BIST circuitry.

FlexTest-specific features include the following:

• Supports a wide range of DFT structures.

• Can display a wide variety of useful information—from design and

debugging information to statistical reports for the generated test set.

Inputs and Outputs

FastScan and FlexTest utilize the following inputs:

• Design - The supported netlist formats are EDDM, EDIF, GENIE, Verilog,

VHDL, SPICE and TDL.

• Test Procedure File - This file defines the operation of the scan circuitry in

your design. You can generate the file by hand or using the Write ATPG Setup command in DFTAdvisor. For more information on test procedure files, refer to “Test Procedure Files” in the Scan and ATPG Process Guide.

• Library - This file contains model descriptions for all library cells used in

your design.

• Fault List - This is an external fault list that you can use as a source of faults

for the internal fault list of FlexTest.

• Test Patterns - This is a set of externally-generated test patterns that you can

use as the pattern source for simulation.

1-2

FastScan and FlexTest Reference Manual, V8.6_4

Introduction Inputs and Outputs

FastScan and FlexTest produce the following outputs:

• Test Patterns - This file set contains test patterns in one or more of the

supported simulator or ASIC vendor pattern formats. For more information on the available test pattern formats, refer to the Save Patterns command reference page within this manual, or the “Saving the Patterns” section in the Scan and ATPG Process Guide.

• ATPG Information Files - These files contain session information that you

can save using various FlexTest commands.

• Fault List - This is an ASCII file containing internal fault information in the

standard Mentor Graphics fault format.

FastScan and FlexTest Reference Manual, V8.6_4

1-3

Inputs and Outputs Introduction

1-4

FastScan and FlexTest Reference Manual, V8.6_4

Chapter 2

Command Dictionary

This chapter contains descriptions of the FastScan, FlexTest, and DFTInsight commands. The subsections are named for the command they describe. For quick reference, the commands appear alphabetically with each beginning on a separate page.

Command Summary

Table 2-1 contains a summary of the commands described in this manual. The

three columns that separate the command name and the description indicate the tools in which you can use the commands. The following tool acronyms are used in the table:

DFTI DFTInsight FS FastScan FT FlexTest

Table 2-1. Command Summary

D F TIFSF

Command

Abort Interrupted Process

Add Ambiguous Paths

Add Atpg Constraints

•

••

Aborts a command placed in suspended state by a Control-C interrupt while the Set Interrupt Handling command is on.

Specifies for FastScan to select multiple paths when there is path ambiguity.

Specifies that the tool restrict all patterns it places into the internal pattern set according to the user-defined constraints.

Description

FastScan and FlexTest Reference Manual, V8.6_4

2-1

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Add Atpg Functions

Add Capture Handling

Add Cell Constraints Add Cell Library

Add Clocks Add Cone Blocks

Add Control Points Add Display Instances

••

•

••

•

•••

Creates an ATPG function that you can then use when generating user-defined ATPG constraints.

Specifies the data capturing behavior for the given state element.

Constrains scan cells to be at a constant value. Specifies the EDIF library in which to place

all or specified library models. Adds clock primary inputs to the clock list.

Specifies the blockage points that you want the tool to use during the calculation of the clock and effect cones.

Adds control points to output pins. Adds the specified instances to the netlist for

display.

Add Display Loop

Add Display Path

Add Display Scanpath

Add Faults Add Iddq Constraints

2-2

•••

••

Displays all the gates in a specified feedback path.

Displays all the gates associated with the specified path.

Displays all the associated gates between two positions in a scan chain.

Adds faults into the current fault list. Sets constraints for generation or selection of

IDDQ patterns.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Add Initial States

Add LFSR Connections

Add LFSR Taps

Add LFSRs

Add Lists

Add Mos Direction

Add Net Property

•

••

Specifies an initial state for the selected sequential instance.

Connects an external pin to a Linear Feedback Shift Register (LFSR).

Adds the tap configuration to a Linear Feedback Shift Register (LFSR).

Adds Linear Feedback Shift Registers (LFSRs) for use as Pseudo-Random Pattern Generators (PRPGs) or Multiple Input Signature Registers (MISRs).

Adds pins to the list of pins on which to report.

Assigns the direction of a bi-directional MOS transistor.

Defines the net in the Spice design and library as VDD or GND.

Add Nofaults

Add Nonscan Handling

Add Notest Points

Add Observe Points

FastScan and FlexTest Reference Manual, V8.6_4

••

•

Places nofault settings either on pin pathnames, pin names of specified instances, or modules.

Overrides behavior classification of non-scan

•

elements that FlexTest learns during the design rules checking process.

Adds circuit points to list for exclusion from testability insertion.

Adds observe points to output pins.

2-3

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Add Output Masks

Add Pin Constraints

Add Pin Equivalences

Add Pin Strobes Add Primary Inputs Add Primary Outputs Add Random Weights

Add Read Controls Add Scan Chains Add Scan Groups

••

•

••

•

••

Ignores any fault effects that propagate to the primary output pins you name.

Adds pin constraints to primary inputs and input channel to I/O pins.

Adds restrictions to primary inputs such that they have equal or inverted values.

Adds strobe time to the primary outputs. Adds primary inputs. Adds primary outputs. Specifies the random pattern weighting

factors for primary inputs. Adds an off-state value to read control lines.

Adds a scan chain to a scan group. Adds a scan chain group to the system.

Add Scan Instances

Add Scan Models Add Slow Pad Add Tied Signals Add Write Controls

2-4

•

••

Adds sequential instances to the scan instance list.

Adds sequential models to the scan model list. Sets the specified I/O pin as a slow pad. Adds a value to floating signals or pins. Adds an off-state value to specified write

control lines.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Analyze Atpg Constraints

Analyze Bus

Analyze Control Analyze Control

Signals Analyze Drc Violation

Analyze Fault

Analyze Observe

•

••

•

•••

••

•

Specifies for FastScan or FlexTest to check the ATPG constraints you’ve created for their satisfiability or for their mutual exclusivity.

Causes the tool to analyze the specified bus gates for contention problems.

Calculates zero and one-state controllability. Identifies the primary inputs of control

signals. Generates a netlist of the portion of the design

involved with the specified rule violation number.

Performs an analysis to identify why a fault is not detected and optionally displays the relevant circuitry in DFTInsight.

Calculates observability coverage.

Analyze Race

Analyze Restrictions

Close Schematic Viewer

Compress Patterns

Create Initialization Patterns

FastScan and FlexTest Reference Manual, V8.6_4

• Performs an analysis to automatically

•••

••

•

Checks for race conditions between the clock

•

and data signals.

determine the source of the problems from a failed ATPG run.

Terminates the optional schematic viewing application (DFTInsight).

Compresses patterns in the current test pattern set.

Creates RAM initialization patterns and places them in the internal pattern set.

2-5

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Create Patterns Delete Atpg Constraints

Delete Atpg Functions Delete Capture

Handling Delete Cell Constraints

Delete Clocks

Delete Cone Blocks

Delete Control Points Delete Display

Instances

•

••

•

••

•

•••

Automates good ATPG compression flow. Removes the state restrictions from the

specified objects. Removes the specified function definitions.

Removes the special data capture handling for the specified objects.

Removes constraints placed on scan cells. Removes primary input pins from the clock

list. Removes the specified output pin names from

the user-created list which the tool uses to calculate the clock and effect cones.

Removes previously specified control points. Removes the specified objects from the

display in DFTInsight.

Delete Faults Delete Iddq Constraints

Delete Initial States

Delete LFSR Connections

Delete LFSR Taps

2-6

••

•

Removes faults from the current fault list. Removes the IDDQ restrictions from the

specified pins. Removes the initial state settings for the

specified instance names. Removes connections between the specified

primary pins and Linear Feedback Shift Registers (LFSRs).

Removes the tap positions from a Linear Feedback Shift Register (LFSR).

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Delete LFSRs

Delete Lists

Delete Mos Direction

Delete Net Property

Delete Nofaults

Delete Nonscan Handling

Delete Notest Points

•

••

•

Removes the specified Linear Feedback Shift Registers (LFSRs).

Removes the specified pins from the pin list that the tool monitors while in the Fault or Good simulation system mode.

Resets the VDD or GND net in the Spice design and library.

Removes the nofault settings from either the specified pin or instance/module pathnames.

Removes the overriding learned behavior classification for the specified non-scan elements.

Removes the circuit points which the tool cannot use for testability insertion from the specified pins.

Delete Observe Points

Delete Output Masks

Delete Paths

Delete Pin Constraints

FastScan and FlexTest Reference Manual, V8.6_4

•

••

Removes observe points from the specified pins.

Removes the masking of the specified

•

primary output pins. Removes the specified path delay faults from

the current fault list. Removes the pin constraints from the

specified primary input pins.

2-7

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Delete Pin Equivalences

Delete Pin Strobes

Delete Primary Inputs

Delete Primary Outputs

Delete Random Weights

Delete Read Controls

Delete Scan Chains

Delete Scan Groups

••

•

••

•

••

Removes the pin equivalence specifications for the designated primary input pins.

Removes the strobe time from the specified primary output pins.

Removes the specified primary inputs from the current netlist.

Removes the specified primary outputs from the current netlist.

Removes the random pattern weighting factors for the specified primary input pins.

Removes the read control line definitions from the specified primary input pins.

Removes the specified scan chain definitions from the scan chain list.

Removes the specified scan chain group definitions from the scan chain group list.

Delete Scan Instances

Delete Scan Models

Delete Slow Pad

Delete Tied Signals

Delete Write Controls

2-8

•

••

Removes from the scan instance list the specified sequential instances.

Removes the specified sequential models from the scan model list.

Resets the specified I/O pin back to the default simulation mode.

Removes the assigned (tied) value from the specified floating nets or pins.

Removes the write control line definitions from the specified primary input pins.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Diagnose Failures

Dofile

Exit Extract Subckts

Flatten Model

Flatten Subckt Help

Insert Testability

•

••

•

Diagnoses the failing patterns that the specified file identifies.

Executes the commands contained within the specified file.

Terminates the application tool program. Performs matching and conversion between

the bi-directional MOS instance and the ATPG library model.

Creates a primitive gate simulation representation of the design.

Flattens the SUBCKT in the Spice design. Displays the usage syntax and system mode

for the specified command. Performs testability analysis to achieve

maximum test coverage.

Load Faults

Load Paths

Macrotest

Mark

FastScan and FlexTest Reference Manual, V8.6_4

••

•

•••

Updates the current fault population to include or exclude the faults contained in the specified fault file.

Reads into FastScan the path definitions contained in the specified ASCII file.

Automates the testing of embedded RAMs or ROMs, embedded hierarchical instances, and embedded blocks of logic with unidirectional I/O.

Highlights the objects that you specify in the Schematic View window.

2-9

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Open Schematic Viewer

Read Modelfile

Read Procfile

Read Subckts Library Redo Display

Report Aborted Faults

Report Atpg Constraints

••

•••

••

Invokes the optional schematic viewing application, DFTInsight.

Initializes the specified RAM or ROM gate using the memory states contained in the named modelfile.

Reads the specified new enhanced procedure file.

Reads the specified Spice SUBCKT library. Nullifies the schematic view effects of an

Undo command. Displays information on undetected faults

caused when the tool aborted the simulation during the ATPG process.

Displays all the current ATPG state restrictions and the pins on which they reside.

Report Atpg Functions

Report AU Faults

Report Bus Data

Report Capture Handling

Report Cell Constraints

2-10

••

•

••

•

••

Displays all the current ATPG function definitions.

Displays information on ATPG untestable faults.

Displays the bus data information for either an individual bus gate or for the buses of a specific type.

Displays any special data capture handling currently in use.

Displays a list of all the constrained scan cells.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Report Clocks

Report Cone Blocks

Report Control Data

Report Control Points Report Core Memory

Report Display Instances

Report Drc Rules

••

•

•••

••

Displays a list of all the primary input pins currently in the clock list.

Displays the current user-defined output pin pathnames that the tool uses to calculate the clock and effect cones.

Displays information from the last Analyze Control command.

Displays the list of control points. Displays the amount of memory FlexTest

requires to avoid paging during the ATPG and simulation processes.

Displays a textual report of the netlist information for either the specified gates or instances or for all the gates in the current schematic view display.

Displays either a summary of all the Design Rule Check (DRC) violations or the data for a specific violation.

Report Environment

Report Failures Report Faults

Report Feedback Paths

FastScan and FlexTest Reference Manual, V8.6_4

••

•

••

•••

Displays the current values of all the “set” commands.

Displays the failing pattern results. Displays fault information from the current

fault list. Displays a textual report of the currently

identified feedback paths.

2-11

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Report Flatten Rules

Report Gates

Report Hosts

Report Id Stamp

Report Iddq Constraints

Report Initial States

Report LFSR Connections

•••

••

•

••

•

Displays either a summary of all the flattening rule violations or the data for a specific violation.

Displays the netlist information for the specified gates.

Displays information on the hosts available for distributed processing.

Displays the unique identifier that FastScan assigns each internal pattern set.

Displays the current IDDQ constraints for the specified pins.

Displays the initial state settings of the specified design instances.

Displays a list of all the connections between Linear Feedback Shift Registers (LFSRs) and primary pins.

Report LFSRs

Report Lists

Report Loops Report Mos Direction

Report Net Properties

2-12

•

••

Displays a list of definitions for all the current Linear Feedback Shift Registers (LFSRs).

Displays a list of pins which the tool reports on while in the Fault or Good simulation system mode.

Displays a list of all the current loops. Reports the direction MOS instances in the

Spice design and Spice SUBCKT library. Reports the VDD or GND net properties in

the Spice design and library.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Report Nofaults

Report Nonscan Cells

Report Nonscan Handling

Report Notest Points

Report Observe Data

Report Observe Points

Report Output Masks

••

•

Displays the nofault settings for the specified pin pathnames or pin names of instances.

Displays the non-scan cells whose model type you specify.

Displays the overriding learned behavior

•

classification for the specified non-scan elements.

Displays all the circuit points for which you do not want FastScan to insert controllability and observability.

Displays information from the preceding Analyze Observe command.

Displays a list of all the current observe points.

••Displays a list of the currently masked

primary output pins.

Report Paths

Report Pin Constraints

Report Pin Equivalences

Report Pin Strobes

Report Primary Inputs

FastScan and FlexTest Reference Manual, V8.6_4

•

••

Displays the path definitions of the specified loaded paths.

Displays the pin constraints of the primary inputs.

Displays the pin equivalences of the primary inputs.

Displays the current pin strobe timing for the

•

specified primary output pins. Displays the specified primary inputs.

2-13

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Report Primary Outputs Report Procedure Report Pulse

Generators Report Random

Weights

Report Read Controls

Report Scan Cells

Report Scan Chains

Report Scan Groups

••

•

••

Displays the specified primary outputs. Displays the specified procedure. Displays the list of pulse generator sink (PGS)

gates. Displays the current random pattern

weighting factors for all primary inputs in the random weight list.

Displays all of the currently defined read control lines.

Displays a report on the scan cells that reside in the specified scan chains.

Displays a report on all the current scan chains.

Displays a report on all the current scan chain groups.

Report Scan Instances

Report Scan Models

Report Seq_transparent Procedures

Report Slow Pads Report Statistics

2-14

•

••

Displays the currently defined sequential scan instances.

Displays the sequential scan models currently in the scan model list.

Displays a list of seq_transparent test procedures along with the associated data that you specify.

Displays all I/O pins marked as slow. Displays a detailed report of the design’s

simulation statistics.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Report Test Stimulus

Report Testability Data

Report Tied Signals

Report Timeplate Report Version Data

Report Write Controls

Reset Au Faults

Reset State

•

••

•

••

Displays the stimulus necessary to satisfy the specified set, write, or read conditions.

Analyzes collapsed faults for the specified fault class and displays the analysis.

Displays a list of the tied floating signals and pins.

Displays the specified timeplate. Displays the current software version

information. Displays the currently defined write control

lines and their off-states. Re-classifies the faults in certain untestable

categories. Resets the circuit status.

Resume Interrupted Process

Run Save Flattened Model

Save Patterns

Save Schematic

FastScan and FlexTest Reference Manual, V8.6_4

••

•

••

Continues a command that you placed in a

•

suspended state by entering a Control-C interrupt.

Runs a simulation or ATPG process. Saves the flattened circuit model, the scan

trace, and all DRC related information to a specific file.

Saves the current test pattern set to a file in the format that you specify.

Saves the schematic currently displayed by DFTInsight.

2-15

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Select Iddq Patterns

Select Object Set Abort Limit

Set Atpg Compression

Set Atpg Limits

Set Atpg Window

Set AU Analysis

Set Bist Initialization

••

•••

••

•

••

•

Selects the patterns that most effectively detect IDDQ faults.

Selects the specified objects in the design. Specifies the abort limit for the test pattern

generator. Specifies for the ATPG to perform dynamic

pattern compression. Specifies the ATPG process limits at which

the tool terminates the ATPG process. Allows you to specify the size of the FlexTest

simulation window. Specifies whether the ATPG uses the ATPG

untestable information to place ATPG untestable faults directly in the AU fault class.

Specifies the scan chain input value which indicates the states of the scan cells before FastScan applies Built-In Self Test (BIST) patterns.

Set Bus Handling

Set Bus Simulation

Set Capture Clock

2-16

••

•

••

Specifies the bus contention results that you desire for the identified buses.

Specifies whether the tool uses global or local bus simulation analysis.

Specifies the capture clock name for random pattern simulation.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Capture Handling

Set Capture Limit

Set Checkpoint

Set Clock Restriction

Set Clock_off Simulation

Set Clockpo Patterns

Set Contention Check

•

••

•

••

Specifies how FastScan globally handles the data capture of state elements that have C3 and C4 rule violations.

Specifies the number of test cycles between two consecutive scan operations.

Specifies whether the tool uses the checkpoint functionality.

Specifies whether the ATPG can create patterns with more than one active capture clock.

Enables or disables simulation with the clocks off.

Specifies whether ATPG can perform pattern creation for primary outputs that connect to clocks.

Specifies the conditions of contention checking.

Set Control Threshold

Set Decision Order

Set Dofile Abort

Set Drc Handling

FastScan and FlexTest Reference Manual, V8.6_4

•

••

Specifies the controllability value for random pattern simulation.

Specifies how the ATPG determines and uses observation points.

Lets you specify whether the tool aborts or continues dofile execution if an error condition is detected.

Specifies how the tool globally handles design rule violations.

2-17

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Driver Restriction

Set Fails Report

Set Fault Mode

Set Fault Sampling Set Fault Type

Set Flatten Handling

Set Gate Level

Set Gate Report

••

•

••

•••

••

Specifies whether the tool allows multiple drivers on buses and multiple active ports on gates.

Specifies whether the design rules checker displays clock rule failures.

Specifies whether the fault mode is collapsed or uncollapsed.

Specifies the fault sampling percentage. Specifies the fault model for which the tool

develops or selects ATPG patterns. Specifies how the tool globally handles

flattening violations. Specifies the hierarchical level of gate

reporting and displaying. Specifies the additional display information

for the Report Gates command.

Set Hypertrophic Limit

Set Iddq Checks

Set Iddq Strobe

2-18

•

••

Specifies the percentage of the original design’s sequential primitives that can differ from the good machine before the tool classifies them as hypertrophic faults.

Specifies the restrictions and conditions that you want the tool to use when creating or selecting patterns for detecting IDDQ faults.

Specifies on which patterns (cycles) the tool will simulate IDDQ measurements.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Instancename Visibility

Set Instruction Atpg

Set Internal Fault

Set Internal Name

Set Interrupt Handling

Set IO Mask

•••

••

Specifies whether DFTInsight displays instance names immediately above each instance in the Schematic View area.

Specifies whether FlexTest generates

•

instruction-based test vectors using the random ATPG process.

Specifies whether the tool allows faults within or only on the boundary of library models.

Specifies whether to delete or keep pin names of library internal pins containing no-fault attributes.

Specifies how FlexTest interprets a Control-C

•

interrupt.

• Modifies the behavior of IO pins so that their

expected values will always be X during test cycles in which the primary input portion of the IO pin is being forced.

Set Learn Report

Set List File

Set Logfile Handling

Set Loop Handling

FastScan and FlexTest Reference Manual, V8.6_4

••

Specifies whether the Report Gates command can display the learned behavior for a specific gate.

Specifies the name of the list file into which the tool places the pins’ logic values during simulation.

Specifies for the tool to direct the transcript information to a file.

Specifies how the tool handles feedback networks.

2-19

Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Multiple Load

Set Net Dominance

Set Net Resolution Set Nonscan Model

Set Number Shifts

Set Observation Point

Set Observe Threshold

•

••

•

Specifies how the tool handles multiple scan loads.

Specifies the fault effect of bus contention on tri-state nets.

Specifies the behavior of multi-driver nets. Specifies how FlexTest classifies the behavior

of non-scan cells with the HOLD and INITX functionality during the operation of the scan chain.

Sets the number of shifts for loading or unloading the scan chains.

Specifies the observation point for random pattern fault simulation.

Specifies the minimum number of observations necessary for the Analyze Observe command to consider a point adequately observed.

Set Output Comparison

Set Output Mask

Set Pathdelay Holdpi

Set Pattern Source

2-20

•

••

Specifies whether FlexTest performs a good circuit simulation comparison.

Specifies how FlexTest handles an unknown (X) state in an external pattern set.

Specifies whether the ATPG keeps non-clock primary inputs at a constant state after the first force.

Specifies the source of the patterns for future Run commands.

FastScan and FlexTest Reference Manual, V8.6_4

Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Possible Credit

Set Procedure Cycle_checking

Set Pulse Generators

Set Race Data

Set Rail Strength

Set Ram Initialization

Set Ram Test

••

•

Specifies the percentage of credit that the tool assigns possible-detected faults.

Enables test procedure cycle timing checking to be done immediately following scan chain tracing during design rules checking.

Specifies whether the tool identifies pulse generator sink (PGS) gates.

Specifies how FlexTest handles the output states of a flip-flop when the data input pin changes at the same time as the clock triggers.

Specifies FlexTest to set the strongest strength of a fault site to a bus driver.

Specifies whether to initialize RAM and ROM gates that do not have initialization files.

Specifies the mode for RAM testing with random or Built-In Self Test (BIST) patterns.

Set Random Atpg

Set Random Clocks

Set Random Patterns

Set Random Weights

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••

•

Specifies whether the tool uses random patterns during ATPG.

Specifies whether FastScan uses combinational or clock_sequential patterns for random pattern simulation.

Specifies the number of random patterns FastScan simulates.

Specifies the default random pattern weighting factor for primary inputs.

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Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Redundancy Identification

Set Schematic Display

Set Screen Display

Set Self Initialization

Set Sensitization Checking

Set Sequential Learning

Set Shadow Check

•

•••

••

•

••

•

Specifies whether FlexTest performs the checks for redundant logic when leaving the Setup mode.

Changes the default schematic display environment settings for DFTInsight.

Specifies whether the tool writes the transcript to the session window.

Specifies whether FlexTest turns on/off selfinitializing sequence behavior.

Specifies whether DRC checking attempts to verify a suspected C3 or C4 rules violation.

Specifies whether the tool performs the learning analysis of sequential elements to make the ATPG process more efficient.

Specifies whether FastScan will identify sequential elements as a “shadow” element during scan chain tracing.

Set Simulation Mode

Set Skewed Load

Set Split Capture_cycle

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•

Specifies whether the ATPG simulation run uses combinational or sequential RAM test patterns.

Specifies whether FastScan includes a skewed load in the patterns.

Enables or disables the simulation of level sensitive and leading edge state elements updating as a result of applied clocks.

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Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Stability Check

Set Static Learning

Set Stg Extraction

Set System Mode

Set Test Cycle

Set Trace Report

Set Transition Holdpi

•

••

•

••

•

••

•

Specifies whether the tool checks the effect of applying the main shift procedure on non-scan cells.

Specifies whether FastScan or FlexTest performs the learning analysis to make the ATPG process more efficient.

Specifies whether FlexTest performs state transition graph extraction.

Specifies the system mode you want the tool to enter.

Specifies the number of timeframes per test cycle.

Specifies whether the tool displays gates in the scan chain trace.

Specifies for FastScan to freeze all primary input values other than clocks and RAM controls during multiple cycles of pattern generation.

Set Unused Net

Set Workspace Size

Set Xclock Handling

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•

Specifies whether FlexTest removes unused

•

bus and wire nets in the design.. Increases the workspace so that FastScan can

try to detect the undetected faults that were aborted due to workspace constraints.

Specifies whether FastScan changes the sequential element model to always set the output of the element to be X when any of its clock inputs become X.

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Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Set Z Handling

Set Zhold Behavior

Set Zoom Factor

Setup Checkpoint

Setup LFSRs

Setup Pin Constraints

Setup Pin Strobes

••

•

•••

••

•

••

•

Specifies how the tool handles high impedance signals for internal and external tri-state nets.

Specifies whether ZHOLD gates retain their state values.

Specifies the scale factor that the zoom icons use in the DFTInsight Schematic View window.

Specifies the checkpoint file to which the tool writes test patterns or fault lists during ATPG.

Changes the shift_type and tap_type default setting for the Add LFSRs and Add LFSR Taps commands.

Changes the default cycle behavior for nonconstrained primary inputs.

Changes the default strobe time for primary outputs without specified strobe times.

Setup Tied Signals

Step

System

Undo Display

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••

•

••

•••

Changes the default value for floating pins and floating nets which do not have assigned values.

Single-steps through several cycles of a test set.

Passes the specified command to the operating system for execution.

Restores the previous schematic view.

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Command Dictionary Command Summary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Unmark

Unselect Object

Update Implication Detections

View

View Area

Write Core Memory

•••

••

•••

•

Removes the highlighting from the specified object in Schematic View window.

Removes the specified objects from the selection list.

Performs an analysis on the undetected and possibly-detected faults to see if the tool can classify any of those faults as detected-byimplication.

Displays, in the DFTInsight Schematic View window, the specified objects in the display list.

Displays an area that you specify in the DFTInsight Schematic View window.

Writes to a file the amount of memory that FlexTest requires to avoid paging during the ATPG and simulation processes.

Write Environment

Write Failures Write Faults

Write Initial States

Write Library_verification Setup

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•

••

Writes the current environment settings to the

•

file that you specify. Writes failing pattern results to a file.

Writes fault information from the current fault list to a file.

Writes the initial state settings of design

•

instances into the file that you specify. Generates ATPG library verification setup

•

files.

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Command Summary Command Dictionary

Table 2-1. Command Summary [continued]

D F TIFSF

Command

Description

Write Loops Write Modelfile

Write Netlist

Write Paths

Write Primary Inputs Write Primary Outputs

Write Procfile

Write Statistics

••

•

••

•

Writes a list of all the current loops to a file. Writes all internal states for a RAM or ROM

gate into the file that you specify. Writes the modified or new format netlist to

the specified file. Writes the path definitions of the loaded paths

into the file that you specify. Writes the primary inputs to the specified file.

Writes the primary outputs to the specified file.

Writes existing procedure and timing data to the named enhanced procedure file.

Writes the current simulation statistics to the specified file.

Write Timeplate

Zoom In

Zoom Out

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•

•••

Writes the default timing information for nonscan related events into the file that you specify.

Enlarges the objects in the DFTInsight Schematic View window by reducing the displayed area.

Reduces the objects in the DFTInsight Schematic View window by enlarging the displayed area.

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Command Dictionary Command Descriptions

Command Descriptions

The remaining pages in this chapter describe, in alphabetical order, the commands used either in FastScan or FlexTest. Each command description begins on a new page and contains a line indicating the applications that are supported. The descriptions of commands that support both FastScan and FlexTest apply equally to both tools unless specified otherwise. All commands are available in both the point tool version and falcon version unless otherwise noted. You can use the line continuation character “\” when application commands extend beyond the end of a line. The line continuation character improves the readability of dofiles and helps with the command line entry of multiple-argument commands.

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Abort Interrupted Process Command Dictionary

Abort Interrupted Process

Tools Supported: FlexTest Scope: All modes Prerequisites: The Set Interrupt Handling command must be on and you must

interrupt a FlexTest command with a Control-C.

Usage

ABOrt INterrupted Process

Description

Aborts a command placed in suspended state by a Control-C interrupt while the Set Interrupt Handling command is on.

The Abort Interrupted Process command aborts a FlexTest command that you previously interrupted by pressing the Control-C keys. This removes the interrupted command from the suspend-state and returns control to FlexTest.

Examples

The following example enables the suspend-state interrupt handling, begins an ATPG run, and (sometime before the run completes) interrupts the run:

set interupt handling on set system mode atpg add faults -all run <Control-C>

Now with the Run suspended, the example continues by reporting all the untestable faults to the display and then aborts the Run:

report faults faultlist -class ut abort interrupted process

Related Commands

Resume Interrupted Process Set Interrupt Handling

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Command Dictionary Add Ambiguous Paths

Add Ambiguous Paths

Tools Supported: FastScan Scope: Atpg, Fault, and Good modes Prerequisites: This command supports the path delay fault model.

Usage

ADD AMbiguous Paths {path_name | -All} [-Max_paths number]

Description

Specifies for FastScan to select multiple paths when there is path ambiguity. When paths have path ambiguity, by default FastScan selects a single path that

satisfies the pin connectivity within the path definition file. If you want FastScan to have additional choices for path ambiguity, you can use the Add Ambiguous Paths command. When FastScan selects from the ambiguous paths it only considers the possible connectivity between points and does not attempt to determine whether the edges are sensitive.

For more information on path delay faults, refer to “Creating a Path Delay Test

Set” in the Scan and ATPG Process Guide.

Arguments

• path_name

A string that specifies the name of an ambiguous path that you want to add to the path list.

• -All

A switch specifying that you want to add all ambiguous paths into the path list.

• -Max_paths number

An optional switch and integer pair that specifies the maximum number of ambiguous paths you want FastScan to process. If you issue this command without this switch, the default maximum number of ambiguous paths is 10.

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Add Ambiguous Paths Command Dictionary

Examples

The following example loads in a path definition file and changes the maximum number of paths to five:

load paths add ambiguous paths -all -max_paths 5

Related Commands

Load Paths

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Command Dictionary Add Atpg Constraints

Add Atpg Constraints

Tools Supported: FastScan and FlexTest Scope: All modes Prerequisites: You can use this command only after the tool flattens the design to

the simulation model, which happens when you first attempt to exit Setup mode or when you issue the Flatten Model command.

Usage

For FastScan

ADD ATpg Constraints {0 | 1 | Z} {pin_pathname | gate_id# | function_name |

{-Cell cell_name {pin_name...}}}... [[-NOCapclock_check]

Dynamic | -Static]

For FlexTest

ADD ATpg Constraints {0 | 1 | Z} {pin_pathname | net_pathname | gate_id# |

function_name | {-Cell cell_name {{pin_name | net_name}...}}}...

Dynamic | -Static]

Description

Specifies that the tool restrict all patterns it places into the internal pattern set according to the user-defined constraints.

When the tool rejects a simulated pattern, it generates a message indicating the number of rejected patterns and the first gate at which the failure occurred. You can control the severity of the violation with the Set Contention Check command. If you set the checking severity to Error, the tool terminates the simulation if it rejects a pattern due to a user-defined constraint. You can analyze the simulation data up to the termination point by using the Report Gates command with the Error_pattern option.

When either FlexTest generates test patterns or FastScan generates test patterns using deterministic test generation methods, the tool ensures that it uses the userdefined pin constraints. When FastScan generates test patterns randomly, it does not have complete control over the highly automated process, which means that FastScan cannot ensure the use of the user-defined ATPG constraints. However, FastScan will reject non-conforming random patterns.

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Add Atpg Constraints Command Dictionary

If you change an ATPG constraint for a single internal set of patterns, the tool continues pattern compression using the new constraints, which can cause the tool to reject good patterns. Therefore, you should remove all ATPG constraints before compressing the pattern set.

If you constrain a pin by directly creating an ATPG constraint to the pin_pathname, and then create another constraint that

Note

indirectly creates a different constraint, the tool uses the constraint that directly specified the pin_pathname (overriding the global ATPG cell constraint).

The Add Atpg Constraints command allows you to change the ATPG constraints any time during the ATPG process (-Dynamic), affecting only the fault simulation and test generation that occurs after the constraint changes. The fault simulator rejects any subsequently simulated patterns that fail to meet the now current constraints.

Dynamic ATPG constraints do not affect DRC because of their temporary nature. Static ATPG constraints are unchangeable in ATPG mode, ensuring that DRC must be repeated if they are changed.

FlexTest Specifics

In addition to the functionality mentioned above, the Add Atpg Constraints command lets you constrain a net. Thus, if the circuit structure changes and the ATPG constraints specified on the net pathnames do not change, you do not have to identify the instance and the pin on which the ATPG constraints have to be applied. If any ATPG constraint is added to the net, the equivalent pin is found first and the function is added to that pin instead. Therefore, the Report Atpg Constraints command may not show the net pathname specified. The constraints added to the net can be deleted using the same net name.

Arguments

You must choose one of the following three literals to indicate the state value to which you want the tool to constrain the specified object:

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Command Dictionary Add Atpg Constraints

• 0 | 1 | Z

A literal that restricts the named object to a low state, high state, or high impedance state, respectively.

The following lists the four methods for naming the objects on which you wish to place the constraint. You can use any number of the four argument choices, in any order.

• pin_pathname

A repeatable string that specifies the pathname to the pin on which you are placing the constraint.

• net_pathname (FlexTest Only)

A repeatable string that specifies the pathname of the net on which you are placing the constraint. You cannot put ATPG constraints on a net in any library modules.

• gate_id#

A repeatable integer that specifies the gate identification number of the gate you wish to constrain.

• function_name

A repeatable string that specifies the name of a function you created with the Add Atpg Functions command. If you place a constraint on an ATPG function (that you generated with the Add Atpg Function -Cell command), then the tool also constrains all cells affected by that ATPG function. You can delete all these constraints using the function_name argument with the Delete Atpg Constraints command.

• -Cell cell_name {pin_name | net_name (FlexTest Only)}

A repeatable switch with a corresponding string pair that specifies the name of a DFT library cell and the name of a specific net (FlexTest Only) or pin on that cell. You can repeat the pin_name or net_name argument if there are multiple pins or nets on a cell that you need to constrain.

If you use the -Cell option, the tool places an ATPG constraint on every occurrence of that cell within the design. However, there is no -Cell option to the Delete Atpg Constraints command, so you can either delete them individually or delete all the ATPG constraints.

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Add Atpg Constraints Command Dictionary

• -Dynamic

An optional switch specifying that the tool only need satisfy the ATPG constraints during the ATPG process and not during design rules checking. You can change these constraints during the ATPG process, therefore, Design Rules Checking (DRC) does not check these constraints. This is the default behavior.

• -Static

An optional switch specifying that the tool (during all its processes) must always satisfy the ATPG constraint you are defining. You can only add or delete static ATPG constraints when you are in Setup mode, ensuring that the tool uses the static ATPG constraints for all ATPG analyses during design rules checking. DRC checks for any violations of ATPG constraints during the simulation of the test procedures (rule E12).

• -NOCapclock_check (FastScan Only)

An optional switch specifying that the tool suppress checking of specified ATPG constraints after the capture clock. By default, the tool checks ATPG constraints at the same time as bus contention. If, and only if, the tool performs contention checking after the capture clock, the tool also checks ATPG constraints after the capture clock.

In some situations, you may have some ATPG constraints that do not need to be checked after the capture clock, although you may want the tool to check other constraints and bus contention after the capture clock. In this case, you can use the -Nocapclock_check switch on certain constraints to suppress checking of those constraints after the capture clock.

Examples

The following example creates a user-defined ATPG function and then uses it when creating ATPG pin constraints:

add atpg functions and_b_in and /i$144/q /i$141/q /i$142/q add atpg constraints 0 /i$135/q add atpg constraints 1 and_b_in

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Command Dictionary Add Atpg Constraints

Related Commands

Add Atpg Functions Delete Atpg Constraints

Report Atpg Constraints

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Add Atpg Functions Command Dictionary

Add Atpg Functions

Tools Supported: FastScan and FlexTest Scope: All modes (except for some FlexTest options) Prerequisites: You can use this command only after the tool flattens the design to

the simulation model, which happens when you first attempt to exit Setup mode or when you issue the Flatten Model command.

Usage